ISL88013IH522Z-TK [INTERSIL]
5 Ld Voltage Supervisors with Adjustable Power-On Reset, Dual Voltage Monitoring or Watchdog Timer Capability; 5 Ld的电压监控器与可调节上电复位，双电压监控和看门狗定时器功能
| 型号： | ISL88013IH522Z-TK |
| 厂家： | 
Intersil |
| 描述： | 5 Ld Voltage Supervisors with Adjustable Power-On Reset, Dual Voltage Monitoring or Watchdog Timer Capability |
| 文件： | 总12页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL88011, ISL88012, ISL88013,
ISL88014, ISL88015
®
Data Sheet
December 14, 2006
FN8093.1
5 Ld Voltage Supervisors with Adjustable
Power-On Reset, Dual Voltage Monitoring
or Watchdog Timer Capability
Features
• Single/Dual Voltage Monitoring Supervisors
• Fixed-Voltage Options Allow Precise Monitoring of +2.5V,
+3.0V, +3.3V, and +5.0V Power Supplies
The ISL88011 through ISL88015 family of devices offer both
fixed and/or adjustable voltage-monitoring that combine
popular functions such as Power On Reset control,
Watchdog Timer, Supply Voltage Supervision, and Manual
Reset assertion in a small 5 Ld SOT-23 package.
• Dual Supervisor Has One Fixed Voltage Input and Another
That is User-Adjustable Down to 0.6V.
• Both RST and RST Outputs Available
• Adjustable POR Timeout Delay Options
Unique features on the ISL88013 and ISL88015 include a
watchdog timer with a 51s startup timeout and a 1.6s normal
timeout duration. On the ISL88011 and ISL88014, users can
increase the nominal 200ms Power On Reset timeout delay
• Watchdog Timer With 1.6s Normal and 51s Startup
Timeout Durations
• Manual Reset Input on All Devices
by adding an external capacitor to the C
pin. Both fixed
POR
and adjustable voltage monitors are provided by the
ISL88012. Complementary active-low and active-high reset
outputs are available on the ISL88011, ISL88012 and
ISL88013 devices. All devices provide manual reset
capability (see “Product Features Table” on page 4).
• Reset Signal Valid Down to V
DD
= 1V
• Accurate ±1.5% Voltage Threshold
• Immune to Power-Supply Transients
• Ultra Low 5.5µA Supply Current
Seven preprogrammed reset threshold voltages accurate to
±1.5% over temperature are offered (see “Ordering
Information” on page 3). The ISL88012, ISL88014 and
ISL88015 have a user-adjustable voltage input available for
custom monitoring of any voltage down to 0.6V. All parts are
specifically designed for low power consumption and high
threshold accuracy.
• Small 5 Ld SOT-23 Pb-Free Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Process Control Systems
• Intelligent Instruments
• Embedded Control Systems
• Computer Systems
• Critical µP and µC Power Monitoring
• Portable/Battery-Powered Equipment
• PDA and Handheld PC Devices
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Pinouts
ISL88011
(5 LD SOT-23)
TOP VIEW
ISL88012
(5 LD SOT-23)
TOP VIEW
RST/MR
GND
1
2
3
5
VDD
RST/MR
GND
1
2
3
5
VDD
RST
VMON
4
RST
CPOR
4
ISL88013
ISL88014
(5 LD SOT-23)
(5 LD SOT-23)
TOP VIEW
TOP VIEW
RST/MR
GND
1
2
3
5
4
VDD
WDI
RST/MR
GND
1
2
3
5
VDD
RST
VMON
CPOR
4
ISL88015
(5 LD SOT-23)
TOP VIEW
RST/MR
GND
1
2
3
5
4
VDD
WDI
VMON
FN8093.1
December 14, 2006
2
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Ordering Information
TEMPERATURE
PACKAGE
PART NUMBER
(Notes 1, 2)
PART
MARKING
V
V
RANGE
(°C)
TAPE AND REEL
(Pb-free)
PKG.
DWG. #
THVDD
(V)
THVMON
(V)
ISL88011IH546Z-TK
ISL88011IH544Z-TK
ISL88011IH531Z-TK
ISL88011IH529Z-TK
ISL88011IH526Z-TK
ISL88011IH523Z-TK
ISL88011IH522Z-TK
ISL88012IH546Z-TK
ISL88012IH544Z-TK
ISL88012IH531Z-TK
ISL88012IH529Z-TK
ISL88012IH526Z-TK
ISL88012IH523Z-TK
ISL88012IH522Z-TK
ISL88013IH546Z-TK
ISL88013IH544Z-TK
ISL88013IH531Z-TK
ISL88013IH529Z-TK
ISL88013IH526Z-TK
ISL88013IH523Z-TK
ISL88013IH522Z-TK
ISL88014IH5Z-TK
ISL88015IH5Z-TK
NOTES:
AGU
4.64
4.38
3.09
2.92
2.63
2.32
2.19
4.64
4.38
3.09
2.92
2.63
2.32
2.19
4.64
4.38
3.09
2.92
2.63
2.32
2.19
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23)
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
5 Ld SOT-23
P5.064
AGV
AGW
AGX
AGY
AGZ
AHE
AHF
AHG
AHH
AHI
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
P5.064
0.6 (Note 2)
0.6 (Note 2)
0.6 (Note 2)
0.6 (Note 2)
0.6 (Note 2)
0.6 (Note 2)
0.6 (Note 2)
N/A
AHJ
AHK
AHL
AHM
AHN
AHO
AHP
AHQ
AHR
AHS
AHT
AHU
N/A
N/A
N/A
N/A
N/A
N/A
0.6 (Note 2)
0.6 (Note 2)
N/A
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020
2. The voltage trip point can be adjusted to be greater than 0.6V using 2 external resistors. By default, the VTHVMON trip point is
0.6V if no external resistors are used.
FN8093.1
December 14, 2006
3
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Functional Block Diagrams
V
V
V
DD
DD
DD
RST/MR
PB
RST/MR
PB
RST/MR
PB
POR
OSC
POR
POR
OSC
±
V
±
±
±
V
V
V
DD
THMON
THMON
THMON
VMON
RST
RST
RST
C
POR
WDI
WDT
V
REF
GND
GND
GND
ISL88011
ISL88012
ISL88013
V
DD
V
DD
R
R
1
1
RST/MR
PB
RST/MR
PB
VMON
VMON
POR
V
POR
R
2
R
2
±
V
±
V
DD
THMON
THMON
OSC
WDT
C
POR
OSC
GND
GND
WDI
ISL88014
ISL88015
Product Features Table
FUNCTION
ISL88011
ISL88012
ISL88013
ISL88014
x
ISL88015
x
Active-Low Reset (RST)
x
x
x
x
x
x
x
Active-High Reset (RST)
Watchdog Timer (WDI)
x
Dual Voltage Supervision
x
Adjustable POR Timeout (C
Manual Reset Input (MR)
Fixed Trip Point Voltage
)
x
x
x
x
x
POR
x
x
x
x
x
x
x
Adjustable Trip Point Voltage
x
Pin Descriptions
PIN
ISL88011 ISL88012 ISL88013 ISL88014 ISL88015
NAME
RST/MR
GND
FUNCTION
1
2
1
2
4
3
1
2
1
2
3
1
2
3
Combined Active-Low Reset Output and Manual Reset Input
Ground
VMON
RST
Adjustable Threshold Voltage Input
Active-High Reset Output
3
4
3
4
5
C
Adjustable POR Timeout Delay Input
Watchdog Timer Input
POR
4
5
4
5
WDI
5
5
V
Supply Voltage and Monitored Input
DD
FN8093.1
December 14, 2006
4
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with respect to GND . . . . . . . . . . . .-1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . .+300°C
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
190
JA
5 Ld SOT-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOT-23 Lead Tips Only)
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
Pull-up Resistance (R ) . . . . . . . . . . . . . . . . . . . . . 5kΩ to 100kΩ
PU
CAUTION: Absolute Maximum Ratings indicate limits beyond which permanent damage to the device and impaired reliability may occur. These are stress ratings
provided for information only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification are not implied.
For guaranteed specifications and test conditions, see Electrical Specifications. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
NOTE:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Over the recommended operating conditions unless otherwise specified, R = 10kΩ.
PU
SYMBOL
PARAMETER
Supply Voltage Range
TEST CONDITIONS
MIN
TYP
MAX
5.5
11.5
10
UNITS
V
V
2.0
DD
I
Supply Current for ISL88011,
ISL88012, ISL88013
V
V
V
V
= 5.0V
8
µA
DD
DD
DD
DD
DD
= 3.3V
= 2.5V
= 3.3V
7
µA
5.5
4.5
9
µA
Supply Current for ISL88014,
ISL88015
8
µA
I
I
Input Leakage Current (VMON)
Output Leakage Current (VMON)
100
100
nA
nA
LI
LO
VOLTAGE THRESHOLDS
V Fixed V Voltage Trip Point
ISL88011, 88012, 88013IH546
ISL88011, 88012, 88013IH544
ISL88011, 88012, 88013IH531
ISL88011, 88012, 88013IH529
ISL88011, 88012, 88013IH526
ISL88011, 88012, 88013IH523
ISL88011, 88012, 88013IH522
4.57
4.31
3.04
2.88
2.59
2.29
2.16
4.64
4.38
3.09
2.92
2.63
2.32
2.19
46
4.71
4.45
3.14
2.96
2.67
2.35
2.22
V
THVDD
DD
V
V
V
V
V
V
V
Hysteresis at V
Input
V
V
V
V
V
V
V
= 4.64V
= 4.38V
= 3.09V
= 2.92V
= 2.63V
= 2.32V
= 2.19V
= 4.64V
= 4.38V
= 3.09V
= 2.92V
= 2.63V
= 2.32V
= 2.19V
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
THVDD
HYST
DD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
THVDD
44
31
29
26
23
22
V
Adj. Reset Voltage Trip Point (Note 4) V
599
597
589
589
589
597
597
594
605
603
595
595
595
603
603
600
611
609
601
601
601
609
609
606
THVMON
V
V
V
V
V
V
V
Adj. Reset Voltage Trip Point (Note 5)
THVMON
FN8093.1
December 14, 2006
5
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Electrical Specifications Over the recommended operating conditions unless otherwise specified, R = 10kΩ. (Continued)
PU
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Hysteresis Voltage (Notes 4, 5)
3
mV
THVMON
HYST
RESET
V
Reset Output Voltage Low
Reset Output Voltage High
V
V
V
V
≥ 3.3V, Sinking 0.5mA
< 3.3V, Sinking 0.5mA
≥ 3.3V, Sourcing 0.4mA
< 3.3V, Sourcing 0.4mA
0.05
0.05
0.40
0.40
V
V
OL
DD
DD
DD
DD
V
V
V
-0.6
V
V
-0.4
V
OH
DD
DD
DD
DD
-0.6
-0.4
V
t
t
V
to Reset Asserted Delay
TH
60
µs
ms
ms
pF
RPD
POR
POR Timeout Delay
ISL88012, ISL88013, ISL88015
ISL88011, ISL88014 with C
140
200
250
5
260
100
= OPEN
200
POR
C
Load Capacitance on Reset Pins
LOAD
MANUAL RESET
V
MR Input Voltage
0
1
mV
µs
MR
t
MR Minimum Pulse Width
MR
WATCHDOG TIMER (Note 6)
Start t
Startup Watchdog Timeout Period
Normal Watchdog Timeout Period
WDI Minimum Pulse Width
Watchdog Input Voltage Low
Watchdog Input Voltage High
Watchdog Input Current
32
1.0
100
51
64
sec
sec
ns
V
WDT
t
t
1.6
2.0
WDT
WDPS
V
V
0.3 x V
100
IL
DD
0.85 x V
DD
V
IH
I
nA
WDT
NOTES:
4. Applies to ISL88012
5. Applies to ISL88014 and ISL88015.
6. Applies to ISL88013 and ISL88015.
The device is designed with hysteresis to help prevent
chattering due to noise.
Pin Description
RST
VMON
The push-pull RST output is set to V
(HIGH) whenever 1)
DD
The VMON pin on the ISL88012, ISL88014 and ISL88015 is
a monitored input voltage that is user-adjustable. The
voltage at this pin is compared against an internal 600mV
the device is first powered up, 2) either V
VMON falls below their respective minimum voltage sense
levels, 3) MR is asserted or 4) the watchdog timeout expires.
or the voltage on
DD
reference voltage (V
whenever the monitored voltage falls below this trip point.
) and a reset is asserted
THVMON
RST/MR
This pin functions as both a reset output and a manual reset
input. The RST output functions identically to the
WDI
The Watchdog Input takes an input from a microprocessor
and ensures that it periodically toggles the WDI pin,
otherwise the internal watchdog timer runs out and reset is
asserted. The internal Watchdog Timer is cleared whenever
the WDI input pin sees a rising or falling edge or the device
is manually reset.
complementary RST output but is an open drain output that
is pulled to GND (LOW) when reset is asserted. The MR
input is an active-low debounced input to which a user can
connect a push-button to add manual reset capability or
drive with active low signal from a controller.
V
DD
The V
C
POR
pin is the power supply terminal. It is monitored by
DD
The C
input pin lets users increase the Power On Reset
the ISL88011, ISL88012 and ISL88013. For these devices,
the voltage at this pin is compared against an internal
POR
timeout delay (t
) by connecting a capacitor between
POR
and ground. (See Figure 3)
C
factory-programmed voltage trip point, V
. A reset is
POR
THVDD
first asserted when the device is initially powered up to
ensure that the power supply has stabilized. Thereafter,
reset is again asserted whenever V
falls below V .
THVDD
DD
FN8093.1
December 14, 2006
6
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
V
THVDD
V
DD
1V
V
THVMON
VMON
>t
MR
MR
t
t
t
t
t
t
POR
POR
RPD
POR
RPD
POR
RST
RST
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
The ISL88012, ISL88014 and ISL88015 allow users to
customize the minimum voltage sense level on the VMON
input pin. To do this, connect an external resistor divider
network to the VMON pin in order to set the trip point to
some voltage above 600mV according to the following
equation (See Figure 2):
Principles of Operation
The ISL88011 through ISL88015 devices provide those
functions needed for critical voltage monitoring. These
features include Power On Reset control, customizable
supply voltage supervision, Watchdog Timer capability, and
manual reset assertion. By integrating all of these features
into a small 5 Ld SOT-23 package and using only 5.5µA of
supply current, the ISL88011 through ISL88015 devices can
assist in lowering system cost, reducing board space
requirements, and increasing the reliability of a system.
(R + R )
1
R
2
2
(EQ. 1)
--------------------------
VINTRIP = 0.6 ×
Low Voltage Monitoring
During normal operation, these supervisors monitor both the
voltage level of V
(ISL88011, ISL88012, ISL88013) and/or
DD
R
VMON
1
ISL88012
ISL88014
ISL88015
VMON (ISL88012, ISL88014, ISL88015). The device asserts
a reset if any of these voltages falls below their respective
trip points. The reset signal effectively prevents the system
from operating during a power failure or brownout condition.
V
IN
R
2
This reset signal remains asserted until V
and the voltage
DD
on VMON exceed their voltage threshold setting for the reset
time delay period t
of 200ms (See Figure 1).
POR
FIGURE 2. USING VMON TO MONITOR V VIA RESISTORS
IN
FN8093.1
December 14, 2006
7
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Power On Reset (POR)
Manual Reset
Applying at least 1V to the V
which asserts reset (i.e. RST goes HIGH while RST goes
LOW). The reset signals remain asserted until the voltage at
pin activates a POR circuit
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active-low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for 1µs or longer
while the push-button is closed. After MR is released, the
DD
V
and/or VMON rise above the minimum voltage sense
DD
level for time period t
. This ensures that the voltages
POR
have stabilized.
These reset signals provide several benefits:
reset outputs remain asserted for t
released.
(200ms) and then
POR
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
V
DD
• It prevents the processor from operating prior to
stabilization of the oscillator.
R
ISL88011
ISL88012
ISL88013
ISL88014
ISL88015
pu
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
RST/MR
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
PB
Adjusting POR Timeout via C
POR
Pin
On the ISL88011 and ISL88014, users can adjust the Power
On Reset timeout delay (t ) up to many times the normal
POR
of 250ms. To do this, connect a capacitor between
t
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
POR
C
and ground (see Figure 3). For example, connecting a
POR
30pF capacitor to C
Watchdog Timer
will increase t
from a typical
POR
POR
250ms to about 2.5s. NOTE: Care should be taken in PCB
layout and capacitor placement in order to reduce stray
capacitance as much as possible, which lengthens the t
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t
(1.6s nominal),
POR
WDT
timeout period.
otherwise the reset signal is asserted (see Figure 5).
Internally, the 1.6s timer is cleared by either a reset or by
toggling the WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for startup.
During this time, a reset cannot be asserted due to the WDI
not being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the
system software to initialize without the burden of dealing
with the Watchdog.
C
POR
ISL88011
ISL88014
Symbol Table
6
5
4
3
2
1
0
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
0
10
20
30
40
50
60
70
80
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
C
(pF)
POR
N/A
Center Line
is High
Impedance
FIGURE 3. ADJUSTING t
WITH A CAPACITOR
POR
FN8093.1
December 14, 2006
8
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
V
THVDD
V
DD
1V
<t
WDT
<t
WDT
STARTt
WDT
START t
WDT
t
WDT
WDI
RST
RST
>t
WDPS
t
POR
t
POR
FIGURE 5. WATCHDOG TIMING DIAGRAM
Typical Parametric Performance Curves
4.70
4.65
4.60
4.55
4.50
4.45
4.40
11
10
Vth_VDD = 4.64V
VDD = 5V
9
8
VDD = 3.3V
7
VDD = 2.5V
6
5
Vth_VDD = 4.38V
4.35
4.30
-45
85 95
45 55 65 75
-35 -25 -15
0
15 25 35
-45 -35 -25 -15
0
15 25 35 45 55 65 75 85 95
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. V
, V = 5V vs TEMPERATURE
THVDD DD
FIGURE 6. I
(ISL88011, ISL88012, ISL88013) vs
DD
TEMPERATURE
2.40
2.35
2.30
2.25
2.20
2.15
2.10
3.20
3.10
3.00
2.90
2.80
2.70
2.60
VTH_VDD = 3.09V
Vth_VDD = 2.32V
VTH_VDD = 2.92V
Vth_VDD = 2.19V
VTH_VDD = 4.38V
2.50
2.40
-45 -35 -25 -15
0
15 25 35 45 55 65 75 85 95
-45 -35 -25 -15
0
15 25 35 45 55 65 75 85 95
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. V
V
= 2.5V vs. TEMPERATURE
THVDD, DD
FIGURE 8. V
V
= 3.3V vs TEMPERATURE
THVDD, DD
FN8093.1
December 14, 2006
9
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Typical Parametric Performance Curves (Continued)
0.608
0.606
0.604
0.602
0.600
0.598
0.596
230
225
220
215
210
205
200
-45
85 95
-45
85 95
45 55 65 75
-35 -25 -15
0
45 55 65 75
-35 -25 -15
0
15 25 35
15 25 35
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. t
(C OPEN) vs TEMPERATURE
POR POR
FIGURE 10. V
vs TEMPERATURE
THVMON
Typical Application Circuits
12V
12V
12V SUPPLY
10k
180k
44k
100k
V
RESET
DD
PGOOD @ 10.8V
PGOOD @ 10.8V
RST
RST
RST
VMON
V
DD
0.1µF
10k
10k
4.7V
V
@ 11.4V
TH
ISL88014 / ISL88015
ISL88011IH531Z
FIGURE 13. 12V SUPPLY PGOOD or PGOOD
FIGURE 12. HIGH ACCURACY 12V SUPPLY MONITOR
+5V
12V
5V
100k
100k
PGOOD
100k
100k
V
DD
V
100k
DD
180k
RST
RST
RST
V
@ 11.4V
TH
V2MON
GND
VMON
V
@ 4.4V
TH2
-5V
6.81k
10k
ISL88012IH546Z
-5V
ISL88012
PGOOD = HIGH IF -V < -4.6V AND -V + +V > 9.4 (abs)
FIGURE 15. +5V AND -5V MONITOR
FIGURE 14. MONITOR 5V AND 12V SUPPLIES
FN8093.1
December 14, 2006
10
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Typical Application Circuits (Continued)
3.3V
3.3V
V
@ 3.09V
THL
V
DD
100k
PGOOD
RST
50k
ISL8801X-31
3.3V
V
100k
DD
V
@ 3.6V
RST
THH
VMON
10K
ISL88014/ISL88015
VOLTAGE OUT OF RANGE = P
LOW
GOOD
FIGURE 16. OVER/UNDERVOLTAGE MONITOR
FN8093.1
December 14, 2006
11
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Small Outline Transistor Plastic Packages (SOT23-5)
D
P5.064
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e1
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.057
0.0059
0.051
0.020
0.018
0.009
0.008
0.118
0.118
0.067
MIN
0.90
0.00
0.90
0.30
0.30
0.08
0.08
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.50
0.45
0.22
0.20
3.00
3.00
1.70
NOTES
5
1
4
A
A1
A2
b
0.036
0.000
0.036
0.012
0.012
0.003
0.003
0.111
0.103
0.060
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
α
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0374 Ref
0.0748 Ref
0.014 0.022
0.95 Ref
1.90 Ref
0.35 0.55
A2
A1
A
e1
L
-
-C-
4
L1
L2
N
0.024 Ref.
0.010 Ref.
5
0.60 Ref.
0.25 Ref.
5
0.10 (0.004) C
5
b
WITH
R
0.004
-
0.10
-
PLATING
b1
R1
α
0.004
0.010
0.10
0.25
o
o
o
o
0
8
0
8
-
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8093.1
December 14, 2006
12
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