ISL83204A [INTERSIL]
60V/2.5A Peak, High Frequency Full Bridge FET Driver; 60V / 2.5A峰值，高频全桥FET驱动器
| 型号： | ISL83204A |
| 厂家： | 
Intersil |
| 描述： | 60V/2.5A Peak, High Frequency Full Bridge FET Driver |
| 文件： | 总15页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL83204A
®
Data Sheet
March 20, 2007
FN6397.2
60V/2.5A Peak, High Frequency Full Bridge
FET Driver
Features
• Drives N-Channel FET Full Bridge Including High Side
Chop Capability
The ISL83204A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The ISL83204A includes an input
comparator used to facilitate the “hysteresis” and PWM
modes of operation. Its HEN (high enable) lead can force
current to freewheel in the bottom two external power
MOSFETs, maintaining the upper power MOSFETs off.
Since it can switch at frequencies up to 1MHz, the
ISL83204A is well suited for driving Voice Coil Motors,
switching power amplifiers and power supplies.
• Bootstrap Supply Max Voltage to 75VDC
• Drives 1000pF Load at 1MHz in Free Air at +50°C with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
• DIS (Disable) Pin Pulls Gates Low
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
ISL83204A can also drive medium voltage brush motors,
and two ISL83204As can be used to drive high performance
stepper motors, since the short minimum “on-time” can
provide fine micro-stepping capability.
• Very Low Power Consumption
• Undervoltage Protection
Short propagation delays of approximately 55ns maximize
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• Uninterruptible Power Supplies
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
Ordering Information
TEMP
PART
NUMBER
PART
MARKING
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL83204AIPZ ISL83204AIPZ -40 to +85 20 Ld PDIP E20.3
(Note) (Pb-Free)
ISL83204AIBZ* ISL83204AIBZ -40 to +85 20 Ld SOIC M20.3
(Note)
(Pb-Free)
*Add “-T” suffix for tape and reel.
Pinout
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL83204A
(20 LD PDIP, 20 LD SOIC)
TOP VIEW
1
2
20
19
BHO
BHS
BHB
HEN
DIS
3
18 BLO
V
BLS
4
17
16
15
14
13
12
11
SS
OUT
IN+
V
5
DD
V
6
CC
IN-
ALS
ALO
7
HDEL
LDEL
AHB
8
AHS
AHO
9
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL83204A
Application Block Diagram
60V
12V
BHO
BHS
BLO
LOAD
HEN
DIS
ISL83204A
IN+
IN-
ALO
AHS
AHO
GND
GND
Functional Block Diagram (1/2 ISL83204A)
AHB
HIGH VOLTAGE BUS ≤ 60VDC
10
11
DRIVER
UNDER-
VOLTAGE
AHO
AHS
CHARGE
PUMP
LEVEL SHIFT
AND LATCH
C
BS
16
2
V
DD
12
HEN
TURN-ON
DELAY
TO V
(PIN 16)
DD
D
BS
DIS
3
V
CC
15
5
6
7
8
9
4
OUT
IN+
DRIVER
+12VDC
BIAS
SUPPLY
ALO
ALS
TURN-ON
DELAY
13
14
+
-
C
BF
_
IN
HDEL
LDEL
V
SS
FN6397.2
March 20, 2007
2
ISL83204A
Typical Application (Hysteresis Mode Switching)
60V
1
2
20
19
18
17
16
15
BHB
HEN
DIS
BHO
BHS
BLO
BLS
12V
DIS
LOAD
3
4
V
SS
5
OUT
IN+
V
V
DD
CC
6
6V
IN
12V
IN-
7
ALS 14
ALO 13
HDEL
LDEL
AHB
8
9
12
11
AHS
AHO
10
GND
-
+
6V
GND
FN6397.2
March 20, 2007
3
ISL83204A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
and V . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
CC
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
JA
DD
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
DD
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation at +85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only)
85
75
Voltage on AHS, BHS . -6.0V (Transient) to 70V (+25°C to +125°C)
Voltage on AHS, BHS . .-6.0V (Transient) to 70V (-55°C to +125°C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . V
-0.3V to V +V
AHS, BHS
AHS, BHS DD
Voltage on ALO, BLO. . . . . . . . . . . . .V
ALS, BLS
-0.3V to V
+0.3V
+0.3V
CC
Voltage on AHO, BHO . . . . . . V
-0.3V to V
AHS, BHS
AHB, BHB
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
All Voltages relative to V , unless otherwise specified.
SS
Operating Conditions
Supply Voltage, V
and V . . . . . . . . . . . . . . . . . . +9.5V to +15V
CC
DD
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . .V +5V to V +15V
AHS, BHS AHS, BHS
Voltage on AHs, BHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500μA to -50μA
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications
V
= V
= V
AHB
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V = 0V, R
BHS HDEL
= R = 100k, and
LDEL
DD
CC
BHB
BLS
T
= +25°C, Unless Otherwise Specified
A
T
= +25°C
TYP
T = -40°C to +125°C
J
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
V
V
Quiescent Current
Operating Current
I
IN- = 2.5V, Other Inputs = 0V
8
8
11
12
14
15
7
8
14
15
mA
mA
DD
DD
DD
I
Outputs switching f = 500kHz, No
Load
DDO
V
V
Quiescent Current
Operating Current
I
IN- = 2.5V, Other Inputs = 0V,
-
25
80
-
100
μA
CC
CC
CC
I
= I
= 0
BLO
ALO
I
f = 500kHz, No Load
1
1.25
-25
2.0
-11
0.8
-60
3
mA
CCO
, I
AHB, BHB Quiescent
Current -Qpump Output
Current
I
IN- = 2.5V, Other Inputs = 0V,
-50
-10
μA
AHB BHB
I
= I = 0,
AHO BHO
V
= V =V
CC AHB
= V = 10V
BHB
DD
AHB, BHB Operating
Current
I
I
,
f = 500kHz, No Load
0.62
-
1.2
1.5
1.0
0.5
-
1.9
10
mA
μA
V
AHBO
BHBO
AHS, BHS, AHB, BHB
Leakage Current
I
V
= V
= V
= 60V,
= 75V
0.02
12.6
HLK
BHS
AHS
BHB
V
AHB
AHB-AHS, BHB-BHS
Qpump Output Voltage
V
V
- V
I
= I = 0, No Load
AHB
11.5
14.0
10.5
14.5
AHB
BHB
AHS AHB
- V
BHS
INPUT COMPARATOR PINS: IN+, IN-, OUT
Offset Voltage
V
Over Common Mode Voltage
Range
-10
0
+10
-15
+15
mV
OS
Input Bias Current
Input Offset Current
I
0
-1
1
0.5
0
2
0
-2
1
4
μA
μA
V
IB
I
+1
+2
OS
Input Common Mode
Voltage Range
CMVR
-
V
- 1.5
V
- 1.5
DD
DD
FN6397.2
March 20, 2007
4
ISL83204A
Electrical Specifications
V
= V
= V
AHB
= V
= 12V, V = V
= V
= V
AHS
= V = 0V, R
BHS HDEL
= R = 100k, and
LDEL
DD
CC
BHB
SS
ALS
BLS
T
= +25°C, Unless Otherwise Specified (Continued)
A
T
= +25°C
T = -40°C to +125°C
J
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
25
-
MAX
MIN
MAX
UNITS
V/mV
V
Voltage Gain
AVOL
-
-
-
-
-
-
OUT High Level Output
Voltage
V
IN+ >IN-, I
OH
= -250μA
V
- 0.4
V
- 0.5
DD
OH
DD
OUT Low Level Output
Voltage
V
IN+ <IN-, I = +250μA
OL
-
-
0.4
-
0.5
V
OL
Low Level Output Current
High Level Output Current
INPUT PINS: DIS
I
V
V
= 6V
= 6V
6.5
-17
14
19
-3
6
20
mA
mA
OL
OUT
I
-10
-20
-2.5
OH
OUT
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
High Level Input Current
INPUT PINS: HEN
V
Full Operating Conditions
Full Operating Conditions
-
2.5
-
-
-
1.0
-
-
2.7
-
0.8
-
V
V
IL
V
IH
35
-100
-
-
-
mV
μA
μA
I
V
V
= 0V, Full Operating Conditions
= 5V, Full Operating Conditions
-130
-1
-75
+1
-135
-10
-65
+10
IL
IN
I
IH
IN
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
High Level Input Current
V
Full Operating Conditions
Full Operating Conditions
-
2.5
-
-
-
1.0
-
-
2.7
-
0.8
-
V
V
IL
V
IH
35
-200
-
-
-
mV
μA
μA
I
V
V
= 0V, Full Operating Conditions
= 5V, Full Operating Conditions
-260
-1
-150
+1
-270
-10
-130
+10
IL
IN
I
IH
IN
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage
V
V
I
= I = -100μA
LDEL
4.9
5.1
5.3
4.8
5.4
V
HDEL,
HDEL
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 100mA
= -100mA
0.7
0.8
1.7
1.7
8.1
0.85
0.95
2.6
1.0
1.1
3.8
3.3
9.4
0.5
0.5
1.4
1.3
8.0
1.1
1.2
4.1
3.6
9.5
V
V
A
A
V
OL
- V
OUT
OUT
V
CC
OH
I +
V
V
= 0V
O
OUT
OUT
Peak Pulldown Current
I -
O
= 12V
2.4
Under Voltage, Rising
Threshold
UV+
8.8
Under Voltage, Falling
Threshold
UV-
7.6
8.3
0.4
8.9
7.5
0.2
9.0
0.7
V
V
Under Voltage, Hysteresis
HYS
0.25
0.65
FN6397.2
March 20, 2007
5
ISL83204A
Switching Specifications
V
C
= V
= V
AHB
= V
= 12V, V = V
= V
= V
AHS
= V
BHS
= 0V, R
HDEL
= R = 10k,
LDEL
DD
CC
BHB
SS
ALS
BLS
= 1000pF, and T = +25°C, Unless Otherwise Specified
L
A
T
= +25°C
T = - 40°C to +125°C
J
J
PARAMETERS
SYMBOL
TEST CONDITIONS MIN TYP MAX
MIN
MAX
90
110
90
140
35
35
-
UNITS
ns
Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO)
Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO)
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO)
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO)
Rise Time
t
-
-
40
50
40
70
10
10
-
70
80
70
110
25
25
-
-
-
LPHL
t
ns
HPHL
t
-
-
ns
LPLH
t
-
-
ns
HPLH
t
-
-
ns
R
Fall Time
t
-
-
ns
F
Turn-on Input Pulse Width
t
50
40
-
50
40
-
ns
PWIN-ON
Turn-off Input Pulse Width
t
-
-
-
ns
PWIN-OFF
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
t
45
75
95
ns
DISLOW
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
t
-
-
55
45
85
70
-
-
105
90
ns
ns
DISHIGH
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
t
DLPLH
Refresh Pulse Width (ALO and BLO)
t
240 380 500
200
600
750
90
ns
ns
ns
ns
REF-PW
Disable to Upper Enable (DIS - AHO and BHO)
HEN-AHO, BHO Turn-off, Propagation Delay
HEN-AHO, BHO Turn-on, Propagation Delay
t
-
-
-
480 630
-
-
-
UEN
t
t
R
R
= R
= R
= 10k
= 10k
40
60
70
90
HEN-PHL
HEN-PLH
HDEL
LDEL
110
HDEL
LDEL
TRUTH TABLE
INPUT
OUTPUT
IN+ >IN-
HEN
U/V
X
0
DIS
ALO
AHO
BLO
BHO
X
0
1
0
1
X
X
0
1
1
0
X
1
0
0
0
0
X
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
FN6397.2
March 20, 2007
6
ISL83204A
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
3
HEN
DIS
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than V ).
DD
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than V ).
DD
4
5
6
V
Chip negative supply, generally will be ground.
SS
OUT
IN+
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).
7
8
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
HDEL
High-side turn-on DELay. Connect resistor from this pin to V to set timing current that defines the turn-on delay of
SS
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9
LDEL
AHB
Low-side turn-on DELay. Connect resistor from this pin to V to set timing current that defines the turn-on delay of
SS
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no
shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
12
AHO
AHS
A High-side Output. Connect to gate of A High-side power MOSFET.
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13
14
15
16
17
18
19
ALO
ALS
A Low-side Output. Connect to gate of A Low-side power MOSFET.
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
V
V
Positive supply to gate drivers. Must be same potential as V
(Pin 16). Connect to anodes of two bootstrap diodes.
CC
DD
DD
Positive supply to lower gate drivers. Must be same potential as V
(Pin 15). De-couple this pin to V (Pin 4).
SS
CC
BLS
BLO
BHS
B Low-side Source connection. Connect to source of B Low-side power MOSFET.
B Low-side Output. Connect to gate of B Low-side power MOSFET.
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
FN6397.2
March 20, 2007
7
ISL83204A
Timing Diagrams
t
DT
t
HPHL
t
LPLH
U/V = DIS
0
1
HEN
IN+ > IN-
ALO
AHO
BLO
BHO
t
HPLH
t
LPHL
t
t
F
R
t
DT
(10% - 90%) (90% - 10%)
FIGURE 1. BI-STATE MODE
t
t
HEN-PLH
HEN-PHL
U/V = DIS
0
HEN
IN+ > IN-
ALO
AHO
BLO
BHO
FIGURE 2. HIGH SIDE CHOP MODE
t
t
DLPLH
DIS
t
REF-PW
U/V or DIS
HEN
IN+ > IN-
ALO
AHO
BLO
BHO
t
UEN
FIGURE 3. DISABLE FUNCTION
FN6397.2
March 20, 2007
8
ISL83204A
Typical Performance Curves V = V = V
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V = 0V,
BHS
DD
R
CC
= R
AHB
BHB
BLS
= 100k, and T = +25°C, Unless Otherwise Specified.
LDEL A
HDEL
13.0
12.5
12.0
11.5
11.0
10.5
10.0
14
12
10
8
6
4
2
8
10
V
12
SUPPLY VOLTAGE (V)
14
0
200k
400k
600k
800k
1M
SWITCHING FREQUENCY (Hz)
DD
FIGURE 4. QUIESCENT I
SUPPLY CURRENT vs V
FIGURE 5. I
NO-LOAD I
SUPPLY CURRENT vs
DD
DD
SUPPLY VOLTAGE
DD
DDO
FREQUENCY (Hz)
5
4
3
2
1
0
+125°C
20
15
10
5
+75°C
+25°C
0°C
-40°C
0
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
FIGURE 7. I
, NO-LOAD I
SUPPLY CURRENT vs
CC
CCO
FREQUENCY (Hz) TEMPERATURE
2.5
1.0
2.0
1.5
1.0
0.5
0.5
0.0
-40
-20
0
20
40
60
80
100
120
0
200k
400k
600k
800k
1M
SWITCHING FREQUENCY (Hz)
JUNCTION TEMPERATURE (°C)
FIGURE 8. I
, I
NO-LOAD FLOATING SUPPLY BIAS
FIGURE 9. COMPARATOR INPUT CURRENT I vs
L
AHB BHB
CURRENT vs FREQUENCY
TEMPERATURE AT V
= 5V
CM
FN6397.2
March 20, 2007
9
ISL83204A
Typical Performance Curves V = V = V
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V
= 0V,
BHS
DD
R
CC
= R
AHB
BHB
BLS
= 100k, and T = +25°C, Unless Otherwise Specified. (Continued)
HDEL
LDEL
A
-90
-100
-110
-120
-180
-190
-200
-210
-220
-230
-50
-25
0
25
50
75
100
125
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 10. DIS LOW LEVEL INPUT CURRENT I vs
IL
FIGURE 11. HEN LOW LEVEL INPUT CURRENT I vs
IL
TEMPERATURE
TEMPERATURE
80
15
70
60
50
40
30
14
13
12
11
10
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION
DELAY t vs TEMPERATURE
DISHIGH
80
70
60
50
40
30
525
500
475
450
425
-50
-25
0
25
50
75
100
125 150
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 14. DISABLE TO UPPER ENABLE t
UEN
FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION
DELAY t vs TEMPERATURE
PROPAGATION DELAY vs TEMPERATURE
DISLOW
FN6397.2
March 20, 2007
10
ISL83204A
Typical Performance Curves V = V = V
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V
= 0V,
BHS
DD
R
CC
= R
AHB
BHB
BLS
= 100k, and T = +25°C, Unless Otherwise Specified. (Continued)
HDEL
LDEL A
80
70
60
50
40
30
20
450
425
400
375
350
-50
-25
0
25
50
75
100
125 150
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 16. tT
REFRESH PULSE WIDTH vs
TEMPERATURE
FIGURE 17. DISABLE TO LOWER ENABLE t
REF-PW
DLPLH
PROPAGATION DELAY vs TEMPERATURE
90
80
70
60
50
40
90
80
70
60
50
40
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY t
vs TEMPERATURE
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY t
vs TEMPERATURE
HPHL
HPLH
90
80
70
60
50
40
90
80
70
60
50
40
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY t
vs TEMPERATURE
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY t
vs TEMPERATURE
LPHL
LPLH
FN6397.2
March 20, 2007
11
ISL83204A
Typical Performance Curves V = V = V
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V
= 0V, R
HDEL
= R
=
DD
CC
AHB
BHB
BLS
BHS
LDEL
100K, and T = +25°C, Unless Otherwise Specified.
A
13.5
12.5
11.5
10.5
9.5
13.5
12.5
11.5
10.5
9.5
8.5
8.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 22. GATE DRIVE FALL TIME t vs TEMPERATURE
F
FIGURE 23. GATE DRIVE RISE TIME t vs TEMPERATURE
R
1500
1250
1000
6.0
5.5
5.0
4.5
4.0
750
-40°C
0°C
+25°C
+75°C
+125°C
500
250
0
10
12
14
-40
-20
0
20
40
60
80
100
120
BIAS SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 24. V
, V
VOLTAGE vs TEMPERATURE
FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, V
CC
- V
vs
LDEL HDEL
OH
BIAS SUPPLY AND TEMPERATURE AT 100μA
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1500
1250
1000
750
-40°C
500
250
0
0°C
+25°C
+75°C
+125°C
6
7
8
9
10
11
12
, V
13
14
15
16
10
12
BIAS SUPPLY VOLTAGE (V)
14
V
, V , V
(V)
CC DD AHG BHB
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE V vs BIAS
OL
FIGURE 27. PEAK PULLDOWN CURRENT I BIAS SUPPLY
O-
SUPPLY AND TEMPERATURE AT 100μA
VOLTAGE
FN6397.2
March 20, 2007
12
ISL83204A
Typical Performance Curves V = V = V
= V
= 12V, V = V
SS ALS
= V
= V
AHS
= V = 0V, R
BHS HDEL
= R =
LDEL
DD
CC
AHB
BHB
BLS
100K, and T = +25°C, Unless Otherwise Specified. (Continued)
A
500
200
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10,000
3,000
1,000
100
100
50
20
10
5
2
1
0.5
0.2
0.1
6
7
8
9
10
11
12
, V
13
14
15
16
1k
2k
5k 10k 20k
50k 100k 200k 500k 1M
V
, V , V
(V)
SWITCHING FREQUENCY (Hz)
CC DD ABH BHB
FIGURE 28. PEAK PULLUP CURRENT I vs SUPPLY
O+
FIGURE 29. LOW VOLTAGE BIAS CURRENT I
AND I
CC
DD
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE
VOLTAGE
9.0
8.8
8.6
1000
500
UV+
200
100
50
UV-
8.4
8.2
20
10
50
25
0
25
50
75
100
125
150
10k
20k
50k
100k
200k
500k
1M
SWITCHING FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
150
120
90
60
30
0
10
50
100
150
200
250
HDEL/LDEL RESISTANCE (kΩ)
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
FN6397.2
March 20, 2007
13
ISL83204A
Dual-In-Line Plastic Packages (PDIP)
N
E20.3 (JEDEC MS-001-AD ISSUE D)
E1
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INDEX
AREA
1
2
3
N/2
INCHES
MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
C
0.015
0.115
0.014
0.045
0.008
0.980
0.005
0.300
0.240
0.39
2.93
0.356
1.55
0.204
24.89
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
1.060
-
4.95
0.558
1.77
0.355
26.9
-
-
SEATING
PLANE
-
L
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
0.325
0.280
8.25
7.11
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
20
20
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN6397.2
March 20, 2007
14
ISL83204A
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.35
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.014
0.1043
0.0118
0.019
-
0.30
-
1
2
3
L
0.49
9
SEATING PLANE
A
0.0091
0.4961
0.2914
0.0125
0.32
-
-A-
0.5118 12.60
13.00
7.60
3
D
h x 45°
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
M
M
S
B
0.25(0.010)
C
A
N
α
20
20
7
0°
8°
0°
8°
-
NOTES:
Rev. 2 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6397.2
March 20, 2007
15
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