ISL6553CB-T_技术文档

ISL6553

TM

Data Sheet

November 2000

File Number 4931

Microprocessor CORE Voltage Regulator

Multi-Phase Buck PWM Controller

Features

• Multi-Phase Power Conversion

The ISL6553 multi-phase PWM control IC together with its

companion gate drivers, the HIP6601, HIP6602 or HIP6603

and Intersil MOSFETs provides a precision voltage

regulation system for advanced microprocessors. Multi-

phase power conversion is a marked departure from earlier

single phase converter conﬁgurations previously employed

to satisfy the ever increasing current demands of modern

microprocessors. Multi-phase converters, by distributing the

power and load current results in smaller and lower cost

transistors with fewer input and output capacitors. These

reductions accrue from the higher effective conversion

frequency with higher frequency ripple current due to the

phase interleaving process of this topology. For example, a

two phase converter operating at 350kHz will have a ripple

frequency of 700kHz. Moreover, greater converter

bandwidth of this design results in faster response to load

transients.

• Precision Channel Current Sharing

- Loss Less Current Sampling - Uses r

DS(ON)

• Precision CORE Voltage Regulation

- ±1% System Accuracy Over Temperature

• Microprocessor Voltage Identiﬁcation Input

- 5-Bit VID Input

- 1.05V to 1.825V in 25mV Steps

- Programmable “Droop” Voltage

• Fast Transient Recovery Time

• Over Current Protection

• High Ripple Frequency, (Channel Frequency) Times

Number Channels . . . . . . . . . . . . . . . . . 100kHz to 3MHz

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Outstanding features of this controller IC include

programmable VID codes from the microprocessor that

range from 1.05V to 1.825V with a system accuracy of ±1%.

Pull up currents on these VID pins eliminates the need for

external pull up resistors. In addition “droop” compensation,

used to reduce the overshoot or undershoot of the CORE

voltage, is easily programmed with a single resistor.

Ordering Information

o

PART NUMBER

TEMP. ( C)

PACKAGE

PKG. NO.

ISL6553CB

0 to 70

16 Ld SOIC

M16.15

ISL6553CB-T

ISL6553EVAL1

16 Ld SOIC Tape and Reel

Evaluation Platform

Another feature of this controller IC is the PGOOD monitor

circuit which is held low until the CORE voltage increases,

during its Soft-Start sequence, to within 10% of the

programmed voltage. Over-voltage, 15% above programmed

CORE voltage, results in the converter shutting down and

turning the lower MOSFETs ON to clamp and protect the

microprocessor. Under voltage is also detected and results

in PGOOD low if the CORE voltage falls 10% below the

programmed level. Over-current protection reduces the

regulator RMS output current to 41% of the programmed

over-current trip value. These features provide monitoring

and protection for the microprocessor and power system.

Pinout

ISL6553 (SOIC)

TOP VIEW

VID3

1

2

3

4

5

6

7

8

16 VCC

VID2

VID1

15 PGOOD

14 ISEN1

13 PWM1

12 PWM2

11 ISEN2

10 VSEN

VID0

VID25mV

COMP

FB

FS/DIS

9

GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

ISL6553

Block Diagram

PGOOD

VCC

POWER-ON

RESET (POR)

THREE

STATE

VSEN

+

UV

-

OV

LATCH

X 0.9

CLOCK AND

S

SAWTOOTH

GENERATOR

FS/EN

+

OVP

-

X1.15

+

SOFT-

+

∑

START

AND FAULT

LOGIC

PWM

-

PWM1

-

COMP

VID3

VID2

VID1

VID0

+

∑

PWM

PWM2

-

D/A

+

E/A

-

VID25mV

FB

CURRENT

CORRECTION

I_TOT

+

ISEN1

ISEN2

+

∑

OC

+

-

I_TRIP

GND

Simpliﬁed Power System Diagram

VSEN

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 1

ISL6553

MICROPROCESSOR

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 2

VID

2

ISL6553

Channel frequency, F , select and disable. A resistor from

this pin to ground sets the switching frequency of the

Functional Pin Description

SW

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

1

2

3

4

5

6

7

8

16

VCC

VID3

VID2

15 PGOOD

14 ISEN1

13 PWM1

12 PWM2

11 ISEN2

10 VSEN

VID1

GND (Pin 9)

VID0

Bias and reference ground. All signals are referenced to this

pin.

VID25mV

COMP

FB

VSEN (Pin 10)

Power good monitor input. Connect to the microprocessor-

CORE voltage.

FS/DIS

9

GND

ISEN2 (Pin 11) and ISEN1 (Pin 14)

VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)

and VID25mV (Pin 5)

Current sense inputs from the individual converter channel’s

phase nodes.

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The ISL6553 decodes

VID bits to establish the output voltage. See Table 1.

PWM2 (Pin 12) and PWM1 (Pin 13)

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601/2/3 driver.

COMP (Pin 6)

PGOOD (Pin 15)

Output of the internal error ampliﬁer. Connect this pin to the

external feedback and compensation network.

Power good. This pin provides a logic-high signal when the

microprocessor CORE voltage (VSEN pin) is within speciﬁed

limits and Soft-Start has timed out.

FB (Pin 7)

Inverting input of the internal error ampliﬁer.

VCC (Pin 16)

FS/DIS (Pin 8)

Bias supply. Connect this pin to a 5V supply.

Typical Application - Two Phase Converter Using HIP6601 Gate Drivers

+12V

V

= +5V

IN

BOOT

UGATE

PVCC

VCC

PHASE

DRIVER

HIP6601

+V

CORE

+5V

PWM

LGATE

GND

COMP

VCC

FB

+12V

VSEN

V

= +5V

IN

BOOT

PGOOD

VID3

PWM2

ISEN2

PVCC

VCC

UGATE

PHASE

VID2

VID1

MAIN

CONTROL

ISL6553

DRIVER

HIP6601

VID0

LGATE

GND

PWM

PWM1

VID25mV

FS/DIS

GND

ISEN1

3

ISL6553

Typical Application - Two Phase Converter Using an HIP6602 Gate Driver

+5V

V

= +12V

IN

+12V

BOOT1

UGATE1

PHASE1

FB

COMP

VCC

L

01

VCC

VSEN

ISEN1

PWM1

LGATE1

PVCC

PGOOD

VID3

PWM1

+V

CORE

DUAL

DRIVER

HIP6602

MAIN

+5V

VID2

CONTROL

ISL6553

V

+12V

IN

VID1

VID0

BOOT2

PWM2

UGATE2

PHASE2

PWM2

L

02

VID25mV

ISEN2

FS/DIS

LGATE2

GND

4

ISL6553

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V

Input, Output, or I/O Voltage . . . . . . . . . GND -0.3V to V + 0.3V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD

Thermal Resistance (Typical, Note 1)

θ

( C/W)

JA

VCC

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

106

o

Recommended Operating Conditions

(SOIC - Lead Tips Only)

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

o

Electrical Speciﬁcations Operating Conditions: VCC = 5V, T = 0 C to 70 C, Unless Otherwise Speciﬁed

A

PARAMETER

INPUT SUPPLY POWER

Input Supply Current

TEST CONDITIONS

MIN

TYP MAX UNITS

R

= 100kΩ, Active and Disabled Maximum Limit

-

10

15

4.5

mA

V

T

POR (Power-On Reset) Threshold

VCC Rising

VCC Falling

4.25

3.75

4.38

3.88

4.00

V

REFERENCE AND DAC

DAC Voltage Accuracy

DAC Pin Input Low Voltage Threshold

DAC Pin Input High Voltage Threshold

VID Pull-Up

-1

-

1

0.8

-

%

V

2.0

10

-

V

VIDx = 0V or VIDx = 3V

20

40

µA

OSCILLATOR

Frequency, F

R

= 100kΩ, ±1%

T

245

0.05

-

275

305

1.5

1.0

kHz

MHz

V

SW

Adjustment Range

See Figure 10

-

Disable Voltage

Maximum Voltage at FS/DIS to Disable Controller. I

= 1mA

FS/DIS

ERROR AMPLIFIER

DC Gain

R

C

R

= 10K to GND

-

72

18

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product

Slew Rate

= 100pF, R = 10K to GND

L

-

= 100pF, Load = ±400µA

5.3

4.1

0.16

Maximum Output Voltage

Minimum Output Voltage

ISEN

= 10K to GND, Load = 400µA

= 10K to GND, Load = -400µA

3.6

-

0.5

V

Full Scale Input Current

Over-Current Trip Level

POWER GOOD MONITOR

Under-Voltage Threshold

PGOOD Low Output Voltage

PROTECTION

-

50

-

µA

82.5

VSEN Rising

VSEN Falling

-

0.92

0.90

0.18

-

V

DAC

V

DAC

V

I

= 4mA

0.4

PGOOD

Over-Voltage Threshold

Percent Over-Voltage Hysteresis

VSEN Rising

1.12

-

1.15

2

1.2

-

V

DAC

%

VSEN Falling after Over-Voltage

5

ISL6553

R

IN

FB

V

IN

ISL6553

ERROR

AMPLIFIER

COMPARATOR

L1

Q1

-

PWM1

ISEN1

CORRECTION

PWM

-

HIP6601

CIRCUIT

∑

+

I

L1

+

-

Q2

PHASE

PROGRAMMABLE

REFERENCE

DAC

R

ISEN1

+

CURRENT

SENSING

∑

-

I AVERAGE

CURRENT

AVERAGING

V

CORE

C

R

-

OUT

LOAD

R

ISEN2

PWM2

+

CURRENT

SENSING

∑

V

IN

PHASE

L2

-

COMPARATOR

+

Q3

+

PWM

HIP6601

CORRECTION

CIRCUIT

-

I

L2

Q4

FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6553 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER

CHANNEL REGULATOR

voltage results in increased comparator output duty cycle.

This increased duty cycle signal is passed through the PWM

circuit with no phase reversal and on to the HIP6601, again

with no phase reversal for gate drive to the upper MOSFETs,

Q1 and Q3. Increased duty cycle or ON time for the

MOSFET transistors results in increased output voltage to

compensate for the low output voltage sensed.

Operation

Figure 1 shows a simpliﬁed diagram of the voltage regulation

and current control loops. Both voltage and current feedback

are used to precisely regulate voltage and tightly control

output currents, I and I , of the two power channels. The

L1 L2

voltage loop comprises the Error Ampliﬁer, Comparators,

gate drivers and output MOSFETs. The Error Ampliﬁer is

essentially connected as a voltage follower that has as an

input, the Programmable Reference DAC and an output that

is the CORE voltage.

Current Loop

The current control loop works in a similar fashion to the

voltage control loop, but with current control information

applied individually to each channel’s comparator. The

information used for this control is the voltage that is

Voltage Loop

Feedback from the CORE voltage is applied via resistor R

to the inverting input of the error ampliﬁer. This signal can

IN

developed across r

of each lower MOSFET, Q2 and

DS(ON)

Q4, when they are conducting. A single resistor converts

and scales the voltage across the MOSFETs to a current

that is applied to the current sensing circuit within the

ISL6553. Output from these sensing circuits is applied to the

current averaging circuit. Each PWM channel receives the

difference current signal from the summing circuit that

compares the average sensed current to the individual

channel current. When a power channel’s current is greater

drive the error ampliﬁer output either high or low, depending

upon the CORE voltage. Low CORE voltage makes the

ampliﬁer output move towards a higher output voltage level.

Ampliﬁer output voltage is applied to the positive inputs of

the comparators via the correction summing networks. Out-

of-phase sawtooth signals are applied to the two

comparators inverting inputs. Increasing error ampliﬁer

6

ISL6553

than the average current, the signal applied via the summing

three state condition that makes these outputs essentially

open. This state results in no gate drive to the output

MOSFETs.

correction circuit to the comparator, reduces the output pulse

width of the comparator to compensate for the detected

“above average” current in that channel.

Once the VCC voltage reaches 4.375V (+125mV), a voltage

level to insure proper internal function, the PWM outputs are

enabled and the soft-start sequence is initiated. If for any

reason, the VCC voltage drops below 3.875V (+125mV).

The POR circuit shuts the converter down and again three

states the PWM outputs.

Droop Compensation

In addition to control of each power channel’s output current,

the average channel current is also used to provide CORE

voltage “droop” compensation. Average full channel current

is deﬁned as 50µA. By selecting an input resistor, R , the

IN

amount of voltage droop required at full load current can be

programmed. The average current driven into the FB pin

Soft-Start

After the POR function is completed with VCC reaching

4.375V, the soft-start sequence is initiated. Soft-Start, by its

slow rise in CORE voltage from zero, avoids an over-current

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error ampliﬁer

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the ISL6553, therefore, the

output voltage is effectively regulated as it rises to the ﬁnal

programmed CORE voltage value.

results in a voltage increase across resistor R that is in the

IN

direction to make the error ampliﬁer “see” a higher voltage at

the inverting input, resulting in the error ampliﬁer adjusting

the output voltage lower. The voltage developed across R

is equal to the “droop” voltage. See the “Current Sensing

and Balancing” section for more details.

IN

Applications and Converter Start-Up

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601, HIP6602 or

HIP6603 MOSFET driver interfaces with the ISL6553. For

more information, see the HIP6601, HIP6602 or HIP6603

data sheets [1] [2].

For the ﬁrst 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles the PWM output remains low, clamping the lower

output MOSFETs to ground, see Figure 3. The time

variability is due to the error ampliﬁer, sawtooth generator

and comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

The ISL6553 controls the two PWM power channels 180

degrees out of phase. Figure 2 shows the out of phase

relationship between the two PWM channels.

PWM 1

PWM 2

The Soft-Start time or delay time, DT = 2048/F . For an

SW

oscillator frequency, F , of 200kHz, the ﬁrst 32 cycles or

SW

FIGURE 2. TWO PHASE PWM OUTPUT AT 500kHz

160µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of

10.24ms.

Power supply ripple frequency is determined by the channel

frequency, F , multiplied by the number of active channels.

SW

For example, if the channel frequency is set to 250kHz, the

ripple frequency is 500kHz.

Figure 3 shows the start-up sequence as initiated by a fast

rising 5V supply, VCC, applied to the ISL6553. Note the

short rise to the three state level in PWM 1 output during ﬁrst

32 PWM cycles.

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the channel frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram ).

Initialization

The ISL6553 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to

the VCC pin of the ISL6553. Oscillator, sawtooth generator,

soft-start and other functions are initialized during this

interval. These circuits are controlled by POR, Power-On

Reset. During this interval, the PWM outputs are driven to a

7

ISL6553

.

Figure 5 shows the regulator operating from an ATX supply.

In this ﬁgure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is made up of NMOS and

PMOS transistors. On the rising VCC, the PMOS device

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

12V ATX

SUPPLY

PGOOD

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the ISL6553 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise ﬁrst, the start-up sequence would be

different. In this case the ISL6553 will sense an over-current

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

V

CORE

5 V ATX

SUPPLY

V

= 5V, CORE LOAD CURRENT = 31A

FREQUENCY 200kHz

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

PWM 1

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

OUTPUT

DELAY TIME

PGOOD

Fault Protection

The ISL6553 protects the microprocessor and the entire

power system from damaging stress levels. Within the

ISL6553 both over-voltage and over-current circuits are

incorporated to protect the load and regulator.

V

CORE

Over-Voltage

5V

VCC

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE over-voltage condition is detected when

the VSEN pin goes more than 15% above the programmed

VID level.

V

= 12V

IN

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

The over-voltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and Soft-Start sequence.

During a latched over-voltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, resulting in the lower or synchronous rectiﬁer

MOSFETs to conduct and shunt the CORE voltage to

ground to protect the load.

V COMP

DELAY TIME

PGOOD

V

CORE

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

destructive ringing of the capacitors and output inductors. If

the conditions that caused the over-voltage still persist, the

5V

VCC

V

= 12V

IN

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

PWM outputs will be cycled between three state and V

clamped to ground, as a hysteretic shunt regulator.

CORE

8

ISL6553

Table 1 shows the nominal DAC voltage as a function of the

Under-Voltage

VID codes. The power supply system is ±1% accurate over

the operating temperature and voltage range.

The VSEN pin also detects when the CORE voltage falls

more than 10% below the VID programmed level. This

causes PGOOD to go low, but has no other effect on

operation and is not latched. There is also hysteresis in this

detection point.

TABLE 1. VOLTAGE IDENTIFICATION CODES

VOLTAGE IDENTIFICATION CODE AT

PROCESSOR PINS

Over-Current

VCC

(CORE)

(VDC)

VID25mV

VID3

0

1

0

VID2

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

In the event of an over-current condition, the over-current

protection circuit reduces the RMS current delivered to 41%

of the current limit. When an over-current condition is

detected, the controller forces all PWM outputs into a three

state mode. This condition results in the gate driver

removing drive to the output stages. The ISL6553 goes into

a wait delay timing cycle that is equal to the Soft-Start ramp

time. PGOOD also goes “low” during this time due to VSEN

going below its threshold voltage. To lower the average

output dissipation, the Soft-Start initial wait time is increased

from 32 to 2048 cycles, then the Soft-Start ramp is initiated.

At a PWM frequency of 200kHz, for instance, an over-

current detection would cause a dead time of 10.24ms, then

a ramp of 10.08ms.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.05

1.075

1.10

1.125

1.15

1.175

1.20

1.225

1.25

1.275

1.30

At the end of the delay, PWM outputs are restarted and the

Soft-Start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

1.325

1.35

1.375

1.40

Figure 6 shows the supply shorted under operation and the

hiccup operating mode described above. Note that due to

the high short circuit current, over-current is detected before

completion of the start-up sequence so the delay is not quite

as long as the normal Soft-Start cycle.

1.425

1.45

1.475

1.50

SHORT APPLIED HERE

1.525

1.55

PGOOD

SHORT

CURRENT

50A/DIV.

1.575

1.60

1.625

1.65

HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY

CORE LOAD CURRENT = 31A, 5V LOAD = 5A

1.675

1.70

SUPPLY FREQUENCY = 200kHz, V = 12V

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

1.725

1.75

FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP

1.775

1.80

CORE Voltage Programming

The voltage identiﬁcation pins (VID25mV, VID0, VID1, VID2

and VID3) set the CORE output voltage. Each VID pin is

pulled to VCC by an internal 20µA current source and

accepts open-collector/open-drain/open-switch-to-ground or

standard low-voltage TTL or CMOS signals.

1.825

9

ISL6553

R

IN

C

R

c

FB

COMP

FB

V

IN

ISL6553

SAWTOOTH

COMPARATOR

L

Q1

ERROR

AMPLIFIER

GENERATOR

V

-

CORE

PWM

HIP6601

+

CIRCUIT

CORRECTION

+

PWM

ISEN

I

L

-

Q2

+

-

PHASE

DIFFERENCE

REFERENCE

DAC

R

ISEN

+

CURRENT

SENSING

-

ONLY ONE OUTPUT

STAGE SHOWN

CURRENT

SENSING

FROM

TO OTHER

CHANNELS

OTHER

CHANNEL

INDUCTOR

CURRENT

FROM

OTHER

CHANNEL

AVERAGING

TO OVER

CURRENT

TRIP

+

-

REFERENCE

COMPARATOR

FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING

current is compared with a trimmed, internally generated

current, and used to detect an over-current condition.

Current Sensing and Balancing

Overview

The nominal current through the R

ISEN

resistor should be

The ISL6553 samples the on-state voltage drop across each

synchronous rectiﬁer FET, Q2, as an indication of the

inductor current in that phase, see Figure 7. Neglecting AC

effects (to be discussed later), the voltage drop across Q2 is

50µA at full output load current, and the nominal trip point for

over-current detection is 165% of that value, or 82.5µA.

Therefore, R

ISEN

= I x r

(Q2) / 50µA.

DS(ON)

L

simply r

(Q2) x inductor current (I ). Note that I , the

For a full load of 25A per phase, and an r

DS(ON)

(Q2) of

DS(ON)

L

inductor current, is 1/2 of the total current (I ).

LT

4mΩ, R

= 2kΩ .

ISEN

The over-current trip point would be 165% of 25A, or ~ 41A

per phase. The R value can be adjusted to change the

The voltage at Q2’s drain, the PHASE node, is applied to the

resistor to develop the I current to the ISL6553

R

ISEN

ISEN pin. This pin is held at virtual ground, so the current

over-current trip point, but it is suggested to stay within ±25%

through R

is I x r

DS(ON)

(Q2) / R .

ISEN

of nominal.

ISEN

L

The I

ISEN

following functions:

current provides information to perform the

Droop, Selection of R

IN

The average of the currents detected through the R

ISEN

resistors is also steered to the FB pin. There is no DC return

1. Detection of an over-current condition

path connected to the FB pin except for R , so the average

IN

current creates a voltage drop across R . This drop

2. Reduce the regulator output voltage with increasing load

current (droop)

IN

voltage with increasing load

increases the apparent V

CORE

3. Balance the I currents in the two phases

L

current, causing the system to decrease V

to maintain

CORE

balance at the FB pin. This is the desired “droop” voltage

Over-Current, Selecting R

ISEN

used to maintain V

conditions.

within limits under transient

The current detected through the R

with the current detected in the other channel. The averaged

resistor is averaged

CORE

ISEN

10

ISL6553

With a high dv/dt load transient, typical of high performance

microprocessors, the largest deviations in output voltage

occur at the leading and trailing edges of the load transient. In

order to fully utilize the output-voltage tolerance range, the

output voltage is positioned in the upper half of the range

when the output is unloaded and in the lower half of the range

when the controller is under full load. This droop

25

20

15

10

5

compensation allows larger transient voltage deviations and

thus reduces the size and cost of the output filter components.

R

should be selected to give the desired “droop” voltage at

IN

the normal full load current 50µA applied through the R

0

ISEN

resistor (or at a different full load current if adjusted as under

“Over-current, Selecting R ” above).

ISEN

R

= V

/ 50µA

IN

DROOP

FIGURE 8. TWO CHANNEL multi-phase SYSTEM WITH

CURRENT BALANCING DISABLED

For a V

of 80mV, R = 1.6kΩ

IN

DROOP

The AC feedback components, R and Cc, are scaled in

FB

relation to R

.

IN

Current Balancing

The detected currents are also used to balance the phase

currents.

25

20

15

10

5

Each phase’s current is compared to the average of the two

phase currents, and the difference is used to create an offset

in that phase’s PWM comparator. The offset is in a direction

to reduce the imbalance.

The balancing circuit can not make up for a difference in

r

between synchronous rectiﬁers. If a FET has a

DS(ON)

0

higher r

, the current through that phase will be

DS(ON)

reduced.

Figures 8 and 9 show the inductor current of a two phase

system without and with current balancing.

FIGURE 9. TWO CHANNEL multi-phase SYSTEM WITH

CURRENT BALANCING ENABLED

Inductor Current

The inductor current in each phase of a multi-phase Buck

converter has two components. There is a current equal to

The inductor, or load current, ﬂows alternately from V

IN

through Q1 and from ground through Q2. The ISL6553

samples the on-state voltage drop across each Q2 transistor

to indicate the inductor current in that phase. The voltage

the load current divided by the number of phases (I / n),

LT

and a sawtooth current, (i

) resulting from switching.

PK-PK

The sawtooth component is dependent on the size of the

inductors, the switching frequency of each phase, and the

values of the input and output voltage. Ignoring secondary

effects, such as series resistance, the peak to peak value of

the sawtooth current can be described by:

drop is sampled 1/3 of a switching period, 1/F , after Q1 is

SW

turned OFF and Q2 is turned on. Because of the sawtooth

current component, the sampled current is different from the

average current per phase. Neglecting secondary effects,

the sampled current (I

current (I ) by:

LT

) can be related to the load

SAMPLE

2

i

= (V x V

IN CORE

- V

) / (L x F

SW

x V )

IN

PK-PK

Where: V

CORE

= DC value of the output or V voltage

ID

= DC value of the input or supply voltage

CORE

2

I

=

I

/ n + (V V

IN CORE

- 3V

) / (6L x F x V )

SW IN

SAMPLE LT

CORE

V

IN

L = value of the inductor

= switching frequency

Where: I

= total load current

n = the number of channels

LT

F

SW

Example: For V

=1.6V,

=12V,

CORE

Example: Using the previously given conditions, and

For I = 50A,

V

IN

LT

n = 2

L = 1.3µH,

F

= 250kHz,

Then I

= 25.49A

SW

= 4.3A

SAMPLE

Then i

PK-PK

11

ISL6553

As discussed previously, the voltage drop across each Q2

transistor at the point in time when current is sampled is

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efﬁciency, radiate noise into the circuit

and lead to device over-voltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops ﬂowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes. Contact

Intersil for evaluation board drawings of the component

placement and printed circuit board.

r

(Q2) x I

. The voltage at Q2’s drain, the

SAMPLE

DSON

PHASE node, is applied through the R

resistor to the

ISEN

ISL6553 ISEN pin. This pin is held at virtual ground, so the

current into ISEN is:

I

= I

x r

(Q2) / R .

ISEN

SENSE

SAMPLE

DS(ON)

R

(Q2) / 50µA

Isen

DS(ON)

Example: From the previous conditions,

where I

= 50A,

LT

I

= 25.49A,

= 4mΩ

SAMPLE

r

(Q2)

ISEN

DS(ON)

Then: R

I

= 2.04K and

= 165%

There are two sets of critical components in a DC-DC

converter using a ISL6553 controller and a HIP6601 gate

driver. The power components are the most critical because

they switch large amounts of energy. Next are small signal

components that connect to sensitive nodes or supply

critical bypassing current and signal coupling.

CURRENT TRIP

Short circuit I

= 82.5A.

LT

Channel Frequency Oscillator

The channel oscillator frequency is set by placing a resistor,

R , to ground from the FS/DIS pin. Figure 10 is a curve

T

showing the relationship between frequency, F , and

resistor R . To avoid pickup by the FS/DIS pin, it is important

T

The power components should be placed ﬁrst. Locate the

input capacitors close to the power switches. Minimize the

SW

to place this resistor next to the pin. If this pin is also used to

disable the converter, it is also important to locate the pull-

down device next to this pin.

length of the connections between the input capacitors, C

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the gate driver close to the MOSFETs.

,

IN

1,000

500

The critical small components include the bypass capacitors

for VCC and PVCC on the gate driver ICs. Locate the

bypass capacitor, C , for the ISL6553 controller close to

BP

the device. It is especially important to locate the resistors

associated with the input to the ampliﬁers close to their

respective pins, since they represent the input to feedback

200

100

50

ampliﬁers. Resistor R , that sets the oscillator frequency

T

should also be located next to the associated pin. It is

especially important to place the R

resistors at the

SEN

respective terminals of the ISL6553.

20

10

A multi-layer printed circuit board is recommended. Figure 11

shows the connections of the critical components for one

output channel of the converter. Note that capacitors C and

IN

5

C

could each represent numerous physical capacitors.

OUT

Dedicate one solid layer, usually the middle layer of the PC

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from

the PHASE terminal to output inductor short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the driver IC to the

MOSFET gate and source should be sized to carry at least 1A

of current.

2

1

10

20

50 100 200

500 1,000 2,000 5,000 10,000

(kHz)

CHANNEL OSCILLATOR FREQUENCY, F

SW

FIGURE 10. RESISTANCE R vs FREQUENCY

T

Layout Considerations

MOSFETs switch very fast and efﬁciently. The speed with

which the current transitions from one device to another

12

ISL6553

increases with case size and can reduce the usefulness of

the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a speciﬁed parameter. Consult the

capacitor manufacturer and measure the capacitor’s

impedance with frequency to select a suitable component.

Component Selection Guidelines

Output Capacitor Selection

The output capacitor is selected to meet both the dynamic

load requirements and the voltage ripple requirements. The

load transient for the microprocessor CORE is characterized

by high slew rate (di/dt) current demands. In general,

multiple high quality capacitors of different size and dielectric

are paralleled to meet the design constraints.

Output Inductor Selection

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Small inductors in a multi-phase converter reduces

the response time without signiﬁcant increases in total ripple

current.

Modern microprocessors produce severe transient load rates.

High frequency capacitors supply the initially transient current

and slow the load rate-of-change seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

The output inductor of each power channel controls the

ripple current. The control IC is stable for channel ripple

current (peak-to-peak) up to twice the average current. A

single channel’s ripple current is approximately:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

speciﬁc decoupling requirements.

V

– V

V

OUT

V

IN

F

OUT

------------------------------- ---------------

∆I =

×

xL

SW

The current from multiple channels tend to cancel each other

and reduce the total ripple current. Figure 12 gives the total

ripple current as a function of duty cycle, normalized to the

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient’s edge. In most cases, multiple capacitors of small

case size perform better than a single large case capacitor.

parameter (Vo) ⁄ (L F ) at zero duty cycle. To determine the

total ripple current from the number of channels and the duty

S

cycle, multiply the y-axis value by (Vo) ⁄ (LxF ) .

SW

Small values of output inductance can cause excessive power

dissipation. The ISL6553 is designed for stable operation for

ripple currents up to twice the load current. However, for this

condition, the RMS current is 115% above the value shown in

the following MOSFET Selection and Considerations section.

With all else fixed, decreasing the inductance could increase

the power dissipated in the MOSFETs by 30%.

Bulk capacitor choices include aluminum electrolytic, OS-

Con, Tantalum and even ceramic dielectrics. An aluminum

electrolytic capacitor’s ESR value is related to the case size

with lower ESR available in larger case sizes. However, the

equivalent series inductance (ESL) of these capacitors

+5V

IN

USE INDIVIDUAL METAL RUNS

FOR EACH CHANNEL TO HELP

ISOLATE OUTPUT STAGES

+12V

C

BP

VCC PVCC

LOCATE NEXT TO IC PIN(S)

C

BOOT

C

IN

LOCATE NEAR TRANSISTOR

VCC

L

C

PWM

O1

BP

V

CORE

HIP6601

PHASE

FS/DIS

COMP

C

OUT

C

T

ISL6553

R

T

R

FB

LOCATE NEXT

TO FB PIN

FB

LOCATE NEXT TO IC PIN

SEN

R

IN

R

VSEN

ISEN

VIA CONNECTION TO GROUND PLANE

ISLAND ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

KEY

FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

13

ISL6553

For bulk capacitance, several electrolytic capacitors (Panasonic

1.0

0.8

0.6

0.4

0.2

0

HFQ series or Nichicon PL series or Sanyo MV-GX or

equivalent) may be needed. For surface mount designs, solid

tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

SINGLE

CHANNEL

2 CHANNEL

MOSFET Selection and Considerations

3 CHANNEL

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the following

equations). The conduction losses are the main component

of power dissipation for the lower MOSFETs, Q2 and Q4 of

Figure 1. Only the upper MOSFETs, Q1 and Q3 have

signiﬁcant switching losses, since the lower device turns on

and off into near zero voltage.

4 CHANNEL

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 12. RIPPLE CURRENT vs DUTY CYCLE

Input Capacitor Selection

The important parameters for the bulk input capacitors are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and

largest RMS current required by the circuit. The capacitor

voltage rating should be at least 1.25 times greater than the

maximum input voltage and a voltage rating of 1.5 times is

a conservative guideline. The RMS current required for a

multi-phase converter can be approximated with the aid of

Figure 13.

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the Driver IC and don’t heat the MOSFETs.

However, large gate-charge increases the switching time,

t

which increases the upper MOSFET switching losses.

SW

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance speciﬁcations. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air ﬂow.

0.5

SINGLE

CHANNEL

0.4

0.3

0.2

0.1

0

2

I

× r

× V

I

× V × t

× F

SW SW

O

DS(ON)

OUT

O

IN

P

= ------------------------------------------------------------ + ---------------------------------------------------------

UPPER

2 CHANNEL

V

2

IN

2

I

× r

× (V – V

)

OUT

O

DS(ON)

IN

3 CHANNEL

P

= --------------------------------------------------------------------------------

LOWER

V

IN

A diode, anode to ground, may be placed across Q2 and Q4

of Figure 1. These diodes function as a clamp that catches

the negative inductor swing during the dead time between

the turn off of the lower MOSFETs and the turn on of the

upper MOSFETs. The diodes must be a Schottky type to

prevent the lossy parasitic MOSFET body diode from

conducting. It is usually acceptable to omit the diodes and let

the body diodes of the lower MOSFETs clamp the negative

inductor swing, but efﬁciency could drop one or two percent

as a result. The diode's rated reverse breakdown voltage

must be greater than the maximum input voltage.

4 CHANNEL

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE

First determine the operating duty ratio as the ratio of the

output voltage divided by the input voltage. Find the Current

Multiplier from the curve with the appropriate power

channels. Multiply the current multiplier by the full load

output current. The resulting value is the RMS current rating

required by the input capacitor.

References

Intersil documents are available on the web at

www.intersil.com/

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors should

be placed very close to the drain of the upper MOSFET to

suppress the voltage induced in the parasitic circuit

impedances.

[1] HIP6601/HIP6603 Data Sheet, Intersil Corporation,

File No. 4819

[2] HIP6602 Data Sheet, Intersil Corporation, File No. 4838

14

ISL6553

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

N

INDEX

0.25(0.010)

M

B M

H

AREA

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

0.0688

0.0098

0.020

MIN

1.35

0.10

0.33

0.19

9.80

3.80

MAX

1.75

0.25

0.51

0.25

10.00

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

-

1

2

3

L

-

SEATING PLANE

A

9

-A-

0.0075

0.3859

0.1497

0.0098

0.3937

0.1574

-

o

h x 45

D

3

4

-C-

α

0.050 BSC

1.27 BSC

-

e

A1

C

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

B

0.10(0.004)

5

0.25(0.010) M

C

A M B S

L

6

N

α

16

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Intersil Ltd.

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

Mercure Center

8F-2, 96, Sec. 1, Chien-kuo North,

Taipei, Taiwan 104

Republic of China

TEL: 886-2-2515-8508

FAX: 886-2-2515-8369

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

15


型号：	ISL6553CB-T
厂家：	Intersil
描述：	Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller 微处理器核心电压调节器多相降压PWM控制器调节器微处理器多相元件控制器
文件：	总15页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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