ISL6554_技术文档

ISL6554

®

Data Sheet

February 11, 2005

FN9003.3

Microprocessor CORE Voltage Regulator

Using Multi-Phase Buck PWM Control

Without Programmable Droop

The ISL6554 is the first controller in the Intersil Multi-Phase

family without the programmable droop feature. The

ISL6554 in combination with the HIP6601A, HIP6602A or

HIP6603A companion gate drivers and Intersil MOSFETs

form a complete solution for high-current, high slew-rate

applications. The ISL6554 regulates output voltage,

balances load currents and provides protective functions for

two to four synchronous-rectified buck-converter channels.

Features

• Multi-Phase Power Conversion

• Precision Channel Current Balance

- Lossless Current Sampling - Uses r

DS(ON)

• Precision CORE Voltage Regulation

- ±1% System Accuracy Over Temperature

- No Programmable Droop

• Microprocessor Voltage Identification Input

- 5-Bit VID Decoder

- 0.95V to 1.70V in 25mV Steps

A novel approach to current sensing is used to reduce

overall solution cost. The voltage developed across the

lower MOSFET’s parasitic on-resistance during conduction

is sampled and fed back to the controller. This lossless

current-sensing approach allows the controller to maintain

phase-current balance between the power channels and

overcurrent protection.

• Fast Transient Response

• Overcurrent Protection

• Selection of 2, 3, or 4 Phase Operation

• High Ripple Frequency (80kHz to 2MHz)

• Pb-Free Available (RoHS Compliant)

A 5-bit DAC allows digital programming of the output voltage

in 25mV steps over a range from 0.95V to 1.70V with a

system accuracy of ±1%. Internal pull ups on each DAC

input make external pull-up resistors unnecessary when

interfacing with open-drain output signals.

Applications

• Power Supply Controller for Intel® Itanium™ Processor

Family

• Voltage Regulator Modules

• Servers and Workstations

The PGOOD signal is held low during soft-start until the

output voltage increases to within 4% of the programmed.

When the CORE voltage falls 9% below the programmed

VID level, an undervoltage condition is detected and results

in PGOOD transitioning low.

Ordering Information

PKG.

PART NUMBER

ISL6554CB

TEMP. (°C)

PACKAGE

DWG. #

0 to 70

20 Ld SOIC

M20.3

In the event of an overvoltage condition, The converter shuts

down and turns ON the lower MOSFETs to clamp and

protect the microprocessor. Overcurrent protection reduces

the regulator RMS output current to 41% of the programmed

overcurrent trip value. These features provide monitoring

and protection for the microprocessor and power system.

ISL6554CB-T

20 Ld SOIC Tape and Reel

ISL6554CBZ (Note)

0 to 70

20 Ld SOIC

(PB-free)

M20.3

ISL6554CBZ-T (Note)

ISL6554CBZA (Note)

20 Ld SOIC Tape and Reel (PB-free)

0 to 70

20 Ld SOIC

(PB-free)

M20.3

Pinout

ISL6554 (SOIC)

TOP VIEW

ISL6554CBZA-T (Note)

20 Ld SOIC Tape and Reel (PB-free)

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

1

2

20

19

18

17

16

15

14

13

12

11

VID4

VID3

VCC

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

3

VID2

4

VID1

5

VID0

6

COMP

FB

7

8

FS/DIS

GND

9

10

VSEN

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

1

Itanium™ is a trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.

ISL6554

Block Diagram

PGOOD

VCC

POWER-ON

RESET (POR)

UV

THREE

STATE

VSEN

+

-

X 0.9

OV

LATCH

CLOCK AND

SAWTOOTH

GENERATOR

S

FS/EN

PWM1

OVP

+

PWM

∑

X1.15

-

+

-

SOFT-

+

∑

START

PWM2

+

-

AND FAULT

LOGIC

-

COMP

+

PWM

∑

PWM3

PWM4

+

-

VID4

VID3

VID2

VID1

VID0

+

D/A

∑

+

-

E/A

-

+

-

PHASE

NUMBER

CHANNEL

CURRENT

CORRECTION

FB

DETECTOR

I_TOT

ISEN1

+

ISEN2

ISEN3

∑

+

-

+

OC

I_TRIP

ISEN4

GND

FN9003.3

February 11, 2005

2

ISL6554

Simplified Power System Diagram

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

VSEN

PWM 1

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 2

MICROPROCESSOR

ISL6554

PWM 3

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 4

VID

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

Functional Pin Description

1

2

20

19

18

17

16

15

14

13

12

11

VID4

VID3

VCC

GND (Pin 9)

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

Bias and reference ground. All signals are referenced to this

pin.

3

VID2

4

VID1

VSEN (Pin 10)

Power good monitor input. Connect to the microprocessor-

CORE voltage.

5

VID0

6

COMP

FB

7

8

FS/DIS

GND

PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and

PWM4 (Pin 18)

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of an HIP6601/2/3 driver. For systems

which use 3 channels, connect PWM4 high. Two channel

systems connect PWM3 and PWM4 high.

9

10

VSEN

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)

and VID0 (Pin 5)

ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and

ISEN4 (Pin 17)

Current sense inputs from the individual converter channel’s

phase nodes. Unused sense lines MUST be left open.

Voltage Identification inputs from microprocessor. These

pins respond to TTL and 3.3V logic signals. The ISL6554

decodes VID bits to establish the output voltage. See

Table 1.

COMP (Pin 6)

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

PGOOD (Pin 19)

Power good. This pin provides a logic-high signal when the

microprocessor CORE voltage is within specified limits and

soft-start has timed out.

FB (Pin 7)

Inverting input of the internal error amplifier.

VCC (Pin 20)

Bias supply. Connect this pin to a 5V supply.

FS/DIS (Pin 8)

Channel frequency, F , select and disable. A resistor from

SW

this pin to ground sets the switching frequency of the

FN9003.3

3

February 11, 2005

ISL6554

Typical Application - 2 Phase Converter Using HIP6601 Gate Drivers

+12V

V

= +5V

IN

BOOT

PVCC

VCC

UGATE

PHASE

+5V

DRIVER

PWM

HIP6601

LGATE

GND

FB

COMP

VCC

VSEN

+V

CORE

PWM4

PWM3

+12V

PGOOD

VID4

V

= +5V

PWM2

PWM1

IN

BOOT

VID3

VID2

PVCC

UGATE

PHASE

MAIN

CONTROL

ISL6554

VID1

VID0

VCC

DRIVER

HIP6601

PWM

NC

ISEN4

ISEN3

ISEN2

ISEN1

LGATE

GND

FS/DIS

GND

FN9003.3

February 11, 2005

4

ISL6554

Typical Application - 4 Phase Converter Using HIP6602 Gate Drivers

V

= +12V

IN

+12V

BOOT1

UGATE1

PHASE1

L

01

VCC

LGATE1

PVCC

+5V

DUAL

DRIVER

HIP6602

+5V

V

+12V

IN

BOOT2

FB

VSEN

COMP

VCC

UGATE2

PHASE2

L

02

ISEN1

PWM1

PWM2

PGOOD

VID4

PWM2

ISEN2

LGATE2

VID3

VID2

MAIN

GND

CONTROL

ISL6554

VID1

VID0

+V

CORE

ISEN3

FS/DIS

PWM3

PWM4

V

+12V

IN

+12V

BOOT3

ISEN4

GND

UGATE3

PHASE3

L

03

VCC

LGATE3

PVCC

DUAL

+5V

DRIVER

HIP6602

V

+12V

IN

BOOT4

UGATE4

PHASE4

L

04

PWM3

PWM4

LGATE4

GND

FN9003.3

February 11, 2005

5

ISL6554

Absolute Maximum Ratings

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5KV

Thermal Information

Thermal Resistance (Typical, Note 1)

θ

(°C/W)

65

JA

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Operating Conditions: VCC = 5V, T = 0°C to 70°C, Unless Otherwise Specified

A

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNITS

INPUT SUPPLY POWER

Input Supply Current

R

= 100kΩ

-

10

15

mA

T

POWER-ON RESET (POR)

VCC Rising Threshold

4.25

3.75

4.38

3.88

4.5

V

VCC Falling Threshold

REFERENCE AND DAC

Reference Voltage Accuracy

DAC Pin Input Low Voltage Threshold

DAC Pin Input High Voltage Threshold

VID Pull-Up

4.00

-1

-

1

0.8

-

%

V

2.0

10

-

V

VIDx = 0V or VIDx = 3V

20

40

µA

OSCILLATOR

Frequency, F

R

= 100kΩ, ±1%

224

280

-

336

1.5

kHz

SW

T

Adjustment Range (GBD) (Note 2)

ERROR AMPLIFIER

DC Gain (GBD) (Note 2)

Gain-Bandwidth Product (GBD) (Note 2)

Slew Rate

(See Figure 10)

0.05

MHz

R

C

R

= 10K to GND

-

72

18

-

dB

MHz

V/µs

V

L

= 100pF, R = 10K to GND

-

L

= 100pF, R = 10K to GND

L

5.3

4.1

0.16

Maximum Output Voltage

Minimum Output Voltage

ISEN

= 10K to GND

3.6

-

0.5

V

Full Scale Input Current (GBD) (Note 2)

Overcurrent Trip Level

POWER GOOD

-

50

-

µA

82.5

Upper Threshold

VSEN Rising

VSEN Falling

0.95

0.89

-

0.97

0.91

0.18

0.99

0.93

0.4

V

DAC

Lower Threshold

V

DAC

V

PGOOD Low Output Voltage

PROTECTION

I

= 4mA

PGOOD

Overvoltage Threshold

VSEN Rising

1.12

-

1.15

2

1.2

-

V

DAC

%

Percent Overvoltage Hysteresis (GNT) (Note 3) VSEN Falling after Overvoltage

NOTES:

2. GBD = Guaranteed by design.

3. GNT = Guaranteed not tested.

FN9003.3

February 11, 2005

6

ISL6554

R

IN

FB

V

IN

ISL6554

ERROR

AMPLIFIER

COMPARATOR

L1

Q1

PWM1

ISEN1

CORRECTION

PWM

-

+

HIP6601

-

CIRCUIT

∑

+

I

L1

+

-

Q2

PHASE

PROGRAMMABLE

REFERENCE

DAC

+

R

ISEN1

CURRENT

SENSING

∑

-

I AVERAGE

CURRENT

V

CORE

AVERAGING

C

R

-

OUT

LOAD

R

+

ISEN2

PWM2

CURRENT

SENSING

∑

V

IN

PHASE

L2

COMPARATOR

-

Q3

+

PWM

+

-

HIP6601

CIRCUIT

CORRECTION

I

L2

Q4

FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6554 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER

CHANNEL REGULATOR

circuit with no phase reversal and on to the HIP6601, again

with no phase reversal for gate drive to the upper MOSFETs,

Q1 and Q3. Increased duty cycle or ON time for the

MOSFET transistors results in increased output voltage to

compensate for the low output voltage sensed.

Operation

Figure 1 shows a simplified diagram of the voltage regulation

and current control loops. Both voltage and current feedback

are used to precisely regulate voltage and tightly control

output currents, I and I , of the two power channels. The

L1 L2

voltage loop comprises the error amplifier, comparators, gate

drivers and output MOSFETs. The error amplifier is

essentially connected as a voltage follower that has as an

input, the programmable reference DAC and an output that

is the CORE voltage.

Current Loop

The current control loop works in a similar fashion to the

voltage control loop, but with current control information

applied individually to each channel’s comparator. The

information used for this control is the voltage that is

developed across r

of each lower MOSFET, Q2 and

DS(ON)

Voltage Loop

Q4, when they are conducting. A single resistor converts and

scales the voltage across the MOSFETs to a current that is

applied to the current sensing circuit within the ISL6554.

Output from these sensing circuits is applied to the current

averaging circuit. Each PWM channel receives the

Feedback from the CORE voltage is applied via resistor R

to the inverting input of the error amplifier. This signal can

IN

drive the error amplifier output either high or low, depending

upon the CORE voltage. Low CORE voltage makes the

amplifier output move towards a higher output voltage level.

Amplifier output voltage is applied to the positive inputs of

the comparators via the correction summing networks.

Out-of-phase sawtooth signals are applied to the two

comparators inverting inputs. Increasing error amplifier

voltage results in increased comparator output duty cycle.

This increased duty cycle signal is passed through the PWM

difference current signal from the summing circuit that

compares the average sensed current to the individual

channel current. When a power channel’s current is greater

than the average current, the signal applied via the summing

correction circuit to the comparator, reduces the output pulse

width of the comparator to compensate for the detected

“above average” current in that channel.

FN9003.3

7

February 11, 2005

ISL6554

Once the VCC voltage reaches 4.375V (+125mV), a voltage

Applications and Converter Start-Up

level to insure proper internal function, the PWM outputs are

enabled and the soft-start sequence is initiated. If for any

reason, the VCC voltage drops below 3.875V (+125mV). The

POR circuit shuts the converter down and again three states

the PWM outputs.

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601, HIP6602 or

HIP6603 MOSFET driver interfaces with the ISL6554. For

more information, see the HIP6601, HIP6602 or HIP6603

data sheets [1], [2].

Soft-Start

After the POR function is completed with VCC reaching

4.375V, the soft-start sequence is initiated. soft-start, by its

slow rise in CORE voltage from zero, avoids an overcurrent

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the ISL6554, therefore; the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

The ISL6554 is capable of controlling up to 4 PWM power

channels. Connecting unused PWM outputs to VCC

automatically sets the number of channels. The phase

relationship between the channels is 360 degrees/number of

active PWM channels. For example, for three channel

operation, the PWM outputs are separated by 120 degrees.

Figure 2 shows the PWM output signals for a four channel

system.

For the first 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles, the PWM output remains low, clamping the lower

output MOSFETs to ground (see Figure 3). The time

variability is due to the error amplifier, sawtooth generator

and comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

PWM 1

PWM 2

PWM 3

PWM 4

The soft-start time or delay time, DT = 2048/F . For an

FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz

SW

oscillator frequency, F , of 200kHz, the first 32 cycles or

SW

160µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of 10.24ms.

Power supply ripple frequency is determined by the channel

frequency, F , multiplied by the number of active

SW

channels. For example, if the channel frequency is set to

250kHz and there are three phases, the ripple frequency is

750kHz.

Figure 3 shows the start-up sequence as initiated by a fast

rising 5V supply, VCC applied to the ISL6554. Note the

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

,

short rise to the three state level in PWM 1 output during first

32 PWM cycles.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the soft-start duration is a

function of the channel frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram).

Initialization

The ISL6554 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to

the VCC pin of the ISL6554. Oscillator, sawtooth generator,

soft-start and other functions are initialized during this

interval. These circuits are controlled by POR, Power-On

Reset. During this interval, the PWM outputs are driven to a

three state condition that makes these outputs essentially

open. This state results in no gate drive to the output

MOSFETs.

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is made up of NMOS and

PMOS transistors. On the rising VCC, the PMOS device

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

FN9003.3

8

February 11, 2005

ISL6554

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the ISL6554 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the ISL6554 will sense an overcurrent

condition due to charging the output capacitors. The supply

will then restart and go through the normal soft-start cycle.

PWM 1

OUTPUT

DELAY TIME

PGOOD

Fault Protection

V

CORE

The ISL6554 protects the microprocessor and the entire

power system from damaging stress levels. Within the

ISL6554 both Overvoltage and Overcurrent circuits are

incorporated to protect the load and regulator.

5V

VCC

Overvoltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE overvoltage condition is detected when the

VSEN pin goes more than 15% above the programmed VID

level.

V

= 12V

IN

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

The overvoltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and soft-start sequence.

V COMP

DELAY TIME

During a latched overvoltage, the PWM outputs will be driven

either low or three state, depending upon the VSEN input.

PWM outputs are driven low when the VSEN pin detects that

the CORE voltage is 15% above the programmed VID level.

This condition drives the PWM outputs low, resulting in the

lower or synchronous rectifier MOSFETs to conduct and shunt

the CORE voltage to ground to protect the load.

PGOOD

V

CORE

5V

VCC

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three-state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

destructive ringing of the capacitors and output inductors. If

the conditions that caused the overvoltage still persist, the

V

= 12V

IN

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

PWM outputs will be cycled between three state and V

clamped to ground, as a hysteretic shunt regulator.

CORE

12V ATX

SUPPLY

Undervoltage

PGOOD

The VSEN pin also detects when the CORE voltage falls

more than 9% below the VID programmed level. This causes

PGOOD to go low, but has no other effect on operation and

is not latched. There is also hysteresis in this detection point.

V

CORE

Overcurrent

5 V ATX

SUPPLY

In the event of an overcurrent condition, the overcurrent

protection circuit reduces the RMS current delivered to 41%

of the current limit. When an overcurrent condition is

detected, the controller forces all PWM outputs into a three

state mode. This condition results in the gate driver

V

= 5V, CORE LOAD CURRENT = 31A

FREQUENCY 200kHz

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

removing drive to the output stages. The ISL6554 goes into

a wait delay timing cycle that is equal to the soft-start ramp

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

FN9003.3

9

February 11, 2005

ISL6554

TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)

time. PGOOD also goes “low” during this time due to VSEN

going below its threshold voltage. To lower the average

output dissipation, the soft-start initial wait time is increased

from 32 to 2048 cycles, then the soft-start ramp is initiated.

At a PWM frequency of 200kHz, for instance, an overcurrent

detection would cause a dead time of 10.24ms, then a ramp

of 10.08ms.

VOLTAGE IDENTIFICATION CODE AT

PROCESSOR PINS

VCC

(V

1.150

CORE

VID4

1

VID3

0

VID2

1

VID1

1

VID0

0

)

DC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

At the end of the delay, PWM outputs are restarted and the

soft-start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

Figure 6 shows the supply shorted under operation and the

hiccup operating mode described above. Note that due to

the high short circuit current, overcurrent is detected before

completion of the start-up sequence so the delay is not quite

as long as the normal soft-start cycle.

SHORT APPLIED HERE

PGOOD

SHORT

CURRENT

50A/DIV.

0

1

0

1

0

1

0

1

0

1

0

HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY

CORE LOAD CURRENT = 31A, 5V LOAD = 5A

SUPPLY FREQUENCY = 200kHz, V = 12V

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

Current Sensing and Balancing

FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP

Overview

CORE Voltage Programming

The ISL6554 samples the on-state voltage drop across each

synchronous rectifier MOSFET, Q2, as an indication of the

inductor current in that phase (see Figure 7). Neglecting AC

effects (to be discussed later), the voltage drop across Q2 is

The voltage identification pins (VID0, VID1,VID2,VID3 and

VID4) set the CORE output voltage. Each VID pin is pulled to

VCC by an internal 20µA current source and accepts open-

collector/open-drain/open-switch-to-ground or standard low-

voltage TTL or CMOS signals.

simply r

(Q2) x inductor current (I ). Note that I , the

DS(ON)

L L

inductor current, is either 1/2, 1/3, or 1/4 of the total current

(I ), depending on how many phases are in use.

LT

Table 1 shows the nominal DAC voltage as a function of the

VID codes. The power supply system is ±1% accurate over

the operating temperature and voltage range.

The voltage at Q2’s drain, the PHASE node, is applied to the

R

resistor to develop the I current to the ISL6554

ISEN

ISEN pin. This pin is held at virtual ground, so the current

TABLE 1. VOLTAGE IDENTIFICATION CODES

VOLTAGE IDENTIFICATION CODE AT

through R

is I x r

(Q2) / R .

ISEN

L

DS(ON) ISEN

PROCESSOR PINS

The I

ISEN

current provides information to perform the

VCC

CORE

VID4

VID3

VID2

VID1

VID0

(V

)

following functions:

DC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Output Off

0.95

1. Detection of an overcurrent condition

2. Balance the I currents in multiple channels

L

0.975

1.000

1.025

1.050

1.075

1.100

1.125

Overcurrent, Selecting RISEN

The current detected through the R

resistor is

ISEN

averaged with the current(s) detected in the other 1, 2, or 3

channels. The averaged current is compared with a

trimmed, internally generated current, and used to detect

an overcurrent condition.

FN9003.3

10

February 11, 2005

ISL6554

C

R

IN

c

FB

COMP

FB

ISL6554

V

IN

SAWTOOTH

COMPARATOR

L

Q1

01

ERROR

AMPLIFIER

GENERATOR

V

CORE

PWM

-

+

HIP6601

CIRCUIT

CORRECTION

+

PWM

ISEN

I

L

-

+

Q2

PHASE

-

DIFFERENCE

REFERENCE

DAC

R

CURRENT

SENSING

CURRENT

ISEN

+

-

ONLY ONE OUTPUT

STAGE SHOWN

TO OTHER

CHANNELS

SENSING

FROM

OTHER

CHANNELS

COMPARATOR

TO OVER

CURRENT

TRIP

INDUCTOR

CURRENT(S)

FROM

AVERAGING

+

-

REFERENCE

OTHER

CHANNELS

FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING

The nominal current through the R

resistor should be

values of the input and output voltage. Ignoring secondary

effects, such as series resistance, the peak to peak value of

the sawtooth current can be described by:

ISEN

50µA at full output load current, and the nominal trip point for

overcurrent detection is 165% of that value, or 82.5µA.

Therefore, R

= I x r

(Q2) / 50µA.

ISEN

L

DS(ON)

2

i

= (V x V

IN CORE

- V

) / (L x F

SW

x V )

IN

PK-PK

Where: V

CORE

For a full load of 25A per phase, and an r

(Q2) of

DS(ON)

= DC value of the output or V voltage

ID

CORE

4mΩ, R

= 2kΩ.

ISEN

V

= DC value of the input or supply voltage

IN

L= value of the inductor

The overcurrent trip point would be 165% of 25A, or ~ 41A

F

= switching frequency

SW

Example: For V

per phase. The R

value can be adjusted to change the

ISEN

overcurrent trip point, but it is suggested to stay within ±25%

=1.6V,

CORE

of nominal.

V

=12V,

IN

L=1.3µH,

Current Balancing

The detected currents are also used to balance the phase

currents.

F

= 250kHz,

SW

Then i

= 4.3A

PK-PK

The inductor, or load current, flows alternately from V

IN

Each phase’s current is compared to the average of all

phase currents, and the difference is used to create an offset

in that phase’s PWM comparator. The offset is in a direction

to reduce the imbalance.

through Q1 and from ground through Q2. The ISL6554

samples the on-state voltage drop across each Q2 transistor

to indicate the inductor current in that phase. The voltage

drop is sampled 1/3 of a switching period, i/F , after Q1 is

SW

The balancing circuit can not make up for a difference in

turned OFF and Q2 is turned on. Because of the sawtooth

current component, the sampled current is different from the

average current per phase. Neglecting secondary effects,

r

between synchronous rectifiers. If a FET has a higher

, the current through that phase will be reduced.

DS(ON)

r

DS(ON)

the sampled current (I

) can be related to the load

SAMPLE

Figures 8 and 9 show the inductor current of a two phase

system without and with current balancing.

current (I ) by:

LT

2

I

=

I

/ n + (V V

IN CORE

-3V

) / (6L x F x V )

SW IN

SAMPLE LT

Where:

CORE

Inductor Current

The inductor current in each phase of a multi-phase Buck

converter has two components. There is a current equal to

I

= total load current

LT

n = the number of channels

the load current divided by the number of phases (I / n),

LT

Example: Using the previously given conditions, and

and a sawtooth current, (i

) resulting from switching.

PK-PK

For

I

= 100A,

LT

n = 4

The sawtooth component is dependent on the size of the

inductors, the switching frequency of each phase, and the

Then I

= 25.49A

SAMPLE

FN9003.3

11

February 11, 2005

ISL6554

resistor R . To avoid pickup by the FS/DIS pin, it is important

T

to place this resistor next to the pin.

25

20

15

10

5

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting impedances

and parasitic circuit elements. These voltage spikes can

degrade efficiency, radiate noise into the circuit and lead to

device overvoltage stress. Careful component layout and

printed circuit design minimizes the voltage spikes in the

converter. Consider, as an example, the turnoff transition of

the upper PWM MOSFET. Prior to turnoff, the upper MOSFET

was carrying channel current. During the turnoff, current stops

flowing in the upper MOSFET and is picked up by the lower

MOSFET. Any inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

magnitude of voltage spikes. Contact Intersil for evaluation

board drawings of the component placement and printed

circuit board.

0

FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH

CURRENT BALANCING DISABLED

25

20

15

10

5

There are two sets of critical components in a DC-DC

converter using a ISL6554 controller and a HIP6601 gate

driver. The power components are the most critical because

they switch large amounts of energy. Next are small signal

components that connect to sensitive nodes or supply critical

bypassing current and signal coupling.

0

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

length of the connections between the input capacitors, C

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the gate driver close to the MOSFETs.

,

IN

FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH

CURRENT BALANCING ENABLED

As discussed previously, the voltage drop across each Q2

The critical small components include the bypass capacitors for

VCC and PVCC on the gate driver ICs. Locate the bypass

transistor at the point in time when current is sampled is r

DSON

. The voltage at Q2’s drain, the PHASE node,

ISEN

This pin is held at virtual ground, so the current into ISEN is:

(Q2) x I

SAMPLE

capacitor, C , for the ISL6554 controller close to the device. It

BP

is applied through the R

resistor to the ISL6554 ISEN pin.

is especially important to locate the resistors associated with

the input to the amplifiers close to their respective pins, since

I

= I

x r

(Q2) / R

ISEN

.

they represent the input to feedback amplifiers. Resistor R ,

SENSE

SAMPLE

DS(ON)

T

that sets the oscillator frequency should also be located next to

R

(Q2) / 50µA

Isen

DS(ON)

the associated pin. It is especially important to place the R

resistors at the respective terminals of the ISL6554.

SEN

Example: From the previous conditions,

where I

= 100A,

LT

A multi-layer printed circuit board is recommended. Figure 11

shows the connections of the critical components for one

I

= 25.49A,

= 4mΩ

SAMPLE

r

(Q2)

DS(ON)

Then: R

output channel of the converter. Note that capacitors C and

IN

= 2.04K and

= 165%

ISEN

C

could each represent numerous physical capacitors.

OUT

I

CURRENT TRIP

Dedicate one solid layer, usually the middle layer of the PC

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from

the PHASE terminal to output inductor short. The power plane

should support the input power and output power nodes. Use

Short circuit I

= 165A.

LT

Channel Frequency Oscillator

The channel oscillator frequency is set by placing a resistor,

R , to ground from the FS/DIS pin. Figure 10 is a curve

T

showing the relationship between frequency, F , and

SW

FN9003.3

12

February 11, 2005

ISL6554

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the driver IC to the

MOSFET gate and source should be sized to carry at least

one ampere of current.

Bulk capacitor choices include aluminum electrolytic, OS-

Con, Tantalum and even ceramic dielectrics. An aluminum

electrolytic capacitor’s ESR value is related to the case size

with lower ESR available in larger case sizes. However, the

equivalent series inductance (ESL) of these capacitors

increases with case size and can reduce the usefulness of

the capacitor to high slew-rate transient loading.

1,000

500

Unfortunately, ESL is not a specified parameter. Consult the

capacitor manufacturer and measure the capacitor’s

impedance with frequency to select a suitable component.

200

Output Inductor Selection

100

50

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Small inductors in a multi-phase converter reduces

the response time without significant increases in total ripple

current.

20

10

The output inductor of each power channel controls the

ripple current. The control IC is stable for channel ripple

current (peak-to-peak) up to twice the average current. A

single channel’s ripple current is approximately:

5

2

1

V

– V

V

IN

OUT

------------------------------- ---------------

∆I =

×

F

× L

SW

10 20

50 100 200

500 1,000 2,000 5,000 10,000

(kHz)

The current from multiple channels tend to cancel each other

and reduce the total ripple current. Figure 12 gives the total

ripple current as a function of duty cycle, normalized to the

CHANNEL OSCILLATOR FREQUENCY, F

SW

FIGURE 10. RESISTANCE R vs FREQUENCY

T

parameter (Vo) ⁄ (LxF ) at zero duty cycle. To determine

SW

Component Selection Guidelines

Output Capacitor Selection

the total ripple current from the number of channels and the

duty cycle, multiply the y-axis value by (Vo) ⁄ (LxF ) .

SW

The output capacitor is selected to meet both the dynamic

load requirements and the voltage ripple requirements. The

load transient for the microprocessor CORE is characterized

by high slew rate (di/dt) current demands. In general,

multiple high quality capacitors of different size and dielectric

are paralleled to meet the design constraints.

Small values of output inductance can cause excessive

power dissipation. The ISL6554 is designed for stable

operation for ripple currents up to twice the load current.

However, for this condition, the RMS current is 115% above

the value shown in the following MOSFET Selection and

Considerations section. With all else fixed, decreasing the

inductance could increase the power dissipated in the

MOSFETs by 30%.

Modern microprocessors produce severe transient load rates.

High frequency capacitors supply the initially transient current

and slow the load rate-of-change seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

1.0

SINGLE

0.8

CHANNEL

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

0.6

2 CHANNEL

0.4

3 CHANNEL

0.2

4 CHANNEL

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient’s edge. In most cases, multiple capacitors of small

case size perform better than a single large case capacitor.

0

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 11. RIPPLE CURRENT vs DUTY CYCLE

FN9003.3

13

February 11, 2005

ISL6554

+5V

IN

USE INDIVIDUAL METAL RUNS

FOR EACH CHANNEL TO HELP

ISOLATE OUTPUT STAGES

+12V

C

BP

VCC PVCC

LOCATE NEXT TO IC PIN(S)

C

BOOT

C

IN

LOCATE NEAR TRANSISTOR

VCC

L

C

PWM

O1

BP

V

CORE

HIP6601

PHASE

FS/DIS

COMP

C

OUT

C

T

ISL6554

R

T

R

FB

LOCATE NEXT

TO FB PIN

FB

LOCATE NEXT TO IC PIN

R

IN

R

SEN

VSEN

ISEN

KEY

ISLAND ON POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

ISLAND ON CIRCUIT PLANE LAYER

FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

Use a mix of input bypass capacitors to control the voltage

Input Capacitor Selection

overshoot across the MOSFETs. Use ceramic capacitance for

the high frequency decoupling and bulk capacitors to supply

the RMS current. Small ceramic capacitors should be placed

very close to the drain of the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

The important parameters for the bulk input capacitors are the

voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current required for a multi-phase

converter can be approximated with the aid of Figure 13.

For bulk capacitance, several electrolytic capacitors (Panasonic

HFQ series or Nichicon PL series or Sanyo MV-GX or

equivalent) may be needed. For surface mount designs, solid

tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

0.5

SINGLE

CHANNEL

0.4

0.3

0.2

0.1

0

MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the following

equations). The conduction losses are the main component

of power dissipation for the lower MOSFETs, Q2 and Q4 of

Figure 1. Only the upper MOSFETs, Q1 and Q3 have

significant switching losses, since the lower device turns on

and off into near zero voltage.

2 CHANNEL

3 CHANNEL

4 CHANNEL

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE

First determine the operating duty ratio as the ratio of the

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the Driver IC and don’t heat the MOSFETs.

However, large gate-charge increases the switching time,

output voltage divided by the input voltage. Find the Current

Multiplier from the curve with the appropriate power

channels. Multiply the current multiplier by the full load

output current. The resulting value is the RMS current rating

required by the input capacitor.

FN9003.3

14

February 11, 2005

ISL6554

t

which increases the upper MOSFET switching losses.

References

Intersil documents are available on the web at

www.intersil.com/

SW

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

[1] HIP6601/HIP6603 Data Sheet, Intersil Corporation,

File No. 4819

[2] HIP6602 Data Sheet, Intersil Corporation, File No. 4838

2

I

× r

× V

I

× V × t

× F

SW SW

O

DS(ON)

OUT

O

IN

P

= ------------------------------------------------------------ + ---------------------------------------------------------

UPPER

LOWER

V

2

IN

2

I

× r

× (V – V

OUT

)

O

DS(ON)

IN

= --------------------------------------------------------------------------------

V

IN

A diode, anode to ground, may be placed across Q2 and Q4

of Figure 1. These diodes function as a clamp that catches

the negative inductor swing during the dead time between

the turn off of the lower MOSFETs and the turn on of the

upper MOSFETs. The diodes must be a Schottky type to

prevent the lossy parasitic MOSFET body diode from

conducting. It is usually acceptable to omit the diodes and let

the body diodes of the lower MOSFETs clamp the negative

inductor swing, but efficiency could drop one or two percent

as a result. The diode’s rated reverse breakdown voltage

must be greater than the maximum input voltage.

FN9003.3

15

February 11, 2005

ISL6554

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

AREA

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.35

0.23

MAX

2.65

NOTES

E

A

A1

B

C

D

E

e

0.0926

0.0040

0.014

0.1043

0.0118

0.019

-

-B-

0.30

-

0.49

9

1

2

3

L

0.0091

0.4961

0.2914

0.0125

0.32

-

SEATING PLANE

A

0.5118 12.60

13.00

7.60

3

-A-

0.2992

7.40

4

o

D

h x 45

0.050 BSC

1.27 BSC

-

-C-

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

α

µ

5

e

A1

C

L

6

B

0.10(0.004)

N

α

20

7

M

S

B

0.25(0.010)

C

A

o

0

8

0

8

-

Rev. 1 1/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9003.3

16

February 11, 2005


型号：	ISL6554
厂家：	Intersil
描述：	Microprocessor CORE Voltage Regulator Using Multi-Phase Buck PWM Control Without Programmable Droop 微处理器核心电压调节器的使用多相降压PWM控制，而可编程下垂调节器微处理器多相元件
文件：	总16页 (文件大小：483K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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