ISL6552CB_技术文档

ISL6552

®

Data Sheet

October 2003

FN4918.1

Microproces s or CORE Voltage Regulator

Multi-Phas e Buck PWM Controller

Features

• Multi-Phase Power Conversion

The ISL6552 multi-phase PWM control IC together with its

companion gate drivers, the HIP6601, HIP6602 or HIP6603

and external Intersil MOSFETs provides a precision voltage

regulation system for advanced microprocessors.

• Precision Channel Current Sharing

- Loss Less Current Sampling - Uses r

DS(ON)

• Precision CORE Voltage Regulation

Multi-phase power conversion is a marked departure from

earlier single phase converter configurations previously

employed to satisfy the ever increasing current demands of

modern microprocessors. Multi-phase converters, by

distributing the power and load current results in smaller and

lower cost transistors with fewer input and output capacitors.

These reductions accrue from the higher effective

conversion frequency with higher frequency ripple current

due to the phase interleaving process of this topology. For

example, a three phase converter operating at 350kHz will

have a ripple frequency of 1.05MHz. Moreover, greater

converter bandwidth of this design results in faster response

to load transients.

- ±1% System Accuracy Over Temperature

• Microprocessor Voltage Identification Input

- 5-Bit VID Input

- 1.05V to 1.825V in 25mV Steps

- Programmable “Droop” Voltage

• Fast Transient Recovery Time

• Over Current Protection

• Automatic Selection of 2, 3, or 4 Phase Operation

• High Ripple Frequency (Channel Frequency) Times

Number Channels . . . . . . . . . . . . . . . . . .100kHz to 6MHz

• QFN Package:

Outstanding features of this controller IC include

- Compliant to JEDEC PUB95 MO-220

programmable VID codes from the microprocessor that

range from 1.05V to 1.825V with a system accuracy of ±1%.

Pull up currents on these VID pins eliminates the need for

external pull up resistors. In addition “droop” compensation,

used to reduce the overshoot or undershoot of the CORE

voltage, is easily programmed with a single resistor.

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

Ordering Information

o

PART NUMBER TEMP. ( C)

PACKAGE

PKG. DWG. #

Another feature of this controller IC is the PGOOD monitor

circuit which is held low until the CORE voltage increases,

during its Soft-Start sequence, to within 10% of the

programmed voltage. Over-voltage, 15% above

programmed CORE voltage, results in the converter shutting

down and turning the lower MOSFETs ON to clamp and

protect the microprocessor. Under voltage is also detected

and results in PGOOD low if the CORE voltage falls 10%

below the programmed level. Over-current protection

reduces the regulator RMS output current to 41% of the

programmed over-current trip value. These features provide

monitoring and protection for the microprocessor and power

system.

ISL6552CB

ISL6552CB-T

ISL6552CR

ISL6552CR-T

0 to 70

20 Ld SOIC

M20.3

20 Ld SOIC Tape and Reel

0 to 70

20 Ld 5x5 QFN L20.5x5

20 Ld QFN Tape and Reel

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6552

Pinouts

ISL6552CB (20 LEAD SOIC

ISL6552CR (20 LEAD 5x5 QFN)

TOP VIEW

1

2

20

19

18

17

16

15

14

13

12

11

VID3

VID2

VCC

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

20 19 18 17 16

3

VID1

4

VID0

VID1

1

2

3

4

5

15

ISEN4

ISEN1

5

VID25mV

COMP

FB

VID0

14

6

13 PWM1

VID25mV

COMP

FB

GND

7

8

FS/DIS

GND

12

11

PWM2

ISEN2

9

10

VSEN

6

7

8

9

10

2

ISL6552

Block Diagram

PGOOD

VCC

POWER-ON

RESET (POR)

UV

THREE

STATE

VSEN

+

-

X 0.9

OV

LATCH

CLOCK AND

SAWTOOTH

GENERATOR

S

FS/EN

PWM1

OVP

+

-

+

PWM

∑

X1.15

+

-

SOFT-

START

AND FAULT

LOGIC

+

∑

PWM2

+

-

COMP

+

PWM

∑

PWM3

PWM4

+

-

VID3

VID2

+

VID1

D/A

∑

+

-

E/A

-

+

-

VID0

VID25mV

PHASE

NUMBER

CHANNEL

DETECTOR

CURRENT

CORRECTION

FB

I_TOT

ISEN1

+

ISEN2

ISEN3

∑

+

-

+

OC

I_TRIP

ISEN4

GND

3

ISL6552

Simplified Power Sys tem Diagram

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

VSEN

PWM 1

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 2

MICROPROCESSOR

ISL6552

PWM 3

PWM 4

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

VID

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

VID3, VID2, VID1, VID0 and VID25mV

Functional Pin Des cription

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The ISL6552 decodes

VID bits to establish the output voltage. See Table 1.

ISL6552CB (20 LEAD SOIC)

1

2

20

19

18

17

16

15

14

13

12

11

VID3

VID2

VCC

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

COMP

3

VID1

4

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

VID0

5

VID25mV

COMP

FB

6

FB

7

Inverting input of the internal error amplifier.

8

FS/DIS

GND

FS/DIS

9

10

VSEN

Channel frequency, F , select and disable. A resistor from

SW

this pin to ground sets the switching frequency of the

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

ISL6552CR (20 LEAD 5x5 QFN)

GND

Bias and reference ground. All signals are referenced to this

pin.

20 19 18 17 16

VID1

VID0

1

2

15

14

ISEN4

ISEN1

VSEN

Power good monitor input. Connect to the microprocessor-

CORE voltage.

3

13 PWM1

VID25mV

COMP

FB

GND

PWM1, PWM2, PWM3 and PWM4

4

5

12

11

PWM2

ISEN2

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601, HIP6602, HIP6603

driver. For systems which use 3 channels, connect PWM4

high. Two channel systems connect PWM3 and PWM4 high.

6

7

8

9

10

4

ISL6552

ISEN1, ISEN2, ISEN3 and ISEN4

PGOOD

Current sense inputs from the individual converter channel’s

phase nodes. Unused sense lines MUST be left open.

Power good. This pin provides a logic-high signal when the

microprocessor CORE voltage (VSEN pin) is within specified

limits and Soft-Start has timed out.

VCC

Bias supply. Connect this pin to a 5V supply.

Typical Application - 2 Phas e Converter Us ing HIP6601 Gate Drivers

+12V

V

= +5V

IN

BOOT

PVCC

VCC

UGATE

PHASE

+5V

DRIVER

HIP6601

PWM

LGATE

GND

FB

COMP

VCC

VSEN

+V

CORE

PWM4

PWM3

+12V

PGOOD

VID3

V

= +5V

PWM2

PWM1

IN

BOOT

VID2

VID1

PVCC

UGATE

PHASE

MAIN

CONTROL

ISL6552

VID0

VCC

DRIVER

HIP6601

VID25mV

PWM

NC

ISEN4

ISEN3

ISEN2

ISEN1

LGATE

GND

FS/DIS

GND

5

ISL6552

Typical Application - 4 Phas e Converter Us ing HIP6602 Gate Drivers

V

= +12V

IN

+12V

BOOT1

UGATE1

PHASE1

L

01

VCC

LGATE1

PVCC

+5V

DUAL

DRIVER

HIP6602

+5V

V

+12V

IN

BOOT2

FB

VSEN

COMP

VCC

UGATE2

PHASE2

L

02

ISEN1

PWM1

PWM2

PGOOD

VID3

PWM2

ISEN2

LGATE2

VID2

VID1

MAIN

GND

CONTROL

ISL6552

VID0

+V

CORE

VID25mV

FS/DIS

ISEN3

PWM3

PWM4

V

+12V

IN

+12V

BOOT3

ISEN4

GND

UGATE3

PHASE3

L

03

VCC

LGATE3

PVCC

DUAL

DRIVER

HIP6602

+5V

V

+12V

BOOT4

IN

UGATE4

PHASE4

L

04

PWM3

PWM4

LGATE4

GND

6

ISL6552

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5KV

Thermal Resistance

θ

( C/W)

θ

( C/W)

JA

JC

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Notes 2, 3). . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

65

33

NA

4.5

o

Recommended Operating Conditions

o

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

(SOIC - Lead Tips Only)

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

o

Electrical Specifications Operating Conditions: VCC = 5V, T = 0 C to 70 C, Unless Otherwise Specified

A

PARAMETER

INPUT SUPPLY POWER

Input Supply Current

TEST CONDITIONS

MIN

TYP MAX UNITS

R

= 100kΩ

-

10

15

4.5

mA

V

T

POR (Power-On Reset) Threshold

VCC Rising

VCC Falling

4.25

3.75

4.38

3.88

4.00

V

REFERENCE AND DAC

DAC Voltage Accuracy

DAC Pin Input Low Voltage Threshold

DAC Pin Input High Voltage Threshold

VID Pull-Up

-1

-

1

0.8

-

%

V

2.0

10

-

V

VIDx = 0V or VIDx = 3V

20

40

µA

OSCILLATOR

Frequency, F

SW

R

= 100kΩ, ±1%

224

0.05

-

280

-

336

1.5

1.0

kHz

MHz

V

T

Adjustment Range

(See Figure 10)

Maximum voltage at FS/DIS to disable controller. I

Disable Voltage

= 1mA.

1.2

FS/DIS

ERROR AMPLIFIER

DC Gain

R

C

R

= 10K to ground

-

72

18

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product

Slew Rate

= 100pF, R = 10K to ground

-

L

= 100pF, R = 10K to ground

L

5.3

4.1

0.16

Maximum Output Voltage

Minimum Output Voltage

ISEN

= 10K to ground

3.6

-

0.5

V

Full Scale Input Current

Over-Current Trip Level

POWER GOOD MONITOR

Under-Voltage Threshold

PGOOD Low Output Voltage

PROTECTION

-

50

-

µA

82.5

VSEN Rising

VSEN Falling

-

0.92

0.90

0.18

-

V

DAC

V

DAC

V

I

= 4mA

0.4

PGOOD

Over-Voltage Threshold

Percent Over-Voltage Hysteresis

VSEN Rising

1.12

-

1.15

2

1.2

-

V

DAC

%

VSEN Falling after Over-Voltage

7

ISL6552

R

IN

FB

V

IN

ISL6552

ERROR

AMPLIFIER

COMPARATOR

L1

Q1

PWM1

ISEN1

CORRECTION

PWM

-

+

HIP6601

-

CIRCUIT

∑

+

I

L1

+

-

Q2

PHASE

PROGRAMMABLE

REFERENCE

DAC

+

R

ISEN1

CURRENT

SENSING

∑

-

I AVERAGE

CURRENT

V

CORE

AVERAGING

C

R

-

OUT

LOAD

R

+

ISEN2

PWM2

CURRENT

SENSING

∑

V

IN

PHASE

L2

COMPARATOR

-

Q3

+

PWM

+

-

HIP6601

CIRCUIT

CORRECTION

I

L2

Q4

FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6552 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER

CHANNEL REGULATOR

This increased duty cycle signal is passed through the PWM

circuit with no phase reversal and on to the HIP6601, again

with no phase reversal for gate drive to the upper MOSFETs,

Q1 and Q3. Increased duty cycle or ON time for the

MOSFET transistors results in increased output voltage to

compensate for the low output voltage sensed.

Operation

Figure 1 shows a simplified diagram of the voltage regulation

and current control loops. Both voltage and current feedback

are used to precisely regulate voltage and tightly control

output currents, I and I , of the two power channels. The

L1 L2

voltage loop comprises the error amplifier, comparators,

gate drivers and output MOSFETs. The error amplifier is

essentially connected as a voltage follower that has as an

input, the programmable reference DAC and an output that

is the CORE voltage.

Current Loop

The current control loop works in a similar fashion to the

voltage control loop, but with current control information

applied individually to each channel’s comparator. The

information used for this control is the voltage that is

Voltage Loop

developed across r

of each lower MOSFET, Q2 and

DS(ON)

Feedback from the CORE voltage is applied via resistor R

to the inverting input of the error amplifier. This signal can

IN

Q4, when they are conducting. A single resistor converts

and scales the voltage across the MOSFETs to a current

that is applied to the current sensing circuit within the

ISL6552. Output from these sensing circuits is applied to the

current averaging circuit. Each PWM channel receives the

difference current signal from the summing circuit that

compares the average sensed current to the individual

channel current. When a power channel’s current is greater

than the average current, the signal applied via the summing

correction circuit to the comparator, reduces the output pulse

drive the error amplifier output either high or low, depending

upon the CORE voltage. Low CORE voltage makes the

amplifier output move towards a higher output voltage level.

Amplifier output voltage is applied to the positive inputs of

the comparators via the correction summing networks.

Out-of-phase sawtooth signals are applied to the two

comparators inverting inputs. Increasing error amplifier

voltage results in increased comparator output duty cycle.

8

ISL6552

width of the comparator to compensate for the detected

“above average” current in that channel.

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

Droop Compens ation

In addition to control of each power channel’s output current,

the average channel current is also used to provide CORE

voltage “droop” compensation. Average full channel current

Initialization

The ISL6552 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to

the VCC pin of the ISL6552. Oscillator, sawtooth generator,

soft-start and other functions are initialized during this

interval. These circuits are controlled by POR, Power-On

Reset. During this interval, the PWM outputs are driven to a

three state condition that makes these outputs essentially

open. This state results in no gate drive to the output

MOSFETs.

is defined as 50µA. By selecting an input resistor, R , the

IN

amount of voltage droop required at full load current can be

programmed. The average current driven into the FB pin

results in a voltage increase across resistor R that is in the

IN

direction to make the error amplifier “see” a higher voltage at

the inverting input, resulting in the error amplifier adjusting

the output voltage lower. The voltage developed across R

IN

is equal to the “droop” voltage. See the “Current Sensing

and Balancing” section for more details.

Once the VCC voltage reaches 4.375V (+125mV), a voltage

level to insure proper internal function, the PWM outputs are

enabled and the Soft-Start sequence is initiated. If for any

reason, the VCC voltage drops below 3.875V (+125mV).

The POR circuit shuts the converter down and again three

states the PWM outputs.

Applications and Converter Start-Up

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601, HIP6602 or

HIP6603 MOSFET driver interfaces with the ISL6552. For

more information, see the HIP6601, HIP6602 or HIP6603

data sheets [1][2].

Soft-Start

After the POR function is completed with VCC reaching

4.375V, the Soft-Start sequence is initiated. Soft-Start, by its

slow rise in CORE voltage from zero, avoids an over-current

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the ISL6552, therefore, the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

The ISL6552 is capable of controlling up to 4 PWM power

channels. Connecting unused PWM outputs to VCC

automatically sets the number of channels. The phase

o

relationship between the channels is 360 /number of active

PWM channels. For example, for three channel operation,

o

the PWM outputs are separated by 120 . Figure 2 shows

the PWM output signals for a four channel system.

For the first 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles the PWM output remains low, clamping the lower

output MOSFETs to ground, see Figure 3. The time

variability is due to the error amplifier, sawtooth generator

and comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

PWM 1

PWM 2

PWM 3

PWM 4

The Soft-Start time or delay time, DT = 2048/F . For an

SW

FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz

oscillator frequency, F , of 200kHz, the first 32 cycles or

SW

160µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of

10.24ms.

Power supply ripple frequency is determined by the channel

frequency, F , multiplied by the number of active

SW

channels. For example, if the channel frequency is set to

250kHz and there are three phases, the ripple frequency is

750kHz.

9

ISL6552

Figure 3 shows the start-up sequence as initiated by a fast

rising 5V supply, VCC applied to the ISL6552. Note the

short rise to the three state level in PWM 1 output during first

32 PWM cycles.

,

12V ATX

SUPPLY

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the channel frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram).

PGOOD

V

CORE

5 V ATX

SUPPLY

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is made up of NMOS and

PMOS transistors. On the rising VCC, the PMOS device

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

V

= 5V, CORE LOAD CURRENT = 31A

FREQUENCY 200kHz

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the ISL6552 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the ISL6552 will sense an over-current

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

PWM 1

OUTPUT

DELAY TIME

PGOOD

Fault Protection

V

The ISL6552 protects the microprocessor and the entire

power system from damaging stress levels. Within the

ISL6552 both Over-Voltage and Over-Current circuits are

incorporated to protect the load and regulator.

CORE

5V

VCC

Over-Voltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE over-voltage condition is detected when

the VSEN pin goes more than 15% above the programmed

VID level.

V

= 12V

IN

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

The over-voltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and Soft-Start sequence.

V COMP

During a latched over-voltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, resulting in the lower or synchronous rectifier

MOSFETs to conduct and shunt the CORE voltage to

ground to protect the load.

DELAY TIME

PGOOD

V

CORE

5V

VCC

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

V

= 12V

IN

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

10

ISL6552

destructive ringing of the capacitors and output inductors. If

the conditions that caused the over-voltage still persist, the

Table 1 shows the nominal DAC voltage as a function of the

VID codes. The power supply system is ±1% accurate over

PWM outputs will be cycled between three state and V

clamped to ground, as a hysteretic shunt regulator.

the operating temperature and voltage range.

CORE

TABLE 1. VOLTAGE IDENTIFICATION CODES

Under-Voltage

VOLTAGE IDENTIFICATION CODE AT

PROCESSOR PINS

The VSEN pin also detects when the CORE voltage falls

more than 10% below the VID programmed level. This

causes PGOOD to go low, but has no other effect on

operation and is not latched. There is also hysteresis in this

detection point.

VCC

CORE

VID25mV

VID3

0

1

0

VID2

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(V

)

DC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.05

1.075

1.10

Over-Current

1.125

1.15

In the event of an over-current condition, the over-current

protection circuit reduces the RMS current delivered to 41%

of the current limit. When an over-current condition is

detected, the controller forces all PWM outputs into a three

state mode. This condition results in the gate driver

removing drive to the output stages. The ISL6552 goes into

a wait delay timing cycle that is equal to the Soft-Start ramp

time. PGOOD also goes “low” during this time due to VSEN

going below its threshold voltage. To lower the average

output dissipation, the Soft-Start initial wait time is increased

from 32 to 2048 cycles, then the Soft-Start ramp is initiated.

At a PWM frequency of 200kHz, for instance, an over-

current detection would cause a dead time of 10.24ms, then

a ramp of 10.08ms.

1.175

1.20

1.225

1.25

1.275

1.30

1.325

1.35

1.375

1.40

At the end of the delay, PWM outputs are restarted and the

soft start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

1.425

1.45

Figure 6 shows the supply shorted under operation and the

hiccup operating mode described above. Note that due to

the high short circuit current, over-current is detected before

completion of the start-up sequence so the delay is not quite

as long as the normal Soft-Start cycle.

1.475

1.50

1.525

1.55

1.575

1.60

SHORT APPLIED HERE

PGOOD

1.625

1.65

SHORT

CURRENT

50A/DIV

1.675

1.70

HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY

CORE LOAD CURRENT = 31A, 5V LOAD = 5A

1.725

1.75

SUPPLY FREQUENCY = 200kHz, V = 12V

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

1.775

1.80

FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP

1.825

CORE Voltage Programming

The voltage identification pins (VID0, VID1, VID3, and

VID25mV) set the CORE output voltage. Each VID pin is

pulled to VCC by an internal 20µA current source and

accepts open-collector/open-drain/open-switch-to-ground or

standard low-voltage TTL or CMOS signals.

11

ISL6552

R

IN

C

R

c

FB

COMP

FB

V

IN

ISL6552

SAWTOOTH

COMPARATOR

L

Q1

01

ERROR

AMPLIFIER

GENERATOR

V

CORE

PWM

-

+

HIP6601

CIRCUIT

CORRECTION

+

PWM

ISEN

I

L

-

+

Q2

-

PHASE

DIFFERENCE

REFERENCE

DAC

R

ISEN

+

CURRENT

SENSING

-

ONLY ONE OUTPUT

STAGE SHOWN

TO OTHER

CHANNELS

CURRENT

SENSING

FROM

OTHER

CHANNELS

INDUCTOR

CURRENT(S)

FROM

AVERAGING

TO OVER

CURRENT

TRIP

+

-

OTHER

CHANNELS

REFERENCE

COMPARATOR

FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING

Current Sens ing and Balancing

The nominal current through the R

resistor should be

Overview

ISEN

50µA at full output load current, and the nominal trip point for

over-current detection is 165% of that value, or 82.5µA.

The ISL6552 samples the on-state voltage drop across each

synchronous rectifier FET, Q2, as an indication of the

inductor current in that phase, see Figure 7. Neglecting AC

effects (to be discussed later), the voltage drop across Q2 is

Therefore, R

ISEN

= I x r

(Q2)/50µA.

DS(ON)

L

For a full load of 25A per phase, and an r

DS(ON)

(Q2) of

simply r

(Q2) x inductor current (I ). Note that I , the

DS(ON)

L L

4mΩ, R

= 2kΩ.

ISEN

The over-current trip point would be 165% of 25A, or ~41A

per phase. The R value can be adjusted to change the

inductor current, is either 1/2, 1/3, or 1/4 of the total current

(I ), depending on how many phases are in use.

LT

ISEN

The voltage at Q2’s drain, the PHASE node, is applied to the

over-current trip point, but it is suggested to stay within

R

resistor to develop the I

current to the ISL6552

±25% of nominal.

ISEN

ISEN pin. This pin is held at virtual ground, so the current

Droop, Selection of R

IN

through R is I x r (Q2)/R

.

ISEN

L

DS(ON)

ISEN

The average of the currents detected through the R

ISEN

resistors is also steered to the FB pin. There is no DC return

path connected to the FB pin except for R , so the average

The I

ISEN

current provides information to perform the

following functions:

IN

current creates a voltage drop across R . This drop

IN

voltage with increasing load

1. Detection of an over-current condition

increases the apparent V

CORE

2. Reduce the regulator output voltage with increasing load

current (droop)

current, causing the system to decrease V

to maintain

CORE

balance at the FB pin. This is the desired “droop” voltage used

to maintain V within limits under transient conditions.

3. Balance the I currents in multiple channels

L

CORE

Over-Current, Selecting R

ISEN

The current detected through the R

With a high dv/dt load transient, typical of high performance

microprocessors, the largest deviations in output voltage occur

at the leading and trailing edges of the load transient. In order to

fully utilize the output-voltage tolerance range, the output

voltage is positioned in the upper half of the range when the

output is unloaded and in the lower half of the range when the

resistor is

ISEN

averaged with the current(s) detected in the other 1, 2, or 3

channels. The averaged current is compared with a

trimmed, internally generated current, and used to detect

an over-current condition.

12

ISL6552

controller is under full load. This droop compensation allows

larger transient voltage deviations and thus reduces the size

and cost of the output filter components.

average current per phase. Neglecting secondary effects,

the sampled current (I

) can be related to the load

SAMPLE

current (I ) by:

LT

2

R

should be selected to give the desired “droop” voltage at

I

=

I

/ n + (V V

IN CORE

-3V

)/(6L x F x V )

SW IN

IN

SAMPLE LT

CORE

the normal full load current 50µA applied through the R

resistor (or at a different full load current if adjusted as

ISEN

Where:

I

= total load current

LT

n = the number of channels

outlined in the Over-Current, Selecting R

section).

ISEN

Example: Using the previously given conditions, and

For

R

= Vdroop/50µA

IN

I

= 100A,

LT

n = 4

= 25.49A

For a Vdroop of 80mV, R = 1.6kΩ

IN

The AC feedback components, R and Cc, are scaled in

Then

I

SAMPLE

FB

relation to R

.

IN

Current Balancing

The detected currents are also used to balance the phase

currents.

25

20

15

10

5

Each phase’s current is compared to the average of all

phase currents, and the difference is used to create an offset

in that phase’s PWM comparator. The offset is in a direction

to reduce the imbalance.

The balancing circuit can not make up for a difference in

0

r

between synchronous rectifiers. If a FET has a higher

, the current through that phase will be reduced.

DS(ON)

r

DS(ON)

Figures 8 and 9 show the inductor current of a two phase

system without and with current balancing.

FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH

CURRENT BALANCING DISABLED

Inductor Current

The inductor current in each phase of a multi-phase Buck

converter has two components. There is a current equal to

the load current divided by the number of phases (I / n),

LT

and a sawtooth current, (i

) resulting from switching.

PK-PK

25

20

15

10

5

The sawtooth component is dependent on the size of the

inductors, the switching frequency of each phase, and the

values of the input and output voltage. Ignoring secondary

effects, such as series resistance, the peak to peak value of

the sawtooth current can be described by:

2

i

= (V x V

IN CORE

- V

)/(L x F

SW

x V )

IN

PK-PK

Where:

CORE

V

= DC value of the output or V voltage

ID

CORE

0

V

= DC value of the input or supply voltage

IN

L = value of the inductor

= switching frequency

F

SW

Example: For V

V

=1.6V,

CORE

= 12V,

FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH

CURRENT BALANCING ENABLED

IN

L = 1.3µH,

= 250kHz,

F

SW

= 4.3A

As discussed previously, the voltage drop across each Q2

transistor at the point in time when current is sampled is

Then i

PK-PK

The inductor, or load current, flows alternately from V

r

(Q2) x I

. The voltage at Q2’s drain, the

IN

DSON

PHASE node, is applied through the R

SAMPLE

through Q1 and from ground through Q2. The ISL6552

samples the on-state voltage drop across each Q2 transistor

to indicate the inductor current in that phase. The voltage

resistor to the

ISEN

ISL6552 ISEN pin. This pin is held at virtual ground, so the

current into ISEN is:

drop is sampled 1/3 of a switching period, i/F , after Q1 is

turned OFF and Q2 is turned on. Because of the sawtooth

current component, the sampled current is different from the

SW

I

= I

x r

(Q2)/R .

ISEN

SENSE

= I

SAMPLE DS(ON)

x r (Q2)/50µA

DS(ON)

R

Isen

SAMPLE

13

ISL6552

Example: From the previous conditions,

especially important to place the R

resistors at the

SEN

respective terminals of the ISL6552.

where:

I

= 100A,

LT

= 25.49A,

= 4mΩ

A multi-layer printed circuit board is recommended. Figure 11

shows the connections of the critical components for one

SAMPLE

r

(Q2)

DS(ON)

output channel of the converter. Note that capacitors C and

Then:

R

= 2.04K and

= 165%

IN

ISEN

C

could each represent numerous physical capacitors.

OUT

I

CURRENT TRIP

Short circuit I

Dedicate one solid layer, usually the middle layer of the PC

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from

the PHASE terminal to output inductor short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the driver IC to the

MOSFET gate and source should be sized to carry at least

one ampere of current.

= 165A.

LT

Channel Frequency Os cillator

The channel oscillator frequency is set by placing a resistor,

R , to ground from the FS/DIS pin. Figure 10 is a curve

T

showing the relationship between frequency, F

resistor R . To avoid pickup by the FS/DIS pin, it is important

to place this resistor next to the pin.

and

SW,

T

Layout Cons iderations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another causes

voltage spikes across the interconnecting impedances and

parasitic circuit elements. These voltage spikes can degrade

efficiency, radiate noise into the circuit and lead to device over-

voltage stress. Careful component layout and printed circuit

design minimizes the voltage spikes in the converter. Consider,

as an example, the turnoff transition of the upper PWM

MOSFET. Prior to turnoff, the upper MOSFET was carrying

channel current. During the turnoff, current stops flowing in the

upper MOSFET and is picked up by the lower MOSFET. Any

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful component

selection, tight layout of the critical components, and short,

wide circuit traces minimize the magnitude of voltage spikes.

Contact Intersil for evaluation board drawings of the

1,000

500

200

100

50

20

10

5

component placement and printed circuit board.

2

1

There are two sets of critical components in a DC-DC

converter using a ISL6552 controller and a HIP6601 gate

driver. The power components are the most critical because

they switch large amounts of energy. Next are small signal

components that connect to sensitive nodes or supply critical

bypassing current and signal coupling.

10

20

50 100 200

500 1,000 2,000 5,000 10,000

(kHz)

CHANNEL OSCILLATOR FREQUENCY, F

SW

FIGURE 10. RESISTANCE R vs FREQUENCY

T

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

Component Selection Guidelines

length of the connections between the input capacitors, C

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the gate driver close to the MOSFETs.

,

Output Capacitor Selection

IN

The output capacitor is selected to meet both the dynamic

load requirements and the voltage ripple requirements. The

load transient for the microprocessor CORE is characterized

by high slew rate (di/dt) current demands. In general,

multiple high quality capacitors of different size and dielectric

are paralleled to meet the design constraints.

The critical small components include the bypass capacitors

for VCC and PVCC on the gate driver ICs. Locate the

bypass capacitor, C , for the ISL6552 controller close to

BP

the device. It is especially important to locate the resistors

associated with the input to the amplifiers close to their

respective pins, since they represent the input to feedback

Modern microprocessors produce severe transient load rates.

High frequency capacitors supply the initially transient current

and slow the load rate-of-change seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

amplifiers. Resistor R , that sets the oscillator frequency

T

should also be located next to the associated pin. It is

14

ISL6552

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

current (peak-to-peak) up to twice the average current. A

single channel’s ripple current is approximately:

V

– V

V

IN

F

OUT

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

------------------------------- ---------------

∆I =

×

× L

V

IN

SW

The current from multiple channels tend to cancel each other

and reduce the total ripple current. Figure 12 gives the total

ripple current as a function of duty cycle, normalized to the

parameter (Vo) ⁄ (LxF ) at zero duty cycle. To determine

SW

the total ripple current from the number of channels and the

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient’s edge. In most cases, multiple capacitors of small

case size perform better than a single large case capacitor.

duty cycle, multiply the y-axis value by (Vo) ⁄ (LxF ) .

SW

Small values of output inductance can cause excessive

power dissipation. The ISL6552 is designed for stable

operation for ripple currents up to twice the load current.

However, for this condition, the RMS current is 115% above

the value shown in the following MOSFET Selection and

Considerations section. With all else fixed, decreasing the

inductance could increase the power dissipated in the

MOSFETs by 30%.

Bulk capacitor choices include aluminum electrolytic, OS-

Con, Tantalum and even ceramic dielectrics. An aluminum

electrolytic capacitor’s ESR value is related to the case size

with lower ESR available in larger case sizes. However, the

equivalent series inductance (ESL) of these capacitors

increases with case size and can reduce the usefulness of

the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Consult the

capacitor manufacturer and measure the capacitor’s

impedance with frequency to select a suitable component.

1.0

SINGLE

0.8

0.6

0.4

0.2

0

CHANNEL

2 CHANNEL

Output Inductor Selection

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Small inductors in a multi-phase converter reduces

the response time without significant increases in total ripple

current.

3 CHANNEL

4 CHANNEL

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

The output inductor of each power channel controls the

ripple current. The control IC is stable for channel ripple

O

FIGURE 11. RIPPLE CURRENT vs DUTY CYCLE

+5V

IN

USE INDIVIDUAL METAL RUNS

FOR EACH CHANNEL TO HELP

ISOLATE OUTPUT STAGES

+12V

C

BP

VCC PVCC

LOCATE NEXT TO IC PIN(S)

C

BOOT

C

IN

LOCATE NEAR TRANSISTOR

VCC

L

C

PWM

O1

BP

V

CORE

HIP6601

PHASE

FS/DIS

COMP

C

OUT

C

T

ISL6552

R

T

R

FB

LOCATE NEXT

TO FB PIN

FB

V

LOCATE NEXT TO IC PIN

SEN

R

IN

R

I

SEN

KEY

ISLAND ON POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

ISLAND ON CIRCUIT PLANE LAYER

FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

15

ISL6552

MOSFETs according to duty factor (see the following

Input Capacitor Selection

equations). The conduction losses are the main component

of power dissipation for the lower MOSFETs, Q2 and Q4 of

Figure 1. Only the upper MOSFETs, Q1 and Q3 have

significant switching losses, since the lower device turns on

and off into near zero voltage.

The important parameters for the bulk input capacitors are the

voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current required for a multi-phase

converter can be approximated with the aid of Figure 13.

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the Driver IC and don’t heat the MOSFETs.

However, large gate-charge increases the switching time,

0.5

t

which increases the upper MOSFET switching losses.

SW

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

SINGLE

CHANNEL

0.4

0.3

0.2

0.1

0

2 CHANNEL

3 CHANNEL

2

I

× r

× V

I

× V × t

× F

SW SW

O

DS(ON)

OUT

O

IN

------------------------------------------------------------ ---------------------------------------------------------

P

=

+

UPPER

LOWER

V

2

IN

4 CHANNEL

0.1

2

I

× r

× (V – V

)

OUT

O

DS(ON)

IN

--------------------------------------------------------------------------------

=

V

IN

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

A diode, anode to ground, may be placed across Q2 and Q4

of Figure 1. These diodes function as a clamp that catches

the negative inductor swing during the dead time between

the turn off of the lower MOSFETs and the turn on of the

upper MOSFETs. The diodes must be a Schottky type to

prevent the lossy parasitic MOSFET body diode from

conducting. It is usually acceptable to omit the diodes and let

the body diodes of the lower MOSFETs clamp the negative

inductor swing, but efficiency could drop one or two percent

as a result. The diode's rated reverse breakdown voltage

must be greater than the maximum input voltage.

FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE

First determine the operating duty ratio as the ratio of the

output voltage divided by the input voltage. Find the Current

Multiplier from the curve with the appropriate power

channels. Multiply the current multiplier by the full load

output current. The resulting value is the RMS current rating

required by the input capacitor.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance for

the high frequency decoupling and bulk capacitors to supply

the RMS current. Small ceramic capacitors should be placed

very close to the drain of the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

References

Intersil documents are available on the web at

www.intersil.com/

[1] HIP6601/HIP6603 Data Sheet, Intersil Corporation,

For bulk capacitance, several electrolytic capacitors

File No. 4819

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs,

solid tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

[2] HIP6602 Data Sheet, Intersil Corporation, File No. 4838

MOSFET Selection and Cons iderations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

16

ISL6552

Small Outline Plas tic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

AREA

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.35

0.23

MAX

2.65

NOTES

E

A

A1

B

C

D

E

e

0.0926

0.0040

0.014

0.1043

0.0118

0.019

-

-B-

0.30

-

0.49

9

1

2

3

L

0.0091

0.4961

0.2914

0.0125

0.32

-

SEATING PLANE

A

0.5118 12.60

13.00

7.60

3

-A-

0.2992

7.40

4

o

D

h x 45

0.050 BSC

1.27 BSC

-

-C-

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

α

µ

5

e

A1

C

L

6

B

0.10(0.004)

N

α

20

7

M

S

B

0.25(0.010)

C

A

o

0

8

0

8

-

Rev. 1 1/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

17

ISL6552

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L20.5x5

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHC ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.23

2.95

0.28

0.38

3.25

5, 8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7, 8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7, 8

0.65 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

20

5

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 3 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

18


型号：	ISL6552CB
厂家：	Intersil
描述：	Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller 微处理器核心电压调节器多相降压PWM控制器调节器微处理器多相元件控制器
文件：	总18页 (文件大小：459K)
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ISL6552CB [INTERSIL]

相关型号：

ISL6552CB-T

ISL6552CBZ

ISL6552CBZ-T

ISL6552CR

ISL6552CR-T

ISL6552CRZ

ISL6552_04

ISL6553

ISL6553CB

ISL6553CB

ISL6553CB-T

ISL6553CB-T