ISL6551_06_技术文档

ISL6551

®

Data Sheet

January 3, 2006

FN9066.5

ZVS Full Bridge PWM Controller

Features

The ISL6551 is a zero voltage switching (ZVS) full-bridge

PWM controller designed for isolated power systems. This

part implements a unique control algorithm for fixed-

frequency ZVS current mode control, yielding high efficiency

with low EMI. The two lower drivers are PWM-controlled on

the trailing edge and employ resonant delay while the two

upper drivers are driven at a fixed 50% duty cycle.

• High Speed PWM (up to 1MHz) for ZVS Full Bridge

Control

• Current Mode Control Compatible

• High Current High-Side and Low-Side Totem-Pole Drivers

• Adjustable Resonant Delay for ZVS

• 10MHz Error Amplifier Bandwidth

• Programmable Soft-Start

2

This IC integrates many features in both 6x6 mm QFN and

28-lead SOIC packages to yield a complete and

sophisticated power supply solution. Control features include

programmable soft-start for controlled start-up,

• Precision Bandgap Reference

• Latching Shutdown Input

programmable resonant delay for zero voltage switching,

programmable leading edge blanking to prevent false

triggering of the PWM comparator due to the leading edge

spike of the current ramp, adjustable ramp for slope

compensation, drive signals for implementing synchronous

rectification in high output current, ultra high efficiency

applications, and current share support for paralleling up to

10 units, which helps achieve higher reliability and

availability as well as better thermal management. Protective

features include adjustable cycle-by-cycle peak current

limiting for overcurrent protection, fast short-circuit protection

(in hiccup mode), a latching shutdown input to turn off the IC

completely on output overvoltage conditions or other

extreme and undesirable faults, a non-latching enable input

to accept an enable command when monitoring the input

voltage and thermal condition of a converter, and VDD under

voltage lockout with hysteresis. Additionally, the ISL6551

includes high current high-side and low-side totem-pole

drivers to avoid additional external drivers for moderate gate

capacitance (up to 1.6nF at 1MHz) applications, an

uncommitted high bandwidth (10MHz) error amplifier for

feedback loop compensation, a precision bandgap reference

with ±1.5% (ISL6551AB) or ±1% (ISL6551IB) tolerance over

recommended operating conditions, and a ±5% “in

regulation” monitor.

• Non-latching Enable Input

• Adjustable Leading Edge Blanking

• Adjustable Dead Time Control

• Adjustable Ramp for Slope Compensation

• Fast Short-Circuit Protection (Hiccup Mode)

• Adjustable Cycle-by-Cycle Peak Current Limiting

• Drive Signals to Implement Synchronous Rectification

• VDD Under-voltage Lockout

• Current Share Support

• ±5% “In Regulation” Indication

• QFN Package:

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Full-Bridge and Push-Pull Converters

• Power Supplies for Off-line and Telecom/Datacom

In addition to the ISL6551, other external elements such as

transformers, pulse transformers, capacitors, inductors and

Schottky or synchronous rectifiers are required for a

complete power supply solution. A detailed 200W telecom

power supply reference design using the ISL6551 with

companion Intersil ICs, Supervisor And Monitor ISL6550 and

Half-bridge Driver HIP2100, is presented in Application Note

AN1002.

• Power Supplies for High End Microprocessors and

Servers

In addition, the ISL6551 can also be designed in push-pull

converters using all of the features except the two upper

drivers and adjustable resonant delay features.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6551

Ordering Information

Ordering Information (Continued)

PART

TEMP

PKG.

PART

TEMP

PKG.

NUMBER

RANGE (°C)

PACKAGE

28 Ld SOIC

DWG. #

NUMBER

RANGE (°C)

PACKAGE

DWG. #

ISL6551IB

0 to 85

M28.3

ISL6551EVAL1

Evaluation Platform (ISL6551IR only)

ISL6551IBZ (Note)

ISL6551IR

28 Ld SOIC (Pb-free) M28.3

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

28 Ld 6x6 QFN

L28.6x6

ISL6551IRZ (Note)

28 Ld 6x6 QFN

(Pb-free)

ISL6551ABZ (Note) -40 to 105 28 Ld SOIC (Pb-free) M28.3

ISL6551AR

-40 to 105 28 Ld 6x6 QFN

L28.6x6

ISL6551ARZ (Note) -40 to 105 28 Ld 6x6 QFN

(Pb-free)

Pinouts

28 PIN WIDE BODY (SOIC)

28 PIN (QFN)

TOP VIEW

1

2

28 VDD

VSS

CT

VDDP1

VDDP2

27

26

28 27 26 25 24 23 22

3

RD

25 PGND

4

R_RESDLY

R_RA

R_RESDLY

R_RA

UPPER1

UPPER2

LOWER1

LOWER2

SYNC1

1

2

3

4

5

6

7

21

20

19

18

17

16

15

5

24 UPPER1

23 UPPER2

22 LOWER1

21 LOWER2

20 SYNC1

6

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

CSS

ISENSE

PKILIM

7

8

9

BGREF

R_LEB

10

11

12

13

14

19

18

17

16

SYNC2

ON/OFF

DCOK

SYNC2

EANI

CS_COMP

ON/OFF

LATSD

EAI

8

9

10 11 12 13 14

15 SHARE

EAO

FN9066.5

January 3, 2006

2

ISL6551

Functional Pin Description

PACKAGE PIN #

SOIC

1

QFN

26

PIN SYMBOL

VSS

FUNCTION

Reference ground. All control circuits are referenced to this pin.

Set the oscillator frequency, up to 1MHz.

2

27

CT

3

28

RD

Adjust the clock dead time from 50ns to 1000ns.

4

1

R_RESDLY

R_RA

Program the resonant delay from 50ns to 500ns.

5

2

Adjust the ramp for slope compensation (from 50mV to 250mV).

The pin receives the current information via a current sense transformer or a power resistor.

Set the over current limit with the bandgap reference as the trip threshold.

Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.

Program the leading edge blanking from 50ns to 300ns.

6

3

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

CSS

7

4

8

5

9

6

10

7

Set a low current sharing loop bandwidth with a capacitor.

11

8

Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.

Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

Inverting input of Error Amp. It receives the feedback voltage.

12

9

EANI

13

10

EAI

14

11

EAO

Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

This pin is the SHARE BUS connecting with other unit(s) for current share operation.

The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.

Power Good indication with a ±5% window.

15

12

SHARE

LATSD

DCOK

16

13

17

14

18

15

ON/OFF

SYNC2, SYNC1

This is an Enable pin that controls the states of all drive signals and the soft-start.

These are the gate control signals for the output synchronous rectifiers.

19, 20

21, 22

23, 24

25

16, 17

18, 19

20, 21

22

LOWER2, LOWER1 Both lower drivers are PWM-controlled on the trailing edge.

UPPER2, UPPER1 Both upper drivers are driven at a fixed 50% duty cycle.

PGND

VDDP2, VDDP1

VDD

Power Ground. High current return paths for both the upper and the lower drivers.

26, 27

28

23, 24

25

Power is delivered to both the upper and the lower drivers through these pins.

Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.

FN9066.5

3

January 3, 2006

ISL6551

Functional Block Diagram

BANDGAP

REFERENCE

SHUTDOWN

LATCH

UVLO

SOFT

SOFT-

8

7

BGREF

PKILIM

START

SSHHUUTTDDOOWWNN

VDDP1

27

24

UPPER1

DRIVER

UPPER1

9

4

R_LEB

RESODLY

R_RESDLY

UPPER2

DRIVER

UPPER2

VDDP2

23

26

LEB

6

5

ISENSE

R_RA

RAMP

ADJUST

2

3

CT

RD

CLOCK

GENERATOR

PWM

LOWER1

DRIVER

22 LOWER1

LOGIC

ERROR AMP

(See Fig. 4)

EAO

14

LOWER2

DRIVER

21 LOWER2

13

12

EAI

CURRENT

SHARE

DC OK

EANI

CIRCUITS REFERENCED TO VSS

CIRCUITS REFERENCED TO PGND

EXTERNAL SINGLE POINT CONNECTION REQUIRED

FN9066.5

January 3, 2006

4

ISL6551

Absolute Maximum Ratings

Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V

Enable Inputs (ON/OFF, LATSD). . . . . . . . . . . . . . . . . . . . . . . . VDD

Thermal Information

Thermal Resistance

QFN Package (Notes 1, 3). . . . . . . . . .

SOIC Package (Note 2) . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC Lead Tips Only)

θ

(°C/W)

30

55

θ

(°C/W)

JC

2.5

N/A

JA

Power Good Sink Current (I

ESD Rating

) . . . . . . . . . . . . . . . . . . . . . . 5mA

DCOK

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .250V

Recommended Operating Conditions

Ambient Temperature Range

ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C

ISL6551AB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C

Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V

Supply Voltage Range, VDDP1 & VDDP2. . . . . . . . . . . . . . . <13.2V

Maximum Operating Junction Temperature. . . . . . . . . . . . . . .125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379 for details.

2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications These specifications apply for VDD = VDDP = 12V and T_A= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

(ISL6551AB), Unless Otherwise Stated

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY (VDD, VDDP1, VDDP2)

Supply Voltage

VDD

IDD

ICC

10.8

5

12.0

13

13.2

18

V

Bias Current from VDD (ISL6551IB)

Bias Current from VDD (ISL6551AB)

Total Current from VDD and VDDP

UNDER VOLTAGE LOCKOUT (UVLO)

Start Threshold (ISL6551IB)

Start Threshold (ISL6551AB)

Stop Threshold (ISL6551IB)

Stop Threshold (ISL6551AB)

Hysteresis (ISL6551IB)

VDD = 12V (not including drivers current at VDDP)

VDD = VDDP = 12V, F = 1MHz, 1.6nF Load

mA

3

20

60

9.6

8.6

1

VDD

9.2

9.16

8.03

7.98

0.3

9.9

9.94

8.87

8.92

1.9

V

ON

VDD

OFF

HYS

Hysteresis (ISL6551AB)

0.27

1.93

CLOCK GENERATOR (CT, RD)

Frequency Range

F

VDD = 12V (Figure 2)

VDD = 12V (Figure 3)

100

50

1000

kHz

ns

Dead Time Pulse Width (Note 4)

BANDGAP REFERENCE (BGREF)

DT

Bandgap Reference Voltage

(ISL6551IB)

VREF

IREF

VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming

1.250

1.244

1.263

1.280

1.287

100

V

Bandgap Reference Voltage

(ISL6551AB)

Bandgap Reference Output Current

VDD = 12V, see Block/Pin Functional Descriptions

for details

µA

FN9066.5

5

January 3, 2006

ISL6551

Electrical Specifications These specifications apply for VDD = VDDP = 12V and T_A= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

(ISL6551AB), Unless Otherwise Stated (Continued)

PARAMETER

PWM DELAYS (Note 4)

LOW1,2 delay “Rising”

LOW1,2 delay “Falling”

SYNC1,2 delay “Falling”

SYNC1,2 delay “Rising”

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LOWR

LOWF

With respect to RESDLY rising

5

ns

Compare Delay @ Verror = Vramp

44

18

20

SYNCF

SYNCR

With respect to RESDLY falling and with 20pF load

With respect to CLK rising and with 20pF load

ERROR AMPLIFIER (EANI, EAI, EAO) (Note 4)

Unity Gain Bandwidth

UGBW

DCG

10

79

MHz

dB

DC Gain

Maximum Offset Error Voltage

Input Common Mode Range

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Maximum Output Source Current

Maximum Lower Saturation Voltage

RAMP ADJUST (R_RA) (Note 4)

Ramp Frequency

Vos

3.1

9

mV

V

Vcm

VDD = 12V

1mA load

0.4

2

CMMR

PSSR

ISRC

Vsatlow

82

95

dB

mA

mV

Sinking 0.27mA

125

F

100

1000

kHz

mV

%

Linear Voltage Ramp, Minimum

Linear Voltage Ramp, Maximum

Overall Variation

LVR

50

250

25

PEAK CURRENT LIMIT (PKILIM)

Peak Current Shutdown Threshold

IpkThr

IpkDel

BGREF = 0.1µF, 399kΩ pull-up

1.25

1.263

75

1.31

V

Peak Current Shutdown Delay

(Note 4)

ns

SOFT-START (CSS)

Charge Current

Iss

Idis

Vcss = 0.6V

8

1.6

2

12

5.2

8

µA

mA

V

Discharge Current

Cycle-by-Cycle Current Limit

(ISL6551IB)

Vclamp

Cycle-by-Cycle Current Limit

(ISL6551AB)

Vclamp

1.9

8.1

V

DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)

Maximum Capacitive Load (each)

CL

VDD = VDDP = 12V, F = 1MHz,

Thermal Dependence

1600

pF

Turn On Rise Time (ISL6551IB)

Turn On Rise Time (ISL6551AB)

Turn Off Fall Time (ISL6551IB)

Turn Off Fall Time (ISL6551AB)

Shutdown Delay (Note 4)

Rising Edge Delay (Note 4)

Falling Edge Delay (Note 4)

Vsat_sourcing

Tr

Tf

1.0nF Capacitive load

8.9

9.2

6.4

16

17

10

12

ns

V

T

14.5

16.4

13.7

SD

RD

T

FD

Vsat_high Sourcing 20mA

Sourcing 200mA

1.00

1.35

V

FN9066.5

6

January 3, 2006

ISL6551

Electrical Specifications These specifications apply for VDD = VDDP = 12V and T_A= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

(ISL6551AB), Unless Otherwise Stated (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

0.035

0.31

0.04

0.5

UNITS

Vsat_sinking (ISL6551IB)

Vsat_low Sinking 20mA

Sinking 200mA

V

Vsat_sinking (ISL6551AB)

Vsat_low Sinking 20mA

Sinking 200mA

SYNCHRONOUS SIGNALS (SYNC1, SYNC2)

Maximum capacitive load (each)

VDD = 12, F = 1MHz

20

50

pF

PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4)

Resonant Delay Adjust Range

Resonant Delay

(Figure 7)

R_RESDLY = 10K

500

300

ns

t

55

RESDLY

R_RESDLY = 120K

(Figure 8)

488

Leading Edge Blanking Adjust

Range

50

Leading Edge Blanking

t

R_LEB = 20K

R_LEB = 140K

R_LEB = 12V

64

302

0

ns

LEB

LATCHING SHUTDOWN (LATSD)

Fault Threshold

VIN

3

2

V

Fault_NOT Threshold

Time to Set latch (Note 4)

ON/OFF (ONOFF)

VINN

TSET

1.9

0.8

415

ns

Turn-off Threshold

OFF

ON

V

Turn-on Threshold

CURRENT SHARE (SHARE, CS_COMP) (Note 4)

Voltage Offset Between Error Amp

Voltage of Master and Slave

Vcs_offset SHARE = 30K

30

mV

µA

Maximum Source Current To

External Reference

Ics_source SHARE = 30K

190

Maximum Correctable Deviation In

Reference Voltage Between Master

and Slave

SHARE = 30K, Rsource = 1K,

OUTPUT REFERENCE = 1 to 5V,

(See Figure 10)

mV

Share/Adjust Loop Bandwidth

DC OK (DCOK)

CS BW

CS_COMP = 0.1µF

500

Hz

Sink Current

I

5

0.4

5

mA

V

DCOK

Saturation Voltage

V

I

= 5mA

SATDCOK DCOK

Vref_in

Input Reference

1

V

Threshold (relative to Vref_in)

Recovery (relative to Vref_in)

Threshold (relative to Vref_in)

Recovery (relative to Vref_in)

Transient Rejection (Note 4)

OV

(Figure 11)

5

3

%

µs

UV

(Figure 11)

-5

UV

-3

TRej

100mV transient on Vout (system implicit rejection

and feedback network dependence (Figure 12)

250

NOTE:

4. Guaranteed by design. Not 100% tested in production.

FN9066.5

7

January 3, 2006

ISL6551

Drive Signals Timing Diagrams

CLOCK

UPPER1

UPPER2

SYNC1

SYNC2

LOWER1

EAO

I

LOWER1

LOWER2

EAO

I

LOWER2

RAMP ADJUST

OUTPUT TO

PWM

LOGIC

T2

T3

T4

T5

T1

NOTES:

T1 = Leading edge blanking

T2 = T4 = Resonant delay

T3 = T5 = dead time

In the above figure, the values for T1 through T5 are exaggerated for demonstration purposes.

Timing Diagram Descriptions

The two upper drivers (UPPER1 and UPPER2) are driven at

a fixed 50% duty cycle and the two lower drivers (LOWER1

and LOWER2) are PWM-controlled on the trailing edge,

while the leading edge employs resonant delay (T2 and T4).

In current mode control, the sensed switch (FET) current

if filtering of the current feedback was incorporated. The dead

time (T3 and T5) is the delay to turn on the upper FET

(UPPER1/UPPER2) after its corresponding lower FET

(LOWER1/LOWER2) is turned off when the bridge is

operating at maximum duty cycle in normal conditions, or is

responding to load transients or input line dipping conditions.

Therefore, the upper and lower FETs that are located at the

same side of the bridge can never be turned on together, which

eliminates shoot-through currents. SYNC1 and SYNC2 are the

gate control signals for the output synchronous rectifiers. They

are biased by VDD and are capable of driving capacitive loads

up to 20pF at 1MHz clock frequency (500kHz switching

frequency). External drivers with high current capabilities are

required to drive the synchronous rectifiers, cascading with

both synchronous signals (SYNC1 and SYNC2).

(I

and I

) is processed in the Ramp Adjust

LOWER1

LOWER2

and Leading Edge Blanking (LEB) circuits and then compared

to a control signal (EAO). Spikes, due to parasitic elements in

the bridge circuit, would falsely trigger the comparator

generating the PWM signal. To prevent false triggering, the

leading edge of the sensed current signal is blanked out by

T1, which can be programmed at the R_LEB pin with a

resistor. Internal switches gate the analog input to the PWM

comparator, implementing the blanking function that

eliminates response degrading delays which would be caused

FN9066.5

8

January 3, 2006

ISL6551

Shutdown Timing Diagrams

LATCH CANNOT BE RESET BY ON/OFF

C

LATSD

D

ON/OFF

VDD

A

E

F

VDD

ON

VDD

OFF

LATCH RESET BY

REMOVING VDD

> BGREF

PKILIM

B

ILIM_OUT

PKILIM < BGREF

SOFT

START

DRIVER

ENABLE

FAULT

SOFT-START

SHUTDOWN

FAULT

OFF

UNDER VOLTAGE

LOCKOUT

OVER

CURRENT

LATCHED

OFF/ON

LATCH

RESET

Shutdown Timing Descriptions

A (ON/OFF) - When the ON/OFF is pulled low, the soft-start

capacitor is discharged and all the drivers are disabled.

When the ON/OFF is released without a fault condition, a

soft-start is initiated.

E (LATCH RESET) - The latch is reset by removing the

VDD. The soft-start capacitor starts to be charged after VDD

increases above the turn-on threshold VDD

.

ON

F (VDD UVLO) - The IC is turned off when the VDD is below

the turn-off threshold VDD . Hysteresis VDD is

B (OVERCURRENT) - If the output of the converter is over

loaded, i.e., the PKILIM is above the bandgap reference

voltage (BGREF), the soft-start capacitor is discharged very

quickly and all the drivers are turned off. Thereafter, the soft-

start capacitor is charged slowly, and discharged quickly if

the output is overloaded again. The soft-start will remain in

hiccup mode as long as the overload conditions persist.

Once the overload is removed, the soft-start capacitor is

charged up and the converter is then back to normal

operation.

OFF

HYS

incorporated in the undervoltage lockout (UVLO) circuit.

C (LATCHING SHUTDOWN) - The IC is latched off

completely as the LATSD pin is pulled high, and the soft-start

capacitor is reset.

D (ON/OFF) - The latch cannot be reset by the ON/OFF.

FN9066.5

January 3, 2006

9

ISL6551

Block/Pin Functional Descriptions

Detailed descriptions of each individual block in the functional

block diagram on page 3 are included in this section.

Application information and design considerations for each pin

and/or each block are also included.

• Undervoltage Lockout (UVLO)

- UVLO establishes an orderly start-up and verifies that VDD

is above the turn-on threshold voltage (VDD ). All the

ON

drivers are held low during the lockout. UVLO incorporates

hysteresis VDD

to prevent multiple startup/shutdowns

HYS

• IC Bias Power (VDD, VDDP1, VDDP2)

- The IC is powered from a 12V ± 10% supply.

while powering up.

- UVLO limits are not applicable to VDDP1 and VDDP2.

• Bandgap Reference (BGREF)

- The reference voltage VREF is generated by a precision

bandgap circuit.

- This pin must be pulled up to VDD with a resistance of

approximately 399kΩ for proper operation. For additional

reference loads (no more than 1mA), this pull-up resistor

should be scaled accordingly.

- This pin must also be decoupled with an 0.1µF low ESR

ceramic capacitor.

- VDD supplies power to both the digital and analog circuits

and should be bypassed directly to the VSS pin with an

0.1µF low ESR ceramic capacitor.

- VDDP1 and VDDP2 are the bias supplies for the upper

drivers and the lower drivers, respectively. They should be

decoupled with ceramic capacitors to the PGND pin.

- Heavy copper should be attached to these pins for a better

heat spreading.

• IC GNDs (VSS, PGND)

- VSS is the reference ground, the return of VDD, of all

control circuits and must be kept away from nodes with

switching noises. It should be connected to the PGND in

only one location as close to the IC as practical. For a

secondary side control system, it should be connected to

the net after the output capacitors, i.e., the output return

pinout(s). For a primary side control system, it should be

connected to the net before the input capacitors, i.e., the

input return pinout(s).

- PGND is the power return, the high-current return path of

both VDDP1 and VDDP2. It should be connected to the

SOURCE pins of two lower power switches or the

RETURNs of external drivers as close as possible with

heavy copper traces.

• Clock Generator (CT, RD)

- This free-running oscillator is set by two external

components as shown in Figure 1. A capacitor at CT is

charged and discharged with two equal constant current

sources and fed into a window comparator to set the clock

frequency. A resistor at RD sets the clock dead time. RD

and CT should be tied to the VSS pin on their other ends

as close as possible. The corresponding CT for a particular

frequency can be selected from Figure 2.

- The switching frequency (Fsw) of the power train is half of

the clock frequency (Fclock), as shown in Equation 1.

Fclock

(EQ. 1)

Fsw = -------------------

2

- Copper planes should be attached to both pins.

RD

SET CLOCK

DEAD TIME (DT)

RD

-

VDD

I_CT

OUT

CLK

VMAX

VMIN

-

+

CT

Q

S

R

-

+

Q

DT

CLK

FIGURE 1. SIMPLIFIED CLOCK GENERATOR CIRCUIT

FN9066.5

10

January 3, 2006

ISL6551

2

3,000

2,500

2,000

0°C

60°C

120°C

1.6

1.2

0.8

0.4

0

1,500

1,000

20

40

60

80

100 120 140 160

0

500

0

RD (kΩ)

FIGURE 3. RD vs DEAD TIME (VDD = 12V)

10

100

1,000

10,000

CT (pF)

• Error Amplifier (EAI, EANI, EAO)

RECOMMENDED RANGE

- This amplifier compares the feedback signal received at

the EAI pin to a reference signal set at the EANI pin and

provides an error signal (EAO) to the PWM Logic. The

feedback loop compensation can be programmed via

these pins.

- Both EANI and EAO are clamped by the voltage

(Vclamp) set at the CSS pin, as shown in Figure 4. Note

that the diodes in the functional block diagram represent

the clamp function of the CSS in a simplified way.

FIGURE 2. CT vs FREQUENCY

- Note that the capacitance of a scope probe (~12pF for

single ended) would induce a smaller frequency at the

CT pin. It can be easily seen at a higher frequency. An

accurate operating frequency can be measured at the

outputs of the bridge/synchronous drivers.

- The dead time is the delay to turn on the upper FET

(UPPER1/UPPER2) after its corresponding lower FET

(LOWER1/LOWER2) is turned off when the bridge is

operating at maximum duty cycle in normal conditions,

or is responding to load transients or input line dipping

conditions. This helps to prevent shoot through between

the upper FET and the lower FET that are located at the

same side of the bridge. The dead time can be

estimated using Equation 2:

• Soft-Start (CSS)

- The voltage on an external capacitor charged by an

internal current source I is fed into a control pin on

SS

the error amplifier. This causes the Error Amplifier to: 1)

limit the EAO to the soft-start voltage level; and 2) over-

ride the reference signal at the EANI with the soft-start

voltage, when the EANI voltage is higher than the soft-

start voltage. Thus, both the output voltage and current

of the power supply can be controlled by the soft-start.

M × RD

kΩ

(ns)

(EQ. 2)

DT = -------------------

- The clamping voltage determines the cycle-by-cycle

peak current limiting of the power supply. It should be

set above the EANI and EAO voltages and can be

programmed by an external resistor as shown in

Figure 4 using Equation 3.

where M=11.4(VDD=12V), 11.1(VDD=14V), and

12(VDD=10V), and RD is in kΩ. This relationship is

shown in Figure 3.

(EQ. 3)

(V)

Vclamp = Rcss • Iss

(See Fig. 9)

SSL

400mV

VDD

+

-

(TO

BLANKING

CIRCUIT)

EAI

(–)

CSS

Iss

EANI

(+)

R

CSS

SHUTDOWN

ERROR AMP

EAO

FIGURE 4. SIMPLIFIED CLAMP/SOFT-START

FN9066.5

11

January 3, 2006

ISL6551

- Per Equation 3, the clamping voltage is a function of the

in a short-circuit condition. The limit can be set with a

resistor divider from the ISENSE pin. The resistor divider

relationship is defined in Equation 7.

charge current Iss. For a more predictable clamping

voltage, the CSS pin can be connected to a reference-

based clamp circuit as shown in Figure 5. To make the

Vclamp less dependent on the soft-start current (Iss),

the currents flowing through R1 and R2 should be

scaled much greater than Iss. The relationship of this

circuit can be found in Equation 4.

- In general, the trip point is a little smaller than the BGREF

due to the noise and/or ripple at the BGREF.

ISENSE

R

UP

PKILIM

V

REF

R

DOWN

R1

CSS

FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT

R2

Rdown

-------------------------------------- = -----------------------------------------

Rdown + Rup ISENSE(max)

BGREF

(EQ. 7)

FIGURE 5. REFERENCE-BASED CLAMP CIRCUIT

• Latching Shutdown (LATSD)

- A high TTL level on LATSD latches the IC off. The IC goes

into a low power mode and is reset only after the power at

the VDD pin is removed completely. The ON/OFF cannot

reset the latch.

R1 × R2

R1 + R2

R2

R1 + R2

----------------------

+ Vref •

Vclamp ≈ Iss •

(EQ. 4)

- This pin can be used to latch the power supply off on

- The soft-start rise time (T ) can be calculated with

ss

output overvoltage or other undesired conditions.

Equation 5. The rise time (T ) of the output voltage is

rise

approximated with Equation 6.

• ON/OFF (ON/OFF)

- A high standard TTL input (safe also for VDD level) signals

the controller to turn on. A low TTL input turns off the

controller and terminates all drive signals including the

SYNC outputs. The soft-start is reset.

- This pin is a non-latching input and can accept an enable

command when monitoring the input voltage and the

thermal condition of a converter.

Vclamp × Css

(s)

(EQ. 5)

(EQ. 6)

T

= ---------------------------------------

Iss

ss

EANI × Css

(s)

= --------------------------------

rise

Iss

• Resonant Delay (R_RESDLY)

• Drivers (Upper1, Upper2, Lower1, Lower2)

- A resistor tied between R_RESDLY and VSS determines

the delay that is required to turn on a lower FET after its

corresponding upper FET is turned off. This is the resonant

delay, which can be estimated with Equation 8.

- The two upper drivers are driven at a fixed 50% duty

cycle and the two lower drivers are PWM-controlled on

the trailing edge while the leading edge employs resonant

delay. They are biased by VDDP1 and VDDP2,

respectively.

(EQ. 8)

t

= 4.01 x R_RESDLY/kΩ + 13 (ns)

RESDLY

- Each driver is capable of driving capacitive loads up to CL

at 1MHz clock frequency and higher loads at lower

frequencies on a layout with high effective thermal

conductivity.

- Figure 7 illustrates the relationship of the value of the

resistor (R_RESDLY) and the resonant delay (t

).

RESDLY

The percentages in the figure are the tolerances at the two

end points of the curve.

- The UVLO holds all the drivers low until the VDD has

reached the turn-on threshold VDD

.

ON

- The upper drivers require assistance of external level-

shifting circuits such as Intersil’s HIP2100 or pulse

transformers to drive the upper power switches of a bridge

converter.

• Peak Current Limit (PKILIM)

- When the voltage at PKILIM exceeds the BGREF voltage,

the gate pulses are terminated and held low until the next

clock cycle. The peak current limit circuit has a high-speed

loop with propagation delay IpkDel. Peak current

shutdown initiates a soft-start sequence.

- The peak current shutdown threshold is usually set slightly

higher than the normal cycle-by-cycle PWM peak current

limit (Vclamp) and therefore will normally only be activated

FN9066.5

12

January 3, 2006

ISL6551

incorporated. The current ramp is blanked out during the

resonant delay period because no switching occurs in the

lower FETs. The leading edge blanking function will not be

activated until the soft-start (CSS) reaches over 400mV, as

illustrated in Figures 4 and 9. The leading edge blanking

(LEB) function can be disabled by tying the R_LEB pin to

VDD, i.e., LEB=1. Never leave the pin floating.

500

450

+18%

-24%

400

350

300

250

- The blanking time can be estimated with Equation 9,

whose relationship can be seen in Figure 8. The

percentages in the figure are the tolerances at the two

endpoints of the curve.

200

150

100

50

+37%

+4%

t

= 2 x R_LEB / kΩ + 15 (ns)

(EQ. 9)

LEB

0

20

40

60

80

100

120

R_RESDLY (kΩ)

300

250

200

FIGURE 7. R_RESDLY vs RESDLY

+20%

-18%

• Leading Edge Blanking (R_LEB)

- In current mode control, the sensed switch (FET) current is

processed in the Ramp Adjust and LEB circuits and then

compared to a control signal (EAO voltage). Spikes, due to

parasitic elements in the bridge circuit, would falsely trigger

the comparator generating the PWM signal. To prevent

false triggering, the leading edge of the sensed current

signal is blanked out by a period that can be programmed

with the R_LEB resistor. Internal switches gate the analog

input to the PWM comparator, implementing the blanking

function that eliminates response degrading delays which

would be caused if filtering of the current feedback was

150

100

+51%

-11%

50

0

20

40

60

80

100

120

140

R_LEB (kΩ)

FIGURE 8. R_LEB vs t

LEB

VDD

ADJ_RAMP

0.1µ

ADJ_RAMP

399K

200mV

0

ISENSE

RAMP_OUT

(TO PWM

BGREF

COMPARATOR)

R_RA

RAMP_OUT

200mV

R_RA

BLANK

ADD RAMP

+

-

ISENSE

200mV

RESDLY

LEB

X

SSL

RAMP_OUT

BLANK

0

X

1

X

0

BLANK

RESDLY

SET

BLANKING

TIME

R_LEB

LEB

1

X

1

NO BLANK

SSL

(See Fig. 4)

X

R_LEB

FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS

FN9066.5

January 3, 2006

13

ISL6551

• Ramp Adjust (R_RA, ISENSE)

synchronous rectifiers. When using these drive

schemes, the user should understand the issues that

might occur in his/her applications, especially the

impacts on current share operation and light load

operation. Refer to application note AN1002 for more

details.

- External high current drivers controlled by the

synchronous signals are required to drive the

synchronous rectifiers. A pulse transformer is required

to pass the drive signals to the secondary side if the IC

is used in a primary control system.

- The ramp adjust block adds an offset component

(200mV) and a slope adjust component to the ISENSE

signal before processing it at the PWM Logic block, as

shown in Figure 9. This ensures that the ramp voltage is

always higher than the OAGS (ground sensing opamp)

minimum voltage to achieve a “zero” state.

- It is critical that the input signal to ISENSE decays to

zero prior to or during the clock dead time. The level-

shifting and capacitive summing circuits in the RAMP

ADJUST block are reset during the dead time. Any input

signal transitions that occur after the rising edge of CLK

and prior to the rising edge of RESDLY can cause

severe errors in the signal reaching the PWM

comparator.

- Typical ramp values are hundreds of mV over the period

on a 3V full scale current. Too much ramp makes the

controller look like a voltage mode PWM, and too little

ramp leads to noise issues (jitter). The amount of ramp

(Vramp), as shown in Figure 9, is programmed with the

R_RA resistor and can be calculated with Equation 10.

• Share Support (SHARE, CS_COMP)

- The unit with the highest reference is the master. Other

units, as slaves, adjust their references via a source

resistor to match the master reference sharing the load

current. The source resistor is typically 1kΩ connecting

the EANI pin and the OUTPUT REFERENCE (external

reference or BGREF), as shown in Figure 10. The share

bus represents a 30kΩ resistive load per unit, up to 10

units.

- The output (ADJ) of “Operational Transconductance

Amplifier (OTA)” can only pull high and it is floating while

in master mode. This ensures that no current is sourced

to the OUTPUT REFERENCE when the IC is working

by itself.

- The slave units attempt to drive their error amplifier

voltage to be within a pre-determined offset (30mV

typical) of the master error voltage (the share bus). The

current-share error is nominally (30mV/EAO)*100%

assuming no other source of error. With a 2.5V full load

error amp voltage, the current-share error at full load

would be -1.2% (slaves relative to master).

- The bandwidth of the current sharing loop should be

much lower than that of the voltage loop to eliminate

noise pick-up and interactions between the voltage

regulation loop and the current loop. A 0.1µF capacitor

is recommended between CS_COMP and VSS pins to

achieve a low current sharing loop bandwidth (100Hz to

500Hz).

V

= BGREF x dt /(R_RA x 500E-12) (V)

ramp

(EQ. 10)

where dt = Duty Cycle / Fsw - t (s). Duty cycle is

discussed in detail in application note AN1002.

LEB

- The voltage representation of the current flowing

through the power train at ISENSE pin is normally

scaled such that the desired peak current is less than or

equal to Vclamp-200mV-Vramp, where the clamping

voltage is set at the CSS pin.

• SYNC Outputs (SYNC1, SYNC2)

- SYNC1 and SYNC2 are the gate control signals for the

output synchronous rectifiers. They are biased by VDD

and are capable of driving capacitive loads up to 20pF

at 1MHz clock frequency (500kHz switching frequency).

These outputs are turned off sooner than the turn-off at

UPPER1 and UPPER2 by the clock dead time, DT.

- Inverting both SYNC signals or both LOWER signals is

another possible way to control the drivers of the

CS_COMP

0.1µF

30mV

EAO

1K

ADJ

-

+

OUTPUT

REFERENCE

+

-

EANI

(+)

OTA

SHARE

30K

FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT

FN9066.5

14

January 3, 2006

ISL6551

• Power Good (DCOK)

18K

R

15N

C

- DCOK pin is an open drain output capable of sinking

5mA. It is low when the output voltage is within the

UVOV window. The static regulation limit is ±3%, while

the ±5% is the dynamic regulation limit. It indicates

power good when the EAI is within -3% to +5% on the

rising edge and within +3% to -5% on the falling edge, as

shown in Figure 11.

EAI

VOUT

-

1K

EAO

+

EANI

1.10V

EAI

VOUT

+5%

1.00V

0.90V

+3%

EANI

-3%

1.05V

1.00V

0.95V

EAI

-5%

FIGURE 12. OUTPUT TRANSIENT REJECTION

DCOK

FAULT

• Thermal Pad (in QFN only)

- In the QFN package, the pad underneath the center of

the IC is a “floating” thermal substrate. The PCB

“thermal land” design for this exposed die pad should

include thermal vias that drop down and connect to

one or more buried copper plane(s). This combination

of vias for vertical heat escape and buried planes for

heat spreading allows the QFN to achieve its full

thermal potential. This pad should be connected to a

low noise copper plane such as Vss.

FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW

- The DCOK comparator might not be triggered even

though the output voltage exceeds ± 5% limits at load

transients. This is because the feedback network of the

error amplifier filters out part of the transients and the EAI

only sees the remaining portion that is still within the limits,

as illustrated in Figure 12. The lower the “zero (1/RC)” of

the error amplifier, the larger the portion of the transient is

filtered out.

- Refer to TB389 for design guidelines.

FN9066.5

15

January 3, 2006

ISL6551

Additional Applications Information

Table 1 highlights parameter setting for the ISL6551.

Designers can use this table as a design checklist. For

detailed operation of the ISL6551, see Block/Pin Functional

Descriptions.

TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST

VDD = 12V at room temperature, unless otherwise stated.

PARAMETER

Frequency

PIN NAME

CT

FORMULA OR SETTING HIGHLIGHT

Set 50% Duty Cycle Pulses with a fixed frequency

DT = M x RD/kΩ, where M = 11.4

UNIT

kHz

ns

V

FIGURE #

1, 2

Dead Time

RD

3

Resonant Delay

R_RESDLY

R_RA

t

= 4.01 x R_RESDLY/kΩ + 13

7

RESDLY

Ramp Adjust

Vramp = BGREF/(R_RA x 500E-12) x dt

<Vclamp-200mV-Vramp

-

Current Sense

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

CSS

V

-

Peak Current

<BGREF and slightly higher than Vclamp

1.263V ±2%, 399kΩ pull-up, No more than 100µA load

V

6

Bandgap Reference

Leading Edge Blanking

Current Share Compensation

Soft-Start & Output Rise Time

Clamp Voltage (Vclamp)

Error Amplifier

V

-

t

= 2 x R_LEB/kΩ + 15, never leave it floating

ns

Hz

S

8, 9

LEB

0.1µ for a low current loop bandwidth (100 - 500Hz)

10

t

= Vclamp x Css/Iss, t

= EANI x CSS / Iss, Iss = 10µA ±20%

rise

4

ss

CSS

Vclamp = Iss x Rcss, or Reference-based clamp

EANI, EAO < Vclamp

V

4, 5

EANI, EAI, EAO

SHARE

LATSD

DCOK

V

-

Share Support

30K load & a resistor (1K, typ.) between EANI and OUTPUT REF.

Latch IC off at > 3V

-

Latching Shutdown

Power Good

V

-

±5% with hysteresis, Sink up to 5mA, transient rejection

Turn on/off at TTL level

V

11, 12

IC Enable

ON/OFF

VSS

V

-

Reference Ground

Power Ground

Connect to PGND in only one single point

Single point to VSS plane

-

PGND

-

Upper Drivers

UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz

LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz

-

Lower Drivers

-

Synchronous Drive Signals

Bias for Control Circuits

Biases for Bridge Drivers

SYNC1, SYNC2

VDD

Capacitive load up to 20pF at Fsw = 500kHz

12V ±10%, 0.1µF decoupling capacitor

Need decoupling capacitors

-

V

VDDP1, VDDP2

V

FN9066.5

January 3, 2006

16

ISL6551

Figure 13 shows the block diagram of a power supply

system employing the ISL6551 full bridge controller. The

ISL6551 not only is a full bridge PWM controller but also can

be used as a push-pull PWM controller. Users can design a

power supply by selecting appropriate blocks in the “System

Blocks Chart” based on the power system requirements.

Figures 13A, 14A, 15A, 16A, 17A, 18A, 19, 20A, 21, 22A,

and 24A have been used in the 200W telecom power supply

reference design, which can be found in the Application Note

AN1002. To meet the specifications of the power supply,

minor modifications of each block are required. To take full

advantage of the integrated features of the ISL6551,

“secondary side control” is recommended.

PRIMARY BIAS

BIASES

SECONDARY BIAS

V

OUT

IN

MAIN

TRANSFORMER

INPUT

FILTER

PRIMARY

FETs

OUTPUT

FILTER

RECTIFIERS

ISL6551

CONTROLLER

PRIMARY FET

DRIVERS

SECONDARY

DRIVERS

CURRENT

SENSE

SUPERVISOR

CIRCUITS

FEEDBACK

FIGURE 13. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551 CONTROLLER

System Blocks Chart

Input Filters

General - Input capacitors are required to absorb the

power switch (FET) pulsating currents.

V

V F

IN

EMI - For good EMI performance, the ripple current that is

reflected back to the input line can be reduced by an input

L-C filter, which filters the differential-mode noises and

operates at two times the switching frequency, i.e., the

clock frequency (Fclock). In some cases, an additional

common-mode choke might be required to filter the

common-mode noises.

C

IN

FIGURE 13A. GENERAL

L

IN

V

IN

V

F

IN

C

IN

FIGURE 13B. EMI

FN9066.5

17

January 3, 2006

ISL6551

Current Sense

Primary FETs

V

F

ISENSE

IN

or CURRENT_SEN_P

T_CURRENT

Q3_S

Q4_S

Q2

Q4

Q1

Q3

Q1_G

P–

Q2_G

P+

Q3_G

Q4_G

Q3_S

Q4_S

P2–

FIGURE 14A. TWO-LEG SENSE

FIGURE 15A. FULL BRIDGE

ISENSE

V

F

IN

P1–

CURRENT_SEN_P

Q4

FIGURE 14B. TOP SENSE

Q3

Q4_G

Q3_G

ISENSE

Q3_S & Q4_S

RSENSE

Q4_S

Q3_S

FIGURE 15B. PUSH-PULL

Full Bridge - Four MOSFETs are required for full bridge

converters. The drain to source voltage rating of the

MOSFETs is Vin.

FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)

Push-Pull - Only the two lower MOSFETs are required for

push-pull converters. The two upper drivers are not used.

Two-Leg Sense - Senses the current that flows through both

lower primary FETs. Operates at the switching frequency.

The V

of the MOSFETs is 2xVin.

DS

Top Sense - Senses the sum of the current that flows through

both upper primary FETs. Operates at the clock frequency.

Resistor Sense - This simple scheme is used in a primary side

control system. The sum of the current that flows through both

lower primary FETs is sensed with a low impedance power

resistor. The sources of Q3 and Q4 and ISENSE should be tied

at the same point as close as possible.

BIASES

Linear Regulator - In a primary side control system, a

linear regulator derived from the input line can be used for

the start-up purpose, and an extra winding coupled with the

main transformer can provide the controller power after the

start up.

DCM Flyback - Use a PWM controller to develop both

primary and secondary biases with discontinuous current

mode flyback topology.

FN9066.5

18

January 3, 2006

ISL6551

Feedback

Rectifiers

SYNCHRONOUS FETs

SCHOTTKY

S+

SYNP

SYNN

EAO

EAI

VOPOUT

S–

FIGURE 17A. CURRENT DOUBLER RECTIFIERS

FIGURE 16A. SECONDARY CONTROL

SYNCHRONOUS FETs

S+

SCHOTTKY

S+

VREF = 5V

IL207

VOPOUT

SYNP

SYNN

EAO

S–

EAI

TL431

FIGURE 17B. CONVENTIONAL RECTIFIERS

S+

FIGURE 16B. PRIMARY CONTROL

Secondary Control - In secondary side control systems,

only a few resistors and capacitors are required to complete

the feedback loop.

Primary Control - This feedback loop configuration for

primary side control systems requires an optocoupler for

isolation. The bandwidth is limited by the optocoupler.

S–

FIGURE 17C. SELF-DRIVEN RECTIFIERS

Current Doubler Rectifiers -

1. Synchronous FETs are used for low output voltage, high

output current and/or high efficiency applications.

2. Schottky diodes are used for lower current applications.

Pins S+ and S- are connected to the output filter and the

main transformer with current doubler configurations.

Conventional Rectifiers -

1. Synchronous FETs are used for low output voltage, high

output current and/or high efficiency applications.

2. Schottky diodes are used for lower current applications.

Pins S+ and S- are connected to the main transformer

with conventional configurations.

Self-Driven Rectifiers - For low output voltage applications,

both FETs can be driven by the voltage across the

secondary winding. This can work with all kinds of main

transformer configurations as shown in Figures 18A-D.

FN9066.5

19

January 3, 2006

ISL6551

Main Transformers

Supervisor Circuits

S +

S–

(1) INTEGRATED SOLUTION

• Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN

package requires less space than the SOIC package.

P+

P–

VCC

VOPP

UVDLY

OVUVSEN

PGOOD

START

PEN

FIGURE 18A. FULL BRIDGE AND CURRENT DOUBLER

1

2

20

19

18

17

16

15

14

13

12

11

VOPM

3

PGOOD

START

PEN

VOPOUT

VREF5

GND

P+

S +

4

VOPOUT

VREF5

5

V

F

OUT

VID0

6

P–

S–

BDAC

VID1

7

BDAC

FIGURE 18B. CONVENTIONAL FULL BRIDGE

OVUVTH

DACHI

DACLO

VID2

8

VID3

VID4

9

10

P1–

S +

S–

V

F

IN

FIGURE 19. ISL6550 SOIC

or CURRENT_SEN_P

P2–

• Over-temperature protection (discrete)

• Input UV lockout (discrete)

FIGURE 18C. PUSH-PULL AND CURRENT DOUBLER

(2) DISCRETE SOLUTION

• Differential Amplifier

P1–

S +

• VCC undervoltage lockout

• Programmable output OV and UV

• Programmable output

V

F

IN

V

F

OUT

or CURRENT_SEN_P

P2–

S–

FIGURE 18D. CONVENTIONAL PUSH-PULL

• Status indicators (PGOOD and START)

• Precision Reference

Full Bridge and Current Doubler - No center tap is

required. The secondary winding carries half of the load, i.e.,

only half of the load is reflected to the primary.

• Ove- temperature protection

• Input UV lockout

Conventional Full Bridge - Center tap is required on the

secondary side, and no center tap is required on the primary

side. The secondary winding carries all the load. i.e., all the

load is reflected to the primary.

The Integrated Solution is much simpler than a discrete

solution. Over-temperature protection and input under

voltage lockout can be added for better system protection

and performance.

Push-Pull and Current Doubler - Center tap is required on

the primary side, and no center tap is required on the

secondary side. The secondary winding carries half of the

load, i.e., only half of the load is reflected to the primary.

The Discrete Solution requires a significant number of

components to implement the features that the ISL6550 can

provide.

Conventional Push-Pull - Both primary and secondary

sides require center taps. The secondary winding carries all

the load, i.e., all the load is reflected to the primary.

FN9066.5

20

January 3, 2006

ISL6551

Output Filter

Secondary Drivers

L

OUT

S+

MIC4421BM

SYNC2

/LOWER1

VOUT

OUT

SYNC1

/LOWER2

IN OUT

GND

IN OUT SYNN

GND

SYNP

C

S–

FIGURE 20A. CURRENT DOUBLER FILTER

FIGURE 22A. INVERTING DRIVERS

L

OUT

MIC4422BM

V

F

OUT

C

OUT

F

CLOCK

IN OUT

GND

IN OUT

GND

SYNC2

SYNC1

SYNP

SYNN

FIGURE 20B. CONVENTIONAL FILTER

Current Doubler Filter - Two inductors are needed, but they

can be integrated and coupled into one core. Each inductor

carries half of the load operating at the switching frequency.

FIGURE 22B. NON-INVERTING DRIVERS

Conventional Filter - One inductor is needed. The inductor

carries all the load operating at two times the switching

frequency.

IN OUT

SYNP

T_SYN

GND

Controller

SYN1

VSS

CT

VDD

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDDP1

VDDP2

PGND

RD

3

SYN2

R_RESDLY

R_RA

SYNN

IN OUT

GND

4

UPPER1

UPPER2

LOWER1

LOWER2

SYNC1

SYNC2

ON / OFF

DCOK

5

F

SW

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

CSS

6

INPUT

UV & OV

7

ICL6551

SOIC

8

INVERTING

SYNC2/LOWER1

SYNC1/LOWER2

MIC4421BM

NON INVERTING

SYNC1

9

SYN1

SYN2

IC

10

11

12

13

14

OUTPUT

REFERENCE

(BDAC)

SYNC2

LED

MIC4422BM

EANI

EAI

LSTSD

SHARE

LSTSD

EAI

FIGURE 22C. PRIMARY CONTROL

EAO

SHARE

BUS

Inverting Drivers - Inverting the SYNC signals or the

LOWER signals with external high current drivers to drive

the synchronous FETs.

FIGURE 21. ISL6551 CONTROLLER

Non-inverting Drivers - Cascading SYNC signals with non-

inverting high current drivers to drive the synchronous FETs.

There is a dead time between SYNC1 and SYNC2. For a

higher efficiency, schottky diodes are normally in parallel

with the synchronous FETs to reduce the conduction losses

during the dead time in high output current applications.

ISL6551 Controller - It can be used as a full bridge or push-

pull PWM controller. The QFN package requires less space

than the SOIC package.

Primary Control - This requires a pulse transformer,

operating at the switching frequency, for isolation. There are

three options to drive the synchronous FETs, as described in

previous lines.

FN9066.5

21

January 3, 2006

ISL6551

Primary FET Drivers

(1) PUSH-PULL DRIVERS

HIP2100IB

Q3_G

HI

HO

Q3_S

Q4_G

HS

LO

LI

VSS

LOWER1

LOWER2

Q3_S

Q4_S

LOWER1

LOWER2

Q4_S

Q4_G

FIGURE 23B. PUSH-PULL HIGH CURRENT DRIVERS

FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS

HIP2100IB

LOWER1

LOWER2

Q3_G

Q3_S

HO

HS

HI

LI

VSS

Q4_G

LO

PGND

Q4_S

FIGURE 23C. PUSH-PULL PRIMARY CONTROL

Push-Pull Medium Current Drivers - Upper drivers are not

used. No external drivers are required. Secondary control.

Operate at the switching frequency.

Push-Pull High Current Drivers - Upper drivers are not

used. External high current drivers are required and less

power is dissipated in the ISL6551 controller. Secondary

control. Operate at the switching frequency.

Push-Pull Primary Control - Upper drivers are not used.

Both lower drivers can directly drive the power switches.

External drivers are required in high gate capacitance

applications.

FN9066.5

22

January 3, 2006

ISL6551

(2) FULL BRIDGE DRIVERS

HIP2100IB

Q1_G

P–

HI

LI

HO

HS

Q3_G

UPPER1

UPPER2

VSS LO

P–

P+

UPPER1

UPPER2

Q3_S

HIP2100IB

Q2_G

Q3_G

Q2_G

P+

HI

LI

HO

HS

Q4_G

VSS LO

LOWER1

LOWER2

Q4_S

Q3_S

Q4_S

LOWER1

LOWER2

Q4_G

FIGURE 24B. FULL BRIDGE MEDIUM CURRENT DRIVERS

FIGURE 24A. FULL BRIDGE HIGH CURRENT DRIVERS

HIP2100IB

Q1G

P–

UPPER1

LOWER1

HI

LI

HO

HS

Q3_G

Q3_S

VSS LO

PGND

HIP2100IB

Q2_G

P+

UPPER2

LOWER2

HI

LI

HO

HS

Q4_G

Q4_S

VSS LO

PGND

FIGURE 24C. FULL BRIDGE PRIMARY CONTROL

Full Bridge High Current Drivers - External high current

drivers are required and less power is dissipated in the

ISL6551 controller. Secondary control. Operate at the

switching frequency.

Full Bridge Medium Current Drivers - No external drivers

are required. Secondary control. Operate at the switching

frequency.

Full Bridge Primary Control - Lower drivers can directly

drive the power switches, while upper drivers require the

assistance of level-shifting circuits such as a pulse

transformer or Intersil’s HIP2100 half-bridge driver. External

high current drivers are not required in medium power

applications, but level-shifting circuits are still required for

upper drivers. Operate at the switching frequency.

FN9066.5

23

January 3, 2006

ISL6551

Small Outline Plastic Packages (SOIC)

M28.3 (JEDEC MS-013-AE ISSUE C)

N

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

0.25(0.010)

M

B M

H

AREA

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

0.30

0.51

0.32

18.10

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.0200

0.0125

-

1

2

3

L

9

SEATING PLANE

A

0.0091

0.6969

0.2914

-

0.7125 17.70

3

-A-

o

h x 45

D

0.2992

7.40

4

0.05 BSC

1.27 BSC

-

-C-

α

H

h

0.394

0.01

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

0.016

6

0.25(0.010) M

C

A M B S

N

α

28

7

o

0

8

0

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

FN9066.5

25

January 3, 2006

ISL6551

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L28.6x6

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)

MILLIMETERS

SYMBOL

MIN

0.80

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.90

-

9

0.20 REF

9

0.23

3.95

0.28

0.35

4.25

5, 8

D

6.00 BSC

-

D1

D2

E

5.75 BSC

9

4.10

7, 8

6.00 BSC

-

E1

E2

e

5.75 BSC

9

4.10

7, 8

0.65 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

28

7

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9066.5

26

January 3, 2006


型号：	ISL6551_06
厂家：	Intersil
描述：	ZVS Full Bridge PWM Controller ZVS全桥PWM控制器控制器
文件：	总26页 (文件大小：608K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6551_06 [INTERSIL]

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