ISL6506BCB-T [INTERSIL]
Multiple Linear Power Controller with ACPI Control Interface; 多元线性电源控制器与ACPI控制接口
| 型号： | ISL6506BCB-T |
| 厂家： | 
Intersil |
| 描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 文件： | 总8页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6506, ISL6506A, ISL6506B
®
Data Sheet
May 2, 2005
FN9141.2
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6506 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
Features
• Provides 2 ACPI-Controlled Voltages
- 5V USB/Keyboard/Mouse
DUAL
- 3.3V
/3.3V PCI/Auxiliary/LAN
DUAL
SB
• Excellent 3.3V
- ±2.0% over temperature
- 1A Capability on ISL6506 and ISL6506A
- 2A Capability on ISL6506B
Regulation in S3/S4/S5
DUAL
integrates the control of the 5V
and 3.3V
rails into
DUAL
DUAL
an 8 pin EPAD SOIC package. The ISL6506 operating mode
(active outputs or sleep outputs) is selectable through two
digital control pins, S3# and S5#.
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
A completely integrated linear regulator generates the
3.3V
voltage plane from the ATX supply’s 5V output
DUAL
SB
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506 uses an external N-channel pass
MOSFET to connect the outputs directly to the 3.3V input
supplied by an ATX power supply, for minimal losses.
• Pb-Free Available (RoHS Compliant)
Applications
•
ACPI-Compliant Power Regulation for Motherboards
The ISL6506 powers up the 5V
plane by switching in
DUAL
- ISL6506, ISL6506B: 5V
is shut down in S4/S5
DUAL
the ATX 5V output through an NMOS transistor in active
sleep states
states, or by switching in the ATX 5V through a PMOS (or
SB
- ISL6506A: 5V
DUAL
stays on in S4/S5 sleep states
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6506 and ISL6506B 5V
output is shut down. In the
DUAL
output stays on during S4/S5 sleep
Pinout
ISL6506A, the 5V
states.
DUAL
ISL6506 (SOIC)
TOP VIEW
Functionally, the ISL6506 and ISL6506B are identical. The
ISL6506B, however, features a 2A current limit on the
internal 3.3V LDO while the ISL6506 has a 1A current limit.
The ISL6506A has a 1A current limit on the internal 3.3V
LDO.
VCC
3V3AUX
S3#
1
2
3
4
8
7
6
5
N/C
5VDLSB
DLA
GND
S5#
GND
Ordering Information
TEMP.
PKG.
PART NUMBER
ISL6506CB
RANGE (°C)
PACKAGE
8 Ld EPSOIC
DWG. #
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
M8.15C
ISL6506CBZ (Note)
ISL6506ACB
8 Ld EPSOIC (Pb-free) M8.15C
8 Ld EPSOIC M8.15C
8 Ld EPSOIC (Pb-free) M8.15C
8 Ld EPSOIC M8.15C
ISL6506ACBZ (Note)
ISL6506BCB
ISL6506BCBZ (Note)
8 Ld EPSOIC (Pb-free) M8.15C
8 Ld EPSOIC (Pb-free) M8.15C
ISL6506BCBZA
(Note)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL6506, ISL6506A, ISL6506B
Block Diagram
S3#
S5#
DLA
VCC
12V POR
SENSE
10µA
10µA
3.5Ω
MONITOR
&
5VDLSB
CONTROL
TEMPERATURE
MONITOR
SOFT START
7.5µA
VCC
DIGITAL
(
)
SOFT START
EA1
+
-
UV DETECTOR
3V3AUX
GND
Typical Application
12VATX 3V3ATX
5VSBY
5VATX
5VSBY
1kΩ
Cg
ISL6506
(OPTIONAL)
5VDUAL
8
1
VCC
NC
2
3
4
7
6
5
3V3AUX
S3#
5VDLSB
DLA
Q2
Q3
SLP_S3
SLP_S5
S5#
GND
9
Q1
3V3DUAL
2
ISL6506, ISL6506A, ISL6506B
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical)
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
θ
(°C/W)
40
θ
(°C/W)
3.5
5VSB
JA
JC
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . TBD
EPSOIC Package (Notes 1, 2) . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
For Recommended soldering conditions see Tech Brief TB389.
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
5VSB
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Sx
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
V
V
V
= 5V, V
= 0V, V
= 5V (S0 State)
= 5V (S3 State)
-
-
-
3.60
4.60
4.60
-
-
-
mA
mA
mA
5VSB
S3#
S3#
S5#
S5#
S5#
= 0V (S5 State)
POWER-ON RESET
Rising 5VSB POR Threshold
Falling 5VSB POR Threshold
Rising 12V POR Threshold
-
-
-
4.5
V
V
V
3.60
8.9
3.95
10.8
1.00kΩ resistor between DLA and 12V Rail
9.8
3.3V
AUX
LINEAR REGULATOR
Regulation
V
= 5.0V, I
3V3SB
= 0A
-
-
-
-
-
-
2.0
-
%
V
V
A
A
5VSBY
3V3SB Nominal Voltage Level
3V3SB Undervoltage Threshold
3V3SB Over Current Trip
V
3.3
3V3SB
V
2.475
-
3V3SB_UV
I
ISL6506, ISL6506A, By Design
ISL6506B, By Design
-
-
1
3V3SB_TRIP
2
5V
SWITCH CONTROLLER
DUAL
5VDLSB Output Drive Current
TIMING INTERVAL
I
V
= 4V V = 5V
5VSB
20
-
-
35
-
mA
5VDLSB
5VDLSB
,
S0 to S3 Transition Delay
SOFT START
58
µs
Soft Start Interval
t
6.55
-
8.2
9.85
-
ms
SS
5VDLSB Soft Start Current Source
CONTROL I/O (S3#, S5#)
High Level Input Threshold
Low Level Input Threshold
S3#, S5# Internal Pull Down Current to GND
TEMPERATURE MONITOR
Shutdown-Level Threshold
-7.5
µA
-
0.8
-
-
-
2.2
V
V
-
-
10
µA
By Design
-
140
-
°C
3
ISL6506, ISL6506A, ISL6506B
controller/regulator supplying the computer system’s
3.3V power, a dual switch controller supplying the
Functional Pin Description
VCC (Pin 1)
DUAL
5V
DUAL
voltage, as well as all the control and monitoring
Provide a very well decoupled 5V bias supply for the IC to
functions necessary for complete ACPI implementation.
this pin by connecting it to the ATX 5V output. This pin
SB
Initialization
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
The ISL6506 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V input supply voltage. The ISL6506 also
SB
GND (Pin 5, Pad)
monitors the 12V rail to insure that the ATX rails are up
before entering into the S0 state even if both SLP_S3 and
SLP_S5 are both high.
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
S3# and S5# (Pins 3 and 4)
3.3V
and 5V
outputs. The internal circuitry does
DUAL
not allow the transition from an S4/S5 state to an S3 state.
DUAL
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3# and S5# to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
TABLE 1. 5V
OUTPUT TRUTH TABLE
DUAL
S5
1
S3
1
3.3AUX
5VDL
5V
COMMENTS
3.3V
3.3V
S0/S1/S2 States (Active)
S3
1
0
5V
3V3AUX (Pin 2)
0
1
Note
Maintains Previous State
S4/S5 (ISL6506 & 06B)
S4/S5 (ISL6506A)
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
0
0
3.3V
3.3V
0V
5V
0
0
NOTE: Combination Not Allowed.
Functional Timing Diagrams
DLA (Pin 6)
Figures 1 (ISL6506/B) and 2 (ISL6506A) are simplified timing
diagrams, detailing the power up/down sequences of all the
outputs in response to the status of the sleep-state pins (S3#,
S5#), as well as the status of the input ATX supply. Not shown
in these diagrams is the deglitching feature used to protect
against false sleep state tripping. Additionally, the ISL6506
features a 60µs delay in transitioning from S0 to S3 states. The
transition from the S0 state to S4/S5 state is immediate.
This pin is an open-drain output. A 1kΩ resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3V
and 5V outputs, respectively. This pin
AUX
DUAL
is also used to monitor the 12V rail during POR. If a resistor
other than 1kΩ is used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
5VSB
S3
ISL6506 and ISL6506B: In S3 sleep state, this transistor is
switched on, connecting the ATX 5V output to the 5V
SB
DUAL
regulator output.
S5
ISL6506A: In S3 and S4/S5 sleep state, this transistor is
3.3V, 5V, 12V
switched on, connecting the ATX 5V output to the 5V
SB
DUAL
DLA
3V3AUX
5VDLSB
5VDL
regulator output.
Description
Operation
The ISL6506 controls 2 output voltages, 3.3V
and
DUAL
5V
. It is designed for microprocessor computer
DUAL
FIGURE 1. 5V
AND 3.3V
TIMING DIAGRAM;
applications requiring 3.3V, 5V, 5V , and 12V bias input
DUAL
AUX
SB
ISL6506 and ISL6506B
from an ATX power supply. The IC is composed of one linear
4
ISL6506, ISL6506A, ISL6506B
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VSB
(1V/DIV)
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
3V3DL
5VDLSB
5VDL
0V
DLA
(10V/DIV)
FIGURE 2. 5V
AND 3.3V TIMING DIAGRAM;
AUX
DUAL
ISL6506A
T0 T1
T2
T3
T4 T5
TIME
T6
FIGURE 3. ISL6506 and ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time T0, 5V
SB
(bias) is applied to the circuit. At time T1, the 5V
5VDUAL
(1V/DIV)
5VSB
(1V/DIV)
SB
surpasses POR level. Time T2, one soft start interval after
T1, denotes the initiation of soft start. The 3.3V
rail is
brought up through the internal standby LDO through an
DUAL
3.3VDUAL
(2V/DIV)
internal digital soft start function. Figure 4 shows the 5V
DUAL
rail initiating a soft start at time T2 as well. The ISL6506A will
draw 7.5µA into the 5VDLSB for a duration of one soft start
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
period. This current will enhance the P-MOSFET (Q , refer
2
to Typical Application Schematic) in a controlled manner. At
time T3, the 3.3V
is in regulation and the 5VDLSB pin
DUAL
0V
is pulled down to ground. If the 5V
rail has not reached
DUAL
the level of the 5V rail by time T3, then the rail will
SB
experience a sudden step as the P-MOSFET gate is fully
enhanced. The soft start profile of the 5VDUAL may be
altered by placing a capacitor between the gate and drain of
the P-MOSFET. Adding this capacitor will increase the gate
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
T0 T1
T2
T3
T4 T5
TIME
T6
capacitance and slow down the start of the 5V
rail.
DUAL
At time T4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp up. With the ISL6506/B
FIGURE 4. SOFT START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506/A/B
(Figure 3), the 5V
rail will begin to ramp up from the
DUAL
5V
rail through the body diode of the N-MOSFET (Q ).
3
ATX
The ISL6506A will already have the 5V
regulation (Figure 4). At time T5, the 12V
rail in
Sleep to Wake State Transitions
DUAL
rail has
ATX
Figures 3 and 4, starting at time T4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506/B from the S4/S5 state to the S0
state. Figure 4 shows how the ISL6506/B will transition from
the S3 sleep state into S0 state. Figure 3 also shows how
the ISL6506A transitions from either S3 or S4/S5 in the S0
state. For all transitions, T4 depicts the system transition into
the S0 state. Here, the ATX supplies are enabled and begin
surpassed the 12V POR level. Time T6 is three soft start
cycles after the 12V POR level has been surpassed. At time
T6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q and Q ) that connect the
1
3
ATX rails to the 3.3V
and 5V
DUAL
rails. The 5VDLSB
DUAL
pin is forced to a high impedance state which will turn the
P-MOSFET (Q ) off. Finally, the internal LDO which regulates
2
to ramp up. At time T5, the 12V
POR threshold for the ISL6506/B and ISL6506A. Three soft
start periods after time T5, at time T6, three events occur
rail has exceeded the
ATX
the 3.3V
rail in sleep states in put in standby mode.
AUX
5
ISL6506, ISL6506A, ISL6506B
simultaneously. The DLA pin is forced to a high impedance
state which allows the 12V rail to enhance the two N-
electrolytics or tantalum capacitors) placement is not as
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
MOSFETs (Q and Q ) that connect the ATX rails to the
1
3
3.3V
and 5V
rails. The 5VDLSB pin is forced to a
DUAL
DUAL
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
high impedance state which will turn the P-MOSFET (Q )
off. Finally, the internal LDO which regulates the 3.3V
rail in sleep states is put in standby mode.
2
DUAL
Internal Linear Regulator Undervoltage Protection
12VATX
5VSB
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
CIN
Q3
VCC
5VDLSB
C
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft start interval later, the 3.3V linear
regulator is retried with a soft start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
5VSB
5VDUAL
+3.3VIN
Q2
C
5V
C
HF5V
ISL6506/A/B
Q4
DLA
Internal Linear Regulator Over Current Protection
3V3DUAL
3V3AUX
5VATX
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced which causes
the output voltage of the linear regulator to be reduced.
When the output voltage is reduced to the undervoltage trip
point, the undervoltage protection is initiated and the output
will shutdown.
C
C
3V
HF3V
KEY
GND
EPAD
ISLAND ON POWER PLANE LAYER
Layout Considerations
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
The typical application employing an ISL6506 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
FIGURE 5. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3V
island or the I/O circuitry. Ensure the
DUAL
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V ) carries a similar level
SB
of current - for best results, ensure it is connected to its
respective source through an adequately sized trace and is
properly decoupled. The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
6
ISL6506, ISL6506A, ISL6506B
Transistor Selection/Considerations
The ISL6506/A usually requires one P-Channel and two N-
Channel MOSFETs. All three of these MOSFETs are utilized
as ON/OFF switching elements.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0/S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
One important criteria for selection of transistors for all the
switching elements is package selection for efficient removal
of heat. The power dissipated in a switch element while on is
2
o
P
= I × r
LOSS
DS(on)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Also, during the transition between active and sleep states
on the 5V
output, there is a short interval of time during
DUAL
which none of the power pass elements are conducting.
During this time the output capacitors have to supply all the
output current. The output voltage drop during this brief
period of time can be easily approximated with the following
formula:
Q1, Q3
These N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the 3.3V
AUX
outputs while in active (S0, S1) state. The main
and 5V
DUAL
criteria for the selection of these transistors is output voltage
budgeting. The maximum r allowed at highest
t
t
∆V
= I
× ESR
+ --------------- , where
OUT
OUT
OUT
C
OUT
DS(ON)
junction temperature can be expressed with the following
equation:
∆V
= output voltage drop
OUT
ESR
= output capacitor bank ESR
V
– V
OUTmin
OUT
INmin
r
= -------------------------------------------------- , where
DS(ON)max
I
I
= output current during transition
OUTmax
OUT
C
= output capacitor bank capacitance
OUT
V
V
= minimum input voltage
INmin
t = active-to-sleep/sleep-to-active transition time (10µs typ.)
t
= minimum output voltage allowed
= maximum output current
OUTmin
OUTmax
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
I
Q2
This is a P-Channel MOSFET used to switch the 5V
output of the ATX supply into the 5V
sleep states. The selection criteria of this device, as with the
N-Channel MOSFETs, is proper voltage budgeting. The
maximum r
SB
output during
DUAL
Input Capacitors Selection
The input capacitors for an ISL6506/A application must have
a sufficiently low ESR so as not to allow the input voltage to
dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
, however, has to be achieved with only
DS(ON)
4.5V of gate-to-source voltage, so a true logic level
MOSFET needs to be selected.
specifications, certain imbalances between the ATX’s
outputs and the ISL6506/A’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, such phenomena could be responsible for the
5V voltage drooping excessively and affecting the output
regulation. The solution to such a potential problem is using
larger input capacitors with a lower total combined ESR.
SB
7
ISL6506, ISL6506A, ISL6506B
Small Outline Expos ed Pad Plas tic Packages (EPSOIC)
M8.15C
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.811
MAX
1.68
0.13
0.49
0.25
4.98
3.99
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
0.050 BSC
1.27 BSC
-
o
h x 45
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
-C-
5
α
µ
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
o
o
o
o
0
8
0
8
-
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
-
-
0.126
0.099
-
-
3.200
2.514
11
11
P1
Rev. 0 11/03
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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