ISL6506BCBZ-T7 [RENESAS]
POWER SUPPLY SUPPORT CKT;
| 型号： | ISL6506BCBZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | POWER SUPPLY SUPPORT CKT |
| 文件： | 总8页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6506, ISL6506A, ISL6506B
September 12, 2013
FN9141.6
Multiple Linear Power Controller with
ACPI Control Interface
Features
• Provides 2 ACPI-Controlled Voltages
The ISL6506 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
- 5V
DUAL
- 3.3V
DUAL
USB/Keyboard/Mouse
/3.3V PCI/Auxiliary/LAN
SB
• Excellent 3.3V
DUAL
- ±2.0% Over-Temperature
Regulation in S3/S4/S5
integrates the control of the 5V
and 3.3V
rails into
DUAL
DUAL
an 8 Ld EPAD SOIC package. The ISL6506 operating mode
(active outputs or sleep outputs) is selectable through two
digital control pins; S3 and S5.
- 1A Capability on ISL6506 and ISL6506A
- 2A Capability on ISL6506B
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
A completely integrated linear regulator generates the
3.3V
voltage plane from the ATX supply’s 5V output
DUAL
SB
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506 uses an external N-Channel pass
MOSFET to connect the outputs directly to the 3.3V input
supplied by an ATX power supply, for minimal losses.
• Pb-Free Available (RoHS Compliant)
Applications
•
ACPI-Compliant Power Regulation for Motherboards
The ISL6506 powers up the 5V
plane by switching in
DUAL
the ATX 5V output through an NMOS transistor in active
- ISL6506, ISL6506B: 5V
sleep states
is shut down in S4/S5
DUAL
states, or by switching in the ATX 5V through a PMOS (or
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
SB
- ISL6506A: 5V
DUAL
stays on in S4/S5 sleep states
ISL6506 and ISL6506B 5V
output is shut down. In the
DUAL
output stays on during S4/S5 sleep
Pinout
ISL6506A, the 5V
states.
DUAL
ISL6506 (8 LD EPSOIC)
TOP VIEW
Functionally, the ISL6506 and ISL6506B are identical. The
ISL6506B, however, features a 2A current limit on the
internal 3.3V LDO while the ISL6506 has a 1A current limit.
The ISL6506A has a 1A current limit on the internal 3.3V
LDO.
VCC
3V3AUX
S3
1
2
3
4
8
7
6
5
N/C
5VDLSB
DLA
GND
S5
GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6506CBZ
6506 CBZ
0 to +70
0 to +70
0 to +70
0 to +70
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
M8.15C
ISL6506ACBZ
ISL6506BCBZ
ISL6506BCBZA
NOTES:
6506 ACBZ
6506 BCBZ
6506 BCBZ
M8.15C
M8.15C
M8.15C
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6506, ISL6506A, ISL6506B. For more information on MSL please see
techbrief TB363.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004, 2005, 2007, 2008, 2010, 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6506, ISL6506A, ISL6506B
Block Diagram
S3
S5
DLA
VCC
12V POR
SENSE
10µA
10µA
3.5Ω
MONITOR
AND
CONTROL
5VDLSB
TEMPERATURE
MONITOR
SOFT-START
VCC
7.5µA
DIGITAL
SOFT-START
(
)
EA1
+
-
UV DETECTOR
3V3AUX
GND
Typical Application
12VATX 3V3ATX
5VSBY
5VATX
5VSBY
1kΩ
Cg
ISL6506
(OPTIONAL)
5VDUAL
8
1
VCC
NC
2
3
4
7
6
5
3V3AUX
S3
5VDLSB
DLA
Q2
Q3
SLP_S3
SLP_S5
S5
GND
9
Q1
3V3DUAL
FN9141.6
September 12, 2013
2
ISL6506, ISL6506A, ISL6506B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
40 3.5
5VSB
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
ESD Rating
EPSOIC Package (Notes 4, 5) . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000V
Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
5VSB
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +5.5V
Sx
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range, 0°C to
+70°C.
MIN
MAX
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNITS
I
V
V
V
= 5V, V = 5V (S0 State)
S5
-
-
-
3.60
4.60
4.60
-
-
-
mA
mA
mA
5VSB
S3
S3
S5
= 0V, V = 5V (S3 State)
S5
= 0V (S5 State)
POWER-ON RESET
Rising 5VSB POR Threshold
Falling 5VSB POR Threshold
Rising 12V POR Threshold
-
-
-
4.5
V
V
V
3.60
8.9
3.95
10.8
1.00kΩ resistor between DLA and 12V Rail
9.8
3.3V
AUX
LINEAR REGULATOR
Regulation
V
= 5.0V, I
3V3SB
= 0A
-
-
-
-
-
-
2.0
-
%
V
V
A
A
5VSBY
3V3SB Nominal Voltage Level
3V3SB Undervoltage Threshold
3V3SB Overcurrent Trip
V
3.3
3V3SB
V
2.475
-
3V3SB_UV
I
ISL6506, ISL6506A
ISL6506B
-
-
1
3V3SB_TRIP
2
5V
DUAL
SWITCH CONTROLLER
5VDLSB Output Drive Current
TIMING INTERVAL
I
V
= 4V V = 5V
5VSB
20
-
35
mA
µs
5VDLSB
5VDLSB
,
S0 to S3 Transition Delay
SOFT-START
-
58
-
Soft-start Interval
t
6.55
8.2
9.85
ms
µA
SS
5VDLSB Soft-start Current Source
CONTROL I/O (S3, S5)
High Level Input Threshold
Low Level Input Threshold
S3, S5 Internal Pull-down Current to GND
TEMPERATURE MONITOR
Shutdown-Level Threshold
NOTE:
-
-7.5
-
-
0.8
-
-
-
2.2
V
V
-
-
10
µA
-
140
-
°C
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN9141.6
September 12, 2013
3
ISL6506, ISL6506A, ISL6506B
controller/regulator supplying the computer system’s
3.3V power, a dual switch controller supplying the
Functional Pin Description
DUAL
voltage, as well as all the control and monitoring
VCC (Pin 1)
5V
DUAL
Provide a very well decoupled 5V bias supply for the IC to
functions necessary for complete ACPI implementation.
this pin by connecting it to the ATX 5V output. This pin
SB
Initialization
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
The ISL6506 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V input supply voltage. The ISL6506 also
SB
GND (Pin 5, Pad)
monitors the 12V rail to insure that the ATX rails are up
before entering into the S0 state even if both SLP_S3 and
SLP_S5 are both high.
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
S3 and S5 (Pins 3 and 4)
3.3V
and 5V
outputs. The internal circuitry does
DUAL
DUAL
not allow the transition from an S4/S5 state to an S3 state.
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull-down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3 and S5 to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
TABLE 1. 5V
OUTPUT TRUTH TABLE
DUAL
S5
1
S3
1
3.3AUX
5VDL
5V
COMMENTS
3.3V
3.3V
S0/S1/S2 States (Active)
S3
1
0
5V
3V3AUX (Pin 2)
0
1
Note
Maintains Previous State
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
0
0
3.3V
3.3V
0V
5V
S4/S5 (ISL6506 and
ISL6506B)
0
0
S4/S5 (ISL6506A)
NOTE: Combination Not Allowed.
Functional Timing Diagrams
DLA (Pin 6)
Figures 1 (ISL6506, ISL6506B) and 2 (ISL6506A) are simplified
timing diagrams, detailing the power-up/down sequences of all
the outputs in response to the status of the sleep-state pins (S3,
S5), as well as the status of the input ATX supply. Not shown in
these diagrams is the deglitching feature used to protect
against false sleep state tripping. Additionally, the ISL6506
features a 60µs delay in transitioning from S0 to S3 states. The
transition from the S0 state to S4/S5 state is immediate.
This pin is an open-drain output. A 1kΩ resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3V
and 5V outputs, respectively. This pin
AUX
DUAL
is also used to monitor the 12V rail during POR. If a resistor
other than 1kΩ is used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
5VSB
S3
ISL6506 and ISL6506B: In S3 sleep state, this transistor is
switched on, connecting the ATX 5V output to the 5V
SB
DUAL
regulator output.
S5
ISL6506A: In S3 and S4/S5 sleep state, this transistor is
3.3V, 5V, 12V
switched on, connecting the ATX 5V output to the 5V
SB
DUAL
regulator output.
DLA
3V3AUX
5VDLSB
5VDL
Description
Operation
The ISL6506 controls 2 output voltages, 3.3V
and
DUAL
. It is designed for microprocessor computer
5V
DUAL
applications requiring 3.3V, 5V, 5V , and 12V bias input
FIGURE 1. 5V
AND 3.3V
TIMING DIAGRAM;
SB
DUAL
AUX
ISL6506 AND ISL6506B
from an ATX power supply. The IC is composed of one linear
FN9141.6
September 12, 2013
4
ISL6506, ISL6506A, ISL6506B
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VSB
5VSB
S3
(1V/DIV)
S5
3.3V, 5V, 12V
DLA
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
3V3DL
5VDLSB
5VDL
0V
DLA
(10V/DIV)
FIGURE 2. 5V
AND 3.3V TIMING DIAGRAM;
AUX
t0 t1
t2
t3
t4 t5
TIME
t6
DUAL
ISL6506A
Soft-Start
FIGURE 3. ISL6506 AND ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5V (bias)
SB
is applied to the circuit. At time t1, the 5V surpasses POR
SB
level. Time t2, one soft-start interval after t1, denotes the
5VSB
5VDUAL
(1V/DIV)
(1V/DIV)
initiation of soft-start. The 3.3V
rail is brought up
DUAL
through the internal standby LDO through an internal digital
soft-start function. Figure 4 shows the 5V rail initiating a
3.3VDUAL
(2V/DIV)
DUAL
soft-start at time t2 as well. The ISL6506A will draw 7.5µA
into the 5VDLSB for a duration of one soft-start period. This
current will enhance the P-MOSFET (Q , refer to
2
?$paratext>? on page 2) in a controlled manner. At time t3,
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
the 3.3V
is in regulation and the 5VDLSB pin is pulled
DUAL
down to ground. If the 5V
rail has not reached the level
DUAL
0V
of the 5V rail by time t3, then the rail will experience a
SB
sudden step as the P-MOSFET gate is fully enhanced. The
5VDLSB
(5V/DIV)
soft-start profile of the 5V
may be altered by placing a
DUAL
DLA
capacitor between the gate and drain of the P-MOSFET.
Adding this capacitor will increase the gate capacitance and
(10V/DIV)
slow down the start of the 5V
DUAL
rail.
t0 t1
t2
t3
t4 t5
TIME
t6
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506,
FIGURE 4. SOFT-START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506, ISL6506A,
ISL650B
ISL6506B (Figure 3), the 5V
rail will begin to ramp-up
rail through the body diode of the N-MOSFET
DUAL
from the 5V
ATX
(Q ). The ISL6506A will already have the 5V
rail in
rail has
3
DUAL
Sleep to Wake State Transitions
regulation (Figure 4). At time t5, the 12V
ATX
Figures 3 and 4, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506, ISL6506B from the S4/S5 state to
the S0 state. Figure 4 shows how the ISL6506, ISL6506B
will transition from the S3 sleep state into S0 state. Figure 3
also shows how the ISL6506A transitions from either S3 or
S4/S5 in the S0 state. For all transitions, t4 depicts the
system transition into the S0 state. Here, the ATX supplies
surpassed the 12V POR level. Time t6 is three soft-start
cycles after the 12V POR level has been surpassed. At time
t6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q and Q ) that connect the
1
3
ATX rails to the 3.3V
and 5V
rails. The 5VDLSB pin
DUAL
DUAL
is actively pulled high, which will turn the P-MOSFET (Q ) off.
2
Finally, the internal LDO which regulates the 3.3V
sleep states is put in standby mode.
rail in
AUX
are enabled and begin to ramp up. At time t5, the 12V
rail
ATX
has exceeded the POR threshold for the ISL6506, ISL6506B
and ISL6506A. Three soft-start periods after time t5, at time
t6, three events occur simultaneously. The DLA pin is forced
FN9141.6
September 12, 2013
5
ISL6506, ISL6506A, ISL6506B
to a high impedance state, which allows the 12V rail to
12VATX
5VSB
enhance the two N-MOSFETs (Q and Q ) that connect the
1
3
ATX rails to the 3.3V
and 5V
rails. The 5VDLSB
DUAL
DUAL
CIN
pin is actively pulled high, which will turn the P-MOSFET
(Q ) off. Finally, the internal LDO which regulates the
2
Q3
VCC
3.3V
rail in sleep states is put in standby mode.
DUAL
5VDLSB
C
5VSB
5VDUAL
Internal Linear Regulator Undervoltage Protection
+3.3VIN
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
C
5V
C
HF5V
ISL6506,
ISL6506A,
ISL6506B
Q2
Q4
DLA
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
3V3DUAL
3V3AUX
5VATX
C
C
HF3V
3V
GND
EPAD
KEY
Internal Linear Regulator Overcurrent Protection
ISLAND ON POWER PLANE LAYER
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD ISLANDS
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
Layout Considerations
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
The typical application employing an ISL6506 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
from the 3.3V
island or the I/O circuitry. Ensure the
DUAL
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V ) carries a similar level
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
properly decoupled). The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
SB
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
Component Selection Guidelines
Output Capacitors Selection
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
electrolytics or tantalum capacitors) placement is not as
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0/S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
FN9141.6
September 12, 2013
6
ISL6506, ISL6506A, ISL6506B
current demands. Thus, it is recommended that the output
Transistor Selection/Considerations
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
The ISL6506, ISL6506A usually requires one P-Channel and
two N-Channel MOSFETs. All three of these MOSFETs are
utilized as ON/OFF switching elements.
Also, during the transition between active and sleep states
on the 5V
output, there is a short interval of time during
DUAL
One important criteria for selection of transistors for all the
switching elements is package selection for efficient removal
of heat. The power dissipated in a switch element while on is
shown in Equation 2:
which none of the power pass elements are conducting.
During this time the output capacitors have to supply all the
output current. The output voltage drop during this brief
period of time can be easily approximated using Equation 1:
2
P
= I × r
(EQ. 2)
t
⎛
⎞
⎟
⎠
LOSS
o
DS(ON)
t
(EQ. 1)
---------------
OUT
ΔV
= I
× ESR
+
⎜
OUT
OUT
OUT
C
⎝
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
where:
ΔV
= output voltage drop
= output capacitor bank ESR
OUT
ESR
OUT
Q1, Q3
I
= output current during transition
OUT
These N-Channel MOSFETs are used to switch the 3.3V and
5V inputs provided by the ATX supply into the 3.3V
5V
DUAL
and
outputs while in active (S0, S1) state. The main
C
= output capacitor bank capacitance
AUX
OUT
t = active-to-sleep/sleep-to-active transition time (10µs
t
typical)
criteria for the selection of these transistors is output voltage
budgeting. The maximum r allowed at highest junction
DS(ON)
temperature can be expressed using Equation 3:
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
V
– V
INmin
OUTmin
(EQ. 3)
--------------------------------------------------
r
=
DS(ON)max
I
OUTmax
where:
Input Capacitors Selection
V
V
= minimum input voltage
INmin
The input capacitors for an ISL6506, ISL6506A application
must have a sufficiently low ESR so as not to allow the input
voltage to dip excessively when energy is transferred to the
output capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6506, ISL6506A’s regulation levels could
have as a result a brisk transfer of energy from the input
capacitors to the supplied outputs. At the transition between
active and sleep states, such phenomena could be
= minimum output voltage allowed
= maximum output current
OUTmin
OUTmax
I
Q2
This is a P-Channel MOSFET used to switch the 5V
SB
output during
output of the ATX supply into the 5V
DUAL
sleep states. The selection criteria of this device, as with the
N-Channel MOSFETs, is proper voltage budgeting. The
responsible for the 5V voltage drooping excessively and
SB
maximum r
, however, has to be achieved with only
DS(ON)
affecting the output regulation. The solution to such a
potential problem is using larger input capacitors with a
lower total combined ESR.
4.5V of gate-to-source voltage, so a true logic level
MOSFET needs to be selected.
FN9141.6
September 12, 2013
7
ISL6506, ISL6506A, ISL6506B
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15C
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.811
MAX
1.68
0.13
0.49
0.25
4.98
3.99
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
0.050 BSC
1.27 BSC
-
h x 45°
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
-C-
5
α
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
0°
-
8°
0°
-
8°
-
11
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
0.126
0.099
3.200
2.514
P1
-
-
11
Rev. 1 6/05
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9141.6
September 12, 2013
8
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