ISL54200IRZ-T [INTERSIL]
USB 2.0 High/Full Speed Multiplexer; USB 2.0高速/全速多路复用器
| 型号： | ISL54200IRZ-T |
| 厂家： | 
Intersil |
| 描述： | USB 2.0 High/Full Speed Multiplexer |
| 文件： | 总16页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL54200
®
Data Sheet
January 24, 2007
FN6408.0
USB 2.0 High/Full Speed Multiplexer
Features
The Intersil ISL54200 dual 2:1 multiplexer IC is a single
supply part that can operate from a single 2.7V to 5.5V supply.
It contains two SPDT (Single Pole/Double Throw) switches
configured as a DPDT. The part was designed for switching
between USB High-Speed and USB Full-Speed sources in
portable battery powered products.
• High Speed (480Mbps) and Full Speed (12Mbps)
Signaling Capability per USB 2.0
• 1.8V Logic Compatible (2.7V to +3.6V supply)
• Enable Pin to Open all Switches
• -3dB Frequency
- HSx Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880MHz
- FSx Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550MHz
The 7Ω normally-closed (NC) FSx switches can swing rail to
rail and were specifically designed to pass USB full speed
data signals (12Mbps) that range from 0V to 3.6V. The 4.5Ω
normally-open (NO) HSx switches have high bandwidth and
low capacitance and were specifically designed to pass USB
high speed data signals (480Mbps) with minimal distortion.
• Cross-talk @ 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . -70dB
• OFF Isolation @ 100kHz . . . . . . . . . . . . . . . . . . . . . -98dB
• Single Supply Operation (V ) . . . . . . . . . . . . 2.7V to 5.5V
DD
The part can be used in Personal Media Players and other
portable battery powered devices that need to switch between
a high-speed transceiver and a full-speed transceiver while
connected to a single USB host (computer).
• Available in Ultra-thin µTQFN and TDFN Packages
• Pb-Free Plus Anneal (RoHS Compliant)
Applications
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The part has an enable
pin to open all switches. It can be used to facilitate proper bus
disconnect and connection when switching between the USB
sources.
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
• Digital Cameras and Camcorders
The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a
small 10 Ld 2.1mmx1.6mm µTQFN packages. It operates
over a temperature range of -40 to +85°C.
Application Block Diagram
3.3V
µCONTROLLER
V
DD
ISL54200
EN
IN
LOGIC CIRCUITRY
VBUS
D-
USB
4MΩ
HIGH-SPEED
TRANSCEIVER
HSD1
HSD2
COMD1
USB
D+
FSD1
FSD2
FULL-SPEED
TRANSCEIVER
COMD2
GND
GND
PORTABLE MEDIA DEVICE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL54200
Pinouts
ISL54200
(10 LD TDFN
TOP VIEW
ISL54200
(10 LD µTQFN)
TOP VIEW
10
4M
LOGIC
VDD
IN
EN
10
9
1
2
3
4
5
4M
CONTROL
HSD1
HSD2
VDD
IN
9
LOGIC
CONTROL
1
2
3
4
HSD1
8
8
COMD1
COMD2
GND
HSD2
FSD1
FSD2
COMD1
FSD1
FSD2
7
7
6
6
COMD2
5
NOTE:
1. ISL54200 Switches Shown for IN = Logic “0” and EN = Logic “1”.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE (°C)
-40 to +85
PACKAGE (Pb-Free)
PKG. DWG. #
ISL54200IRZ
200Z
200Z
FM
10 Ld 3x3 TDFN
L10.3x3A
ISL54200IRZ-T
-40 to +85
10 Ld 3x3 TDFN Tape and Reel
L10.3x3A
ISL54200IRUZ-T
-40 to +85
10 Ld 2.1x1.6mm μTQFN Tape and Reel
L10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
Pin Descriptions
ISL54200
FSD1, FSD2
ISL54200
EN
1
IN
0
HSD1, HSD2
OFF
PIN NO.
NAME
VDD
IN
FUNCTION
ON
OFF
OFF
1
2
Power Supply
1
1
ON
Select Logic Control Input
0
X
OFF
3
COMD1 USB Common Port
COMD2 USB Common Port
Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with a 2.7V to 3.6V
4
Supply. X = Don’t Care
5
GND
FSD1
FSD2
HSD1
HSD2
EN
Ground Connection
6
Full Speed USB Differential Port
Full Speed USB Differential Port
High Speed USB Differential Port
High Speed USB Differential Port
Bus Switch Enable
7
8
9
10
FN6408.0
January 24, 2007
2
ISL54200
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V
Input Voltages
Thermal Resistance (Typical, Note 3)
q
(°C/W)
JA
10 Ld 3x3 TDFN Package . . . . . . . . . . . . . . . . . . . .
10 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
55
140
FSD2, FSD1, HSD2, HSD1 (Note 2) . . . . . - 1V to ((V ) +0.3V)
DD
IN, EN (Note 2). . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V ) +0.3V)
DD
Output Voltages
COMD1, COMD2 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -1V to 5V
Continuous Current (HSD2, HSD1, FSD2, FSD1). . . . . . . . . ±40mA
Peak Current (HSD2, HSD1, FSD2, FSD1)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>7kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Operating Conditions
Temperature Range
ISL54200IRZ and ISL54200IRUZ . . . . . . . . . . . . . . -40°C to +85°C
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on FSD1, FSD2, HSD1, HSD2, COMD1, COMD2, EN, IN exceeding V
maximum current ratings.
or GND by specified amount are clamped. Limit current to
DD
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.3V, GND = 0V, V
= 1.4V, V
= 0.5V, V
= 1.4V,
ENH
DD
INH
INL
V
= 0.5V, (Notes 4, 6), Unless Otherwise Specified
ENL
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
NC Switches (FSD1, FSD2)
Analog Signal Range, V
ANALOG
V
= 3.3V, IN = 0V, EN = 3.3V
Full
+25
Full
+25
Full
0
-
-
7
V
V
Ω
Ω
Ω
Ω
DD
DD
ON Resistance, r
V
V
= 3.3V, IN = 0.5V, EN = 1.4V, I
= 40mA,
= 0V to 3.3V, (See Figure 4)
10
15
(ON)
DD
COMx
or V
FSD2
FSD1
-
-
r
Matching Between Channels,
V
V
= 3.3V, IN = 0.5V, EN = 1.4V, I
COMx
= 40mA,
-
0.1
-
0.35
0.4
(ON)
Δr
DD
or V
= Voltage at max r
over signal range
(ON)
FSD1
FSD2
(ON)
-
of 0V to 3.3V, (Note 8)
r
Flatness, r
FLAT(ON)
V
V
= 3.3V, IN = 0.5V, EN = 1.4V, I
COMx
= 40mA,
+25
Full
+25
Full
+25
Full
-
4
-
6
Ω
(ON)
DD
or V
= 0V to 3.3V, (Note 7)
FSD1
FSD2
-
8
Ω
OFF Leakage Current, I
V+ = 3.6V, IN = 3.6V, EN = 0V and 3.6V, V
3V, V
= 0.3V,
-20
-70
-20
-70
2
-
20
70
20
70
nA
nA
nA
nA
FSX(OFF)
FSX(ON)
COMx
= 3V, 0.3V
FSX
ON Leakage Current, I
V+ = 3.6V, IN = 0V, EN = 3.6V, V
COMx
V
= 0.3V, 3V,
2
-
= 0.3V, 3V
FSX
NO Switches (HSD1, HSD2)
Analog Signal Range, V
V
= 3.3V, IN = 3.3V, EN = 3.3V
= 3.3V, IN = 1.4V, EN = 1.4V, I
Full
+25
Full
+25
Full
+25
Full
0
-
-
-
-
-
-
-
20
-
V
DD
V
Ω
Ω
Ω
Ω
Ω
Ω
ANALOG
DD
ON Resistance, r
V
V
= 1mA,
30
35
6
(ON)
DD
COMx
or V
= 3.3V (See Figure 3)
HSD2
HSD1
ON Resistance, r
V
V
= 3.3V, IN = 1.4V, EN = 1.4V, I
= 40mA,
4.5
-
(ON)
DD
COMx
or V
= 0V to 400mV (See Figure 3)
HSD1
HSD2
8
r
Matching Between Channels,
V
V
= 3.3V, IN = 1.4V, EN = 1.4V, I
COMx
= 40mA,
, Voltage at max
0.01
-
0.1
0.5
(ON)
Δr
DD
or V
= Voltage at max r
(ON)
HSD2
HSD1
(ON)
r
over signal range of 0V to 400mV (Note 8)
(ON)
r
Flatness, r
FLAT(ON)
V
V
= 3.3V, IN = 1.4V, EN = 1.4V, I
= 40mA,
= 0V to 400mV, (Note 7)
HSD1
+25
Full
-
-
0.4
-
1
Ω
Ω
(ON)
DD
COMx
or V
HSD2
1.5
FN6408.0
January 24, 2007
3
ISL54200
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.3V, GND = 0V, V
= 1.4V, V
= 0.5V, V
= 1.4V,
ENH
DD
INH
INL
V
= 0.5V, (Notes 4, 6), Unless Otherwise Specified (Continued)
ENL
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
OFF Leakage Current, I
TEST CONDITIONS
TYP
V
V
= 3.6V, IN = 0V, EN = 0 and 3.6V, V
or
+25
Full
+25
Full
-20
-70
-20
-70
2
-
20
70
20
70
nA
nA
nA
nA
HSD2(OFF)
DD
COMD1
= 0.3V, 3V
or I
= 3V, 0.3V, V
or V
HSD1(OFF)
COMD2
HSD2 HSD1
ON Leakage Current, I
or
V
V
= 3.6V, IN = 3.6V, EN = 3.6V, V
or
= 0.3V, 3.0V
2
-
HSD2(ON)
DD
COMD1
I
= 0.3V, 3.0V, V or V
HSD2 HSD1
HSD1(ON)
COMD2
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V
V
V
V
= 3.3V, R = 45Ω, C = 10pF, (See Figure 1)
+25
+25
+25
+25
-
-
-
-
25
15
7
-
-
-
-
ns
ns
ns
ps
ON
Turn-OFF Time, t
DD
DD
DD
DD
L
L
= 3.3V, R = 45Ω, C = 10pF, (See Figure 1)
OFF
Break-Before-Make Time Delay, t
L
L
= 3.3V, R = 45Ω, C = 10pF, (See Figure 2)
D
L
L
Skew, t
= 3.3V, IN = 3.3V, EN = 3.3V, R = 45Ω, C = 10pF,
50
SKEW
(HSx Switch)
L
L
t
= t = 720ps at 480Mbps, (Duty Cycle = 50%)
R
F
(See Figure 7)
Total Jitter, t
(HSx Switch)
V
=3.3V, IN = 3.3V, EN = 3.3V, R = 45Ω, C = 10pF,
+25
+25
+25
-
-
-
210
250
0.15
-
-
-
ps
ps
ns
J
DD
t = t = 720ps at 480Mbps
R
L
L
F
Propagation Delay, t
(HSx Switch)
V
= 3.3V, IN = 3.3V, EN = 3.3V, R = 45Ω, C = 10pF,
L L
PD
DD
(See Figure 7)
Skew, t
V
= 3.3V, IN = 0V, EN = 3.3V, R = 39Ω, C = 50pF,
L L
SKEW
(FSx Switch)
DD
= t = 12ns at 12Mbps, (Duty Cycle = 50%)
t
R
F
(See Figure 7)
Rise/Fall Time Mismatch, t
(FSx Switch)
V
= 3.3V, IN = 0V, EN = 3.3V, R = 39Ω, C = 50pF,
+25
+25
+25
+25
-
-
-
-
10
1.6
0.9
-70
-
-
-
-
%
ns
ns
dB
M
DD
t = t = 12ns at 12Mbps, (Duty Cycle = 50%)
R
L
L
F
Total Jitter, t
V
= 3.3V, IN = 0V, EN = 3.3V, R = 39Ω, C = 50pF,
L L
J
DD
t = t = 12ns at 12Mbps
R
(FSx Switch)
F
Propagation Delay, t
(FSx Switch)
V
= 3.3V, IN = 0V, EN = 3.3V, R = 39Ω, C = 50pF,
L L
PD
DD
(See Figure 7
Crosstalk
V
= 3.3V, R = 45Ω, f = 1MHz
L
DD
(See Figure 6)
OFF Isolation
V
= 3.3V, R = 45Ω, f = 100kHz
+25
+25
+25
+25
-
-
-
-
-98
880
550
6
-
-
-
-
dB
MHz
MHz
pF
DD
L
FSx Switch -3dB Bandwidth
HSx Switch -3dB Bandwidth
Signal = -10dBm, 1.0VDC offset, R = 45Ω, C = 5pF
L
L
Signal = -10dBm, 0.2VDC offset, R = 45Ω, C = 5pF
L
L
HSx OFF Capacitance, C
FSx OFF Capacitance, C
COM ON Capacitance, C
COM ON Capacitance, C
f = 1MHz, V
V
= 3.3V, IN = 0V, EN = 3.3V, V
or
HSxOFF
DD
HSD1
= V
= 0V, (See Figure 5)
HSD2
COMx
f = 1MHz, V
V
= 3.3V, IN = 3.3V, EN = 3.3V, V
or
+25
+25
+25
-
-
-
9
-
-
-
pF
pF
pF
FSxOFF
DD
FSD1
= V
= 0V, (See Figure 5)
FSD2
COMx
f = 1MHz, V
V
= 3.3V, IN = 3.3V, EN = 3.3V, V
or
12
15
COMX(ON)
DD
HSD1
= V
= 0V, (See Figure 5)
HSD2
COMx
f = 1MHz, V
= 3.3V, IN = 0V, EN = 3.3V, V
or
COMX(ON)
DD
FSD1
V
= V
= 0V, (See Figure 5)
FSD2
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V
COMx
Full
+25
Full
2.7
-
20
-
5.5
60
80
V
DD
Positive Supply Current, I
V
= 3.6V, IN = 0V or 3.6V, EN = 0V or 3.6V
DD
-
-
nA
nA
DD
FN6408.0
January 24, 2007
4
ISL54200
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.3V, GND = 0V, V
= 1.4V, V
= 0.5V, V
= 1.4V,
ENH
DD
INH
INL
V
= 0.5V, (Notes 4, 6), Unless Otherwise Specified (Continued)
ENL
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
TEST CONDITIONS
TYP
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V , V
INL ENL
V
V
V
V
V
= 2.7V to 3.6V
Full
Full
Full
Full
Full
-
-
-
0.5
V
DD
DD
DD
DD
DD
Input Voltage High, V , V
= 2.7V to 3.6V
1.4
-
-
-
-
V
INH ENH
Input Current, I , I
INL ENL
= 3.6V, IN = 0V, EN = 0V
= 3.6V, IN = 3.6
-
-
-
10
10
1
nA
nA
μA
Input Current, I
Input Current, I
NOTES:
INH
= 3.6V, EN = 3.6
ENH
4. V
= Input voltage to perform proper function.
LOGIC
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parameters with limits are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range
8. r
r
matching between channels is calculated by subtracting the channel with the highest max r
value, between HSD2 and HSD1 or between FSD2 and FSD1.
value from the channel with lowest max
(ON)
(ON)
(ON)
Test Circuits and Waveforms
V
DD
VIN
t < 20ns
r
t < 20ns
f
H
LOGIC
INPUT
50%
VIN
L
EN
V
INPUT
V
t
OUT
OFF
HSx or FSx
SWITCH
INPUT
COMx
SWITCH
INPUT
V
INPUT
IN
V
OUT
90%
90%
R
45W
C
L
10pF
VIN
L
GND
SWITCH
OUTPUT
0V
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
---------------------------
V
= V
OUT
(INPUT)
R
+ r
(ON)
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FN6408.0
January 24, 2007
5
ISL54200
Test Circuits and Waveforms (Continued)
V
DD
C
VIN
H
EN
LOGIC
INPUT
FSD1 or FSD2
V
V
OUT
INPUT
COMx
VIN
L
HSD1 or HSD2
C
R
L
L
45Ω
10pF
IN
90%
SWITCH
OUTPUT
GND
VIN
V
OUT
0V
t
D
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
V
DD
V
DD
C
C
r
= V /I
COMx
(ON)
1
r
= V /40mA
1
(ON)
HSx
FSx
V
HSX
V
FSX
IN
1.4V
V
IN
0.5V
1
V
1
I
COMx
40mA
COMx
COMx
EN
GND
EN
GND
1.4V
1.4V
Repeat test for all switches.
FIGURE 4. FSx Switch r
Repeat test for all switches.
FIGURE 3. HSx Switch r
TEST CIRCUIT
TEST CIRCUIT
(ON)
(ON)
FN6408.0
January 24, 2007
6
ISL54200
Test Circuits and Waveforms (Continued)
V
DD
V
DD
C
C
EN
EN
SIGNAL
GENERATOR
45Ω
HSx or FSx
HSx
COMx
IN
IN
IMPEDANCE
ANALYZER
VIN OR
VIN
L
VIN
H
COMx
GND
FSx
COMx
ANALYZER
N.C.
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 5. CAPACITANCE TEST CIRCUIT
V
DD
C
t
ri
EN
90%
50%
VIN
VIN
10%
90%
DIN+
DIN-
t
skew_i
15.8Ω
143Ω
OUT+
D2
D1
COMD2
COMD1
DIN+
DIN-
50%
10%
45Ω
C
L
15.8Ω
143Ω
OUT-
t
fi
45Ω
C
t
L
ro
90%
10%
90%
GND
50%
OUT+
OUT-
t
skew_o
|tro-tri| Delay Due to Switch for Rising Input and Rising Output
Signals.
|tfo-tfi| Delay Due to Switch for Falling Input and Falling Output
Signals.
50%
10%
t
f0
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 7B. TEST CIRCUIT
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7. SKEW TEST
FN6408.0
January 24, 2007
7
ISL54200
Application Block Diagram
3.3V
µCONTROLLER
V
DD
ISL54200
EN
IN
LOGIC CIRCUITRY
VBUS
D-
USB
4MΩ
HIGH-SPEED
TRANSCEIVER
HSD1
HSD2
COMD1
USB
D+
FSD1
FSD2
FULL-SPEED
TRANSCEIVER
COMD2
GND
GND
PORTABLE MEDIA DEVICE
were specifically designed to pass USB full-speed (12Mbps)
differential signals and meet the USB 2.0 full-speed signal
quality specifications. See eye diagram Figure 8.
Detailed Description
The ISL54200 device is a dual single pole/double throw
(SPDT) analog switch that operates from a single DC power
supply in the range of 2.7V to 5.5V. It was designed to
function as dual 2-to-1 multiplexer to select between a USB
high-speed transceiver and a USB full-speed transceiver in
portable battery powered products. It is offered in a TDFN
package and a small µTQFN package for use in MP3
players, cameras, PDAs, cellphones, and other personal
media players. The device has an enable pin to open all
switches.
The FSx switches can also pass USB high speed signals
(480Mbps) but do not quite meet the USB 2.0 high speed
signal quality eye diagram compliance requirement.
The maximum signal range for the FSx switches is from
-1.5V to V . The signal voltage should not be allowed to
DD
exceed the V
than -1.5V.
voltage rail or go below ground by more
DD
When operated with a 2.7V to 3.6V supply, the FSx switches
are active (turned ON) whenever the IN logic control voltage
is ≤0.5V and the EN logic voltage ≥1.4V.
The part consist of two 7Ω full speed (FSx) switches and two
4.5Ω high speed (HSx) switches. The FSx switches can
swing from 0V to V . They were designed to pass USB full-
DD
speed (12Mbps) differential data signals with minimal
distortion. The HSx switches have high bandwidth and low
capacitance to pass USB high-speed (480Mbps) differential
data signals with minimal edge and phase distortion.
HSx Switches (HSD1, HSD2)
The two HSx switches (HSD2, HSD1) are bidirectional
switches that can pass rail-to-rail signals. When powered
with a 3.3V supply these switches have a nominal r
of
(ON)
The ISL54200 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have both high-speed and full-speed transceivers and
need to multiplex between these USB sources to a single
USB host (computer). A typical application block diagram of
this functionality is shown above.
4.5Ω over the signal range of 0V to 400mV with a r
flatness of 0.4Ω. The r
HSD2 switches over this signal range is only 0.01Ω ensuring
(ON)
matching between the HSD1 and
(ON)
minimal impact by the switches to USB high speed signal
transitions. As the signal level increases the r
switch,
(ON)
resistance increases. At signal level of 3.3V the switch
resistance is nominally 20Ω.
A detailed description of the two types of switches are
provided in the sections below.
The HSx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals typically in the
range of 0V to 400mV. They have low capacitance and high
bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0 high
speed signal quality specifications. See high-speed eye
diagrams Figures 9 and 10.
FSx Switches (FSD1, FSD2)
The two FSx switches (FSD1, FSD2) are bidirectional
switches that can pass rail-to-rail signals. When powered
with a 3.3V supply, these switches have a nominal r
(ON)
resistance of 7Ω over the signal range of 0V to 3.3V. They
FN6408.0
January 24, 2007
8
ISL54200
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See full-
speed eye diagram Figure 11.
computer. The device will be able to transmit and receive
data from the computer at a data rate of 12Mbps.
High-speed Mode
If the IN pin = Logic “1” and EN pin = Logic “1” the part will go
into high-speed mode. In high-speed mode the HSD1 and
HSD2 switches are ON and the FSD1 and FSD2 switches
are OFF (high impedance). When a USB cable from a
computer or USB hub is connected at the common USB
connector and the part is in the high-speed mode a link will
be established between the high-speed driver section of the
media player and the computer. The device will be able to
transmit and receive data from the computer at a data rate of
480Mbps.
The maximum signal range for the HSx switches is from
-1.5V to V . The signal voltage should not be allow to
DD
exceed the V
than -1.5V.
voltage rail or go below ground by more
DD
The HSx switches are active (turned ON) whenever the IN
voltage is ≥1.4V and the EN logic voltage ≥1.4V when
operated with a 2.7V to 3.6V supply.
ISL54200 Operation
The discussion that follows will discuss using the ISL54200 in
the typical application shown in the block diagram on page 9.
All Switches OFF Mode
If the IN pin = Logic “0” or Logic “1” and EN pin = Logic “0” all
of the switches will turn OFF (high impedance).
POWER
The power supply connected at the VDD (pin 1) provides the
DC bias voltage required by the ISL54200 part for proper
operation. The ISL54200 can be operated with a VDD
voltage in the range of 2.7V to 5.5V. When used in a USB
application the VDD voltage should be kept in the range of
3.0V to 5.5V to ensure you get the proper signal levels for
good signal quality.
The all OFF state can be used to switch between the two
USB sections of the media player. When disconnecting from
one USB device to the other USB device you can
momentarily put the ISL54400 switch in the “all off” state in
order to get the computer to disconnect from the one device
so it can properly connect to the other USB device when that
channel is turned ON.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any power
supply noise from entering the part. The capacitor should be
located as close to the VDD pin as possible.
LOGIC CONTROL
The state of the ISL54200 device is determined by the
voltage at the IN pin (pin 2) and the EN pin (pin 10). IN is
only active when the EN pin is logic “1” (High). Refer to“Truth
Table” on page 2.
The EN pin is internally pulled low through a 4MΩ resistor to
ground. For logic “0” (Low) it can be driven low or allowed to
Float. The IN pin must be driven low or high and cannot be
left floating.
Logic control voltage levels:
EN = Logic “0” (Low) when V
≤0.5V or Floating.
≥1.4V
EN
EN = Logic “1” (High) when V
EN
IN = Logic “0” (Low) when V ≤0.5V.
IN
IN = Logic “1” (High) when V ≥1.4V
IN
Full-speed Mode
If the IN pin = Logic “0” and EN pin = Logic “1” the part will be
in the full-speed mode. In this mode the FSD1 and FSD2
switches are ON and the HSD1 and HSD2 switches are OFF
(high impedance). In a typical application V
will be in the
DD
range of 2.8V to 3.6V and will be connected to the battery or
LDO of the portable media device. When a computer or USB
hub is plugged into the common USB connector and the part
is in the full-speed mode a link will be established between
the full-speed driver section of the media player and the
FN6408.0
January 24, 2007
9
ISL54200
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
V
= 3.3V
DD
TIME (10ns/DIV.)
FIGURE 8. EYE PATTERN: 12MBPS USB SIGNAL WITH FSX SWITCHES IN THE SIGNAL PATH
FN6408.0
January 24, 2007
10
ISL54200
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
V
= 3.3V
DD
TIME (0.2ns/DIV.)
FIGURE 9. EYE PATTERN WITH FAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
FN6408.0
January 24, 2007
11
ISL54200
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
V
= 3.3V
DD
TIME (0.2ns/DIV.)
FIGURE 10. EYE PATTERN WITH NEAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
FN6408.0
January 24, 2007
12
ISL54200
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
V
= 3.3V
DD
TIME (0.2ns/DIV.)
FIGURE 11. EYE PATTERN: 12MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
-10
6
R
= 45Ω
= 0.2V
L
V+ = 3.3V
= 40mA
-20
-30
-40
V
to 2V
P-P P-P
IN
I
COM
5.5
85°C
5
-50
25°C
4.5
-60
-70
4
3.5
3
-80
-90
-40°C
-110
0
0.1
0.2
(V)
0.3
0.4
0.001
0.01
0.1
1
10
100
500
V
FREQUENCY (MHz)
COM
FIGURE 12. HSx SWITCH ON RESISTANCE vs SWITCH
VOLTAGE
FIGURE 13. OFF-ISOLATION
FN6408.0
January 24, 2007
13
ISL54200
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
-10
Die Characteristics
R
V
= 45Ω
= 0.2V
L
-20
-30
-40
to 2V
P-P
IN
P-P
SUBSTRATE POTENTIAL (POWERED UP):
GND (TDFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
-50
-60
98
PROCESS:
-70
Submicron CMOS
-80
-90
-110
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 14. CROSSTALK
FN6408.0
January 24, 2007
14
ISL54200
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L10.2.1x1.6A
D
A
B
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
6
MILLIMETERS
INDEX AREA
N
E
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
2X
0.10 C
A
A1
A3
b
0.50
-
1
2
2X
0.10 C
-
-
0.05
-
TOP VIEW
0.127 REF
-
0.15
2.05
1.55
0.20
0.25
2.15
1.65
5
0.10 C
0.05 C
D
2.10
-
C
A
E
1.60
-
SEATING PLANE
e
0.50 BSC
-
A1
k
0.20
0.35
-
0.40
10
4
-
-
SIDE VIEW
L
0.45
-
(DATUM A)
N
2
PIN #1 ID
Nd
Ne
θ
3
4xk
1
2
NX L
1
3
N
0
-
12
4
(DATUM B)
Rev. 3 6/06
N-1
NOTES:
5
NX b
e
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
0.10 M C A B
0.05 M C
3
(ND-1) X e
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
C
L
(A1)
NX (b)
L
5
7. Maximum package warpage is 0.05mm.
e
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
SECTION "C-C"
TERMINAL TIP
C C
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
FOR ODD TERMINAL/SIDE
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
b
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
0.25
0.50
DETAIL “A” PIN 1 ID
10
LAND PATTERN
FN6408.0
January 24, 2007
15
ISL54200
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
MILLIMETERS
2X
0.10
C B
SYMBOL
MIN
0.70
-
NOMINAL
MAX
0.80
0.05
NOTES
A
A1
A3
b
0.75
-
-
0.20 REF
0.25
3.0
-
E
-
6
INDEX
AREA
0.20
2.95
2.25
2.95
1.45
0.30
3.05
2.35
3.05
1.55
5, 8
D
-
TOP VIEW
B
A
D2
E
2.30
3.0
7, 8
-
// 0.10
0.08
C
E2
e
1.50
0.50 BSC
-
7, 8
-
C
k
0.25
0.25
-
-
A3
C
SIDE VIEW
L
0.30
10
0.35
8
SEATING
PLANE
N
2
D2
D2/2
2
Nd
5
3
7
8
(DATUM B)
Rev. 3 3/06
NOTES:
1
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
NX k
E2
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
NX b
5
8
e
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
(A1)
NX (b)
L1
L
9
5
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6408.0
January 24, 2007
16
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