ISL54205AIRZ-T [INTERSIL]
MP3/USB 2.0 High Speed Switch with Negative Signal Handling; MP3 / USB 2.0高速开关，可处理负信号处理
| 型号： | ISL54205AIRZ-T |
| 厂家： | 
Intersil |
| 描述： | MP3/USB 2.0 High Speed Switch with Negative Signal Handling |
| 文件： | 总14页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL54205A
®
Data Sheet
December 7, 2006
FN6342.1
MP3/USB 2.0 High Speed Switch with
Negative Signal Handling
Features
• High Speed (480Mbps) Signaling Capability per USB 2.0
• Low Distortion Negative Signal Capability
The Intersil ISL54205A dual SPDT (Single Pole/Double
Throw) switches combine low distortion audio and accurate
USB 2.0 high speed data (480Mbps) signal switching in the
same low voltage device. When operated with a 2.7V to 3.6V
single supply these analog switches allow audio signal swings
below-ground, allowing the use of a common USB and audio
headphone connector in Personal Media Players and other
portable battery powered devices.
• Detection of V
BUS
Voltage on USB Cable
• Control Pin to Open all Switches and Enter Low Power
State
• Low Distortion Headphone Audio Signals
- THD+N at 20mW into 32Ω Load . . . . . . . . . . . . . <0.1%
• Cross-talk (20Hz to 20kHz) . . . . . . . . . . . . . . . . . . -110dB
The ISL54205A incorporates circuitry for detection of the USB
V
voltage, which is used to switch between the audio and
• Single Supply Operation (V ) . . . . . . . . . . . . 2.7V to 3.6V
DD
BUS
USB signal sources in the portable device. The part has a
control pin to open all the switches and put the part in a low
power down state.
• -3dB Bandwidth USB Switch. . . . . . . . . . . . . . . . . 630MHz
• Available in μTQFN and TDFN Packages
• Pb-Free Plus Anneal (RoHS Compliant)
The ISL54205A is available in a small 10 Ld 2.1mm x 1.6mm
ultra-thin μTQFN package and a 10Ld 3mm x 3mm TDFN
package. It operates over a temperature range of -40 to
+85°C.
• Compliant with USB 2.0 Short Circuit Requirements
Without Additional External Components
Applications
Related Literature
• Application Note AN1280 “ISL54205EVAL1Z Evaluation
Board User’s Manual.
• MP3 and Other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Audio/USB Switching
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Application Block Diagram
V
DD
μCONTROLLER
ISL54205A
V
BUS
CTRL
Logic Circuitry
22kΩ
USB
4MΩ
4MΩ
HIGH-SPEED
D-
COM -
COM +
TRANSCEIVER
D+
50kΩ
50kΩ
L
R
CODEC
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL54205A
Pinouts (Note 1)
ISL54205A
(10 LD μTQFN)
TOP VIEW
ISL54205A
(10 LD TDFN)
TOP VIEW
CTRL
10
CTRL
D-
4M
VDD
10
9
1
4M
VDD
9
LOGIC
CONTROL
VBUS
1
D-
LOGIC
CONTROL
2
4M
VBUS
COM -
COM +
D+
2
3
4
8
COM -
D+
L
3
4
5
8
7
6
4M
7
L
COM +
GND
6
R
R
50k
50k
50k
50k
5
GND
NOTE:
1. ISL54205 Switches shown for V
= Logic “0” and CTRL = Logic “1”.
BUS
Truth Table
Pin Descriptions
ISL54205A
ISL54205A
V
CTRL
L, R
OFF
D+, D-
OFF
OFF
ON
PIN NO.
NAME
VDD
VBUS
COM-
COM+
GND
R
FUNCTION
BUS
0
0
1
X
1
2
Power Supply
0
1
ON
Digital Control Input
OFF
3
Voice and Data Common Pin
Voice and Data Common Pin
Ground Connection
CTRL: Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V
4
V
: Logic “0” when ≤ V
+ 0.8V
+ 0.2V or Floating, Logic “1” when
BUS
≥V
DD
5
DD
6
Audio Right Input
Ordering Information
7
L
Audio Left Input
TEMP.
RANGE
(°C)
8
D+
USB Differential Input
USB Differential Input
Digital Control Input (Audio Enable)
PART
PKG.
DWG. #
9
D-
PART NUMBER MARKING
PACKAGE
10
CTRL
ISL54205AIRUZ-T FT
(Note)
-40 to +85 10 Ld μTQFN L10.2.1x1.6A
Tape and Reel
(Pb-free)
ISL54205AIRZ-T
(Note)
205Z
205Z
-40 to +85 10 Ld TDFN
Tape and Reel
(Pb-free)
L10.3x3A
L10.3x3A
ISL54205AIRZ
(Note)
-40 to +85 10 Ld TDFN
(Pb-free)
ISL54205EVAL1Z
-40 to +85 Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate or
NiPdAu termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
FN6342.1
December 7, 2006
2
ISL54205A
Absolute Maximum Ratings
Thermal Information
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
DD
Input Voltages
D+, D-, L, R (Note 2) . . . . . . . . . . . . . . . . . - 2V to ((V ) + 0.3V)
JA
10 Ld μTQFN Package . . . . . . . . . . . . . . . . . . . . . . .
10 Ld 3x3 TDFN Package. . . . . . . . . . . . . . . . . . . . .
130
110
DD
(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V
V
BUS
CTRL (Note 2). . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V ) + 0.3V)
Output Voltages
DD
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . -65°C to +150°C
COM-, COM+ (Note 2) . . . . . . . . . . . . . . . . -2V to ((V ) + 0.3V)
DD
Continuous Current (Audio Switches). . . . . . . . . . . . . . . . . ±150mA
Peak Current (Audio Switches)
(Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . ±300mA
Continuous Current (USB Switches). . . . . . . . . . . . . . . . . . . ±40mA
Peak Current (USB Switches)
Operating Conditions
Temperature Range
ISL54205AIRUZ and ISL54205AIRZ . . . . . . . . . . . . -40°C to +85°C
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >7kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >450V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on D+, D-, L, R, COM-, COM+, CTRL, V
ratings.
exceeding V
or GND by specified amount are clamped. Limit current to maximum current
DD
BUS
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.0V, GND = 0V, V
= 3.8V, V = 3.2V,
BUSL
DD
BUSH
= 0.5V, (Notes 4, 6), unless otherwise specified.
V
= 1.4V, V
CTRLH
CTRLL
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Audio Switches (L, R)
Analog Signal Range, V
ANALOG
V
V
= 3.0V, V
= 3.0V, V
= float, CTRL = 1.4V
= float, CTRL = 1.4V,
Full
+25
Full
-1.5
-
2.65
-
1.5
4
V
Ω
Ω
DD
BUS
ON Resistance, r
ON
-
-
DD
BUS
I
= 100mA, V or V = -0.85V to 0.85V,
COMx
L R
5.5
(See Figure 3)
r
Matching Between Channels,
V
= 3.0V, V
= float, CTRL = 1.4V, I
= 100mA,
BUS
V or V = Voltage at max r over signal range of -0.85V
ON
+25
Full
-
-
0.02
-
0.13
0.16
Ω
Ω
ON
Δr
DD
COMx
ON
L
R
to 0.85V, (Note 9)
r
Flatness, r
V
= 3.0V, V
= float, CTRL = 1.4V,
= 100mA, V or V = -0.85V to 0.85V, (Note 7)
+25
Full
+25
-
-
-
0.03
-
0.05
0.07
-
Ω
Ω
ON
FLAT(ON)
DD
BUS
I
COMx
L
R
Discharge Pull-Down Resistance,
R , R
V
V
V
= 3.6V, V
= float, CTRL = 1.4V, V
or
= -0.85V, 0.85V, V or V = -0.85V, 0.85V,
50
kΩ
DD
BUS
COM-
L
R
COM+
L
R
and V = floating, Measure current through the
D+
D-
discharge pull-down resistor and calculate resistance
value.
USB Switches (D+, D-)
Analog Signal Range, V
V
V
= 3.0V, V
= 3.6V, V
= 5.0V, CTRL = 0V or 3V
= 4.4V, CTRL = 0V or 3.6V,
Full
+25
Full
0
-
-
4.6
-
V
V
Ω
Ω
ANALOG
DD
BUS
DD
ON Resistance, r
ON
5
DD
BUS
I
= 40mA, V or V = 0V to 400mV
COMx
D+ D-
-
6.5
(See Figure 4)
r
Matching Between Channels,
V
= 3.6V, V
BUS
= 4.4V, CTRL = 0V or 3.6V,
+25
Full
-
-
0.06
-
0.5
Ω
Ω
ON
Δr
DD
I
= 40mA, V or V = Voltage at max r
,
ON
COMx
D+ D-
ON
0.55
(Note 8)
FN6342.1
December 7, 2006
3
ISL54205A
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.0V, GND = 0V, V
= 3.8V, V
= 3.2V,
BUSL
DD
BUSH
V
= 1.4V, V
= 0.5V, (Notes 4, 6), unless otherwise specified.
CTRLH
CTRLL
(Continued)
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
Flatness, R
TEST CONDITIONS
TYP
r
V
= 3.6V, V
BUS
= 4.4V, CTRL = 0V or 3.6V,
+25
Full
+25
Full
-
0.4
0.6
1.0
10
Ω
Ω
ON
FLAT(ON)
DD
I
= 40mA, V or V = 0V to 400mV, (Note 7)
COMx
D+ D-
-
-
-
-
OFF Leakage Current, I
or
V
V
V
= 3.6V, V = 0V, CTRL = 3.6V, V
BUS COM-
or
-10
-70
nA
nA
D+(OFF)
DD
I
= 0.5V, 0V, V or V = 0V, 0.5V, V and
D-(OFF)
COM+
D+ D-
L
70
= float
R
ON Leakage Current, I
V
V
= 3.3V, V
BUS
= 5.25V, CTRL = 0V or 3.6V, V or
D+
,V
+25
Full
-10
-75
2
-
10
75
nA
nA
Dx
DD
= 2.0V, V , V and V = float
D-
COM- COM+ L R
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V
V
V
V
= 2.7V, R = 50Ω, C = 10pF, (See Figure 1)
+25
+25
+25
+25
-
-
-
-
67
48
18
50
-
-
-
-
ns
ns
ns
ps
ON
Turn-OFF Time, t
DD
DD
DD
DD
L
L
= 2.7V, R = 50Ω, C = 10pF, (See Figure 1)
OFF
Break-Before-Make Time Delay, t
L
L
= 2.7V, R = 50Ω, C = 10pF, (See Figure 2)
D
L
L
Skew, t
= 3.0V, V
= 5.0V, CTRL = 0V or 3V, R = 45Ω,
SKEW
BUS L
C
= 10pF, t = t = 720ps at 480Mbps,
L
R F
(Duty Cycle = 50%) (See Figure 7)
Total Jitter, t
V
C
= 3.0V, V = 5.0V, CTRL = 0V or 3V, R = 50Ω,
+25
+25
+25
-
-
-
210
250
-110
-
-
-
ps
ps
dB
J
DD
BUS
L
= 10pF, t = t = 750ps at 480Mbps
L
R
F
Propagation Delay, t
V
C
= 3.0V, V
= 5.0V, CTRL = 0V or 3V, R = 45Ω,
PD
DD
BUS L
= 10pF, (See Figure 7)
L
Crosstalk (Channel-to-Channel),
R to COM-, L to COM+
V
= 3.0V, V
= float, CTRL = 3.0V, R = 32Ω,
BUS L
DD
f = 20Hz to 20kHz, V or V = 0.707V
(2V ),
R
L
RMS
P-P
(See Figure 6)
Total Harmonic Distortion
f = 20Hz to 20kHz, V
= 3.0V, V
= float,
+25
-
0.06
-
%
DD
BUS
(2V ), R = 32Ω
CTRL = 3.0V, V or V = 0.707V
L
R
RMS
P-P
L
USB Switch -3dB Bandwidth
Signal = 0dBm, 0.2V
offset, R = 50Ω, C = 5pF
+25
+25
-
-
630
6
-
-
MHz
pF
DC
L
L
D+/D- OFF Capacitance, C
, f = 1MHz, V
= 3.0V, V
= float, CTRL = 3.0V,
DD
or V = V = 0V, (See Figure 5)
COMx
D+(OFF)
BUS
C
V
D-(OFF)
D-
D+
f = 1MHz, V
L/R OFF Capacitance, C
,
= 3.0V, V
= 5.0V, CTRL = 0V or 3V,
+25
+25
-
-
9
-
-
pF
pF
LOFF
DD
V or V = V
BUS
= 0V, (See Figure 5)
C
ROFF
L
R
COMx
= 3.0V, V
COM ON Capacitance, C
, f = 1MHz, V
= 5.0V, CTRL = 0V or 3V,
10
COM-(ON)
DD
or V = V = 0V, (See Figure 5)
COMx
BUS
C
V
COM+(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V
D-
D+
Full
+25
Full
+25
Full
2.7
3.6
8
V
DD
Positive Supply Current, I
V
= 3.6V, V
= 3.6V, V
= float or 5.25V, CTRL = 1.4V
= 0V or float, CTRL = 0V or float
-
-
-
-
6
-
μA
μA
nA
nA
DD
DD
BUS
10
7
Positive Supply Current, I
(Low Power State)
V
1
-
DD
DD
BUS
140
DIGITAL INPUT CHARACTERISTICS
V
V
Voltage Low, V
BUSL
V
V
V
V
V
= 2.7V to 3.6V
= 2.7V to 3.6V
= 2.7V to 3.6V
= 2.7V to 3.6V
Full
Full
Full
Full
Full
-
-
-
V + 0.2
DD
V
V
BUS
BUS
DD
DD
DD
DD
DD
Voltage High, V
V
+ 0.8
-
0.5
-
BUSH
DD
CTRL Voltage Low, V
-
-
V
CTRLL
CTRL Voltage High, V
1.4
-50
-
V
CTRLH
Input Current, I
, I
= 3.6V, V
BUS
= 0V or float, CTRL = 0V or float
20
50
nA
BUSL CTRLL
FN6342.1
December 7, 2006
4
ISL54205A
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +3.0V, GND = 0V, V
= 3.8V, V
= 3.2V,
BUSL
DD
BUSH
V
= 1.4V, V
= 0.5V, (Notes 4, 6), unless otherwise specified.
CTRLH
CTRLL
(Continued)
TEMP
(°C)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
TEST CONDITIONS
TYP
1.1
1.1
4
Input Current, I
V
V
V
V
= 3.6V, V
= 3.6V, V
= 3.6V, V
= 3.6V, V
= 5.25V, CTRL = 0V or float
= 0V or float, CTRL = 3.6V
= 5.25V, CTRL = 0V or float
= 0V or float, CTRL = 3.6V
Full
Full
Full
Full
-2
-2
-
2
-2
-
μA
μA
BUSH
DD
DD
DD
DD
BUS
BUS
BUS
BUS
Input Current, I
CTRLH
V
Pull-Down Resistor, R
MΩ
MΩ
BUS
VBUS
CTRL Pull-Down Resistor, R
NOTES:
-
4
-
CTRL
4. V
= Input voltage to perform proper function.
LOGIC
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed by design.
9. r
matching between channels is calculated by subtracting the channel with the highest max r
value from the channel with lowest max r
ON ON
ON
value, between L and R or between D+ and D-.
Test Circuits and Waveforms
C
V
t < 20ns
r
BUSH
V
DD
t < 20ns
f
LOGIC
INPUT
V
50%
BUSL
CTRL
AUDIO OR USB
t
OFF
V
INPUT
V
OUT
SWITCH
INPUT
SWITCH
INPUT
COMX
V
INPUT
0V
V
OUT
V
BUS
90%
90%
R
C
L
SWITCH
OUTPUT
V
L
GND
BUS
10pF
50Ω
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
R
capacitance.
L
---------------------------
V
= V
OUT
(INPUT)
R
+ r
(ON)
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FN6342.1
December 7, 2006
5
ISL54205A
Test Circuits and Waveforms (Continued)
V
DD
C
V
BUSH
LOGIC
INPUT
CTRL
D- or D+
V
BUSL
V
V
OUT
INPUT
COMx
L or R
C
R
50Ω
L
L
V
OUT
0V
10pF
V
90%
BUS
SWITCH
OUTPUT
GND
V
BUS
t
D
Repeat test for all switches. C includes fixture and stray capacitance.
L
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 2B. TEST CIRCUIT
V
V
DD
DD
C
C
r
= V /40mA
r
= V /100mA
1
ON 1
ON
CTRL
D- or D+
CTRL
L OR R
V
D- or D+
V
L OR R
OV OR FLOAT
4.4V to 5.25V
V
V
BUS
V
BUS
V
1
1
40mA
100mA
COMx
COMX
GND
GND
Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. USB r
TEST CIRCUIT
FIGURE 3. AUDIO r
TEST CIRCUIT
ON
ON
FN6342.1
December 7, 2006
6
ISL54205A
Test Circuits and Waveforms (Continued)
V
DD
V
DD
C
C
CTRL
L or R
CTRL
SIGNAL
GENERATOR
32Ω
AUDIO OR USB
COMx
V
V
BUS
BUS
IMPEDANCE
ANALYZER
0V or Float
V
or
BUSL
V
BUSH
COMx
GND
R or L
COMx
ANALYZER
N.C.
GND
R
L
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CAPACITANCE TEST CIRCUIT
FIGURE 6. AUDIO CROSSTALK TEST CIRCUIT
V
DD
C
t
ri
CTRL
90%
50%
V
V
BUSH
15.8Ω
BUS
10%
90%
DIN+
DIN-
t
skew_i
OUT+
D+
D-
COM+
DIN+
50%
10%
45Ω
143Ω
15.8Ω
C
L
OUT-
COM-
DIN-
t
fi
45Ω
C
t
143Ω
L
ro
90%
10%
90%
GND
50%
OUT+
OUT-
t
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
skew_o
50%
10%
t
f0
FIGURE 7B. TEST CIRCUIT
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7. SKEW TEST
FN6342.1
December 7, 2006
7
ISL54205A
Application Block Diagram
V
DD
μCONTROLLER
ISL54205A
V
BUS
CTRL
LOGIC CIRCUITRY
22kΩ
USB
4MΩ
4MΩ
HIGH-SPEED
TRANSCEIVER
D-
COM -
COM +
D+
50kΩ
50kΩ
L
R
CODEC
GND
Audio Switches
Detailed Description
The two audio switches (L, R) are 3Ω switches that can pass
signals that swing below ground. Crosstalk between the
audio switches over the audio band is < -110dB.
The ISL54205A device is a dual single pole/double throw
(SPDT) analog switch device that operates from a single DC
power supply in the range of 2.7V to 3.6V. It was designed to
function as a dual 2 to 1 multiplexer to select between USB
differential data signals and audio L and R stereo signals. It
comes in tiny μTQFN and TDFN packages for use in MP3
players, PDAs, cell phones, and other personal media
players.
Over a signal range of ±1V (0.707Vrms) with V
>2.7V,
DD
resistance
these switches have an extremely low r
ON
variation. They can pass ground referenced audio signals
with very low distortion (<0.06% THD+N) when delivering
15.6mW into a 32Ω headphone speaker load. See Figures 8,
9, 10, and 11 THD+N performance curves.
The part consists of two 3Ω audio switches and two 5Ω USB
switches. The audio switches can accept signals that swing
below ground. They were designed to pass audio left and
right stereo signals, that are ground referenced, with minimal
distortion. The USB switches were designed to pass high-
speed USB differential data signals with minimal edge and
phase distortion.
These switches are uni-directional switches. The audio
drivers should be connected at the L and R side of the switch
(pins 7 and 8) and the speaker loads should be connected at
the COM side of the switch (pins 3 and 4).
The audio switches are active (turned ON) whenever the
V
voltage is ≤ to V + 0.2V or floating and the CTRL
DD
BUS
voltage ≥ to 1.4V.
The ISL54205A was specifically designed for MP3 players,
cell phones and other personal media player applications
that need to combine the audio headphone jack and the
USB data connector into a single shared connector, thereby
saving space and component cost. A typical application
block diagram of this functionality is shown above.
Note: Whenever the audio switches are ON the USB
transceivers need to be in the high impedance state or static
high or low state.
USB Switches
The ISL54205A incorporates circuitry for the detection of the
The two USB switches (D+, D-) are 5Ω bidirectional switches
that are designed to pass high-speed USB differential
signals in the range of 0V to 400mV. The switches have low
capacitance and high bandwidth to pass USB high-speed
signals (480Mbps) with minimum edge and phase distortion
to meet USB 2.0 signal quality specifications. See Figure 12
for High-speed Eye Pattern taken with switch in the signal
path.
USB V
voltage, which is used to switch between the
BUS
audio CODEC drivers and USB transceiver of the MP3
player or cell phone. The ISL54205A contains a logic control
pin (CTRL) that when driven Low while V
is Low, opens
BUS
all switches and puts the part into a low power state, drawing
typically 1nA of I current.
DD
A detailed description of the two types of switches is
provided in the sections below. The USB transmission and
audio playback are intended to be mutually exclusive
operations.
The maximum signal range for the USB switches is from
-1.5V to V . The signal voltage at D- and D+ should not be
DD
allowed to exceed the V
by more than -1.5V.
voltage rail or go below ground
DD
FN6342.1
December 7, 2006
8
ISL54205A
The USB switches are active (turned ON) whenever the
voltage is ≥ to V + 0.8V. V is internally pulled
Low Power Mode
V
BUS
low, so when V
DD BUS
If the VBUS pin = Logic “0” and CTRL pin = Logic “0,” the
part will be in the Low Power mode. In the Low Power mode,
the audio switches and the USB switches are OFF (high
impedance). In this state, the device draws typically 1nA of
current.
is floating, the USB switches are OFF.
BUS
Note: Whenever the USB switches are ON the audio drivers
of the CODEC need to be at AC or DC ground or floating to
keep from interfering with the data transmission.
EXTERNAL VBUS SERIES RESISTOR
ISL54205A Operation
The ISL54205A contains a clamp circuit between VBUS and
VDD. Whenever the VBUS voltage is greater than the VDD
voltage by more than 2.55V, current will flow through this
The discussion that follows will discuss using the ISL54205A
in the typical application shown in the block diagram on
page 8.
clamp circuitry into the V
power supply bus.
DD
LOGIC CONTROL
During normal USB operation, V
3.6V and V
BUS
is in the range of 2.7V to
DD
is in the range of 4.4V to 5.25V. The clamp
The state of the ISL54205A device is determined by the
voltage at the VBUS pin (pin 2) and the CTRL pin (pin 10).
Refer to truth-table on page 2 of data sheet.
circuit is not active and no current will flow through the clamp
into the VDD supply.
The VBUS pin and CTRL pin are internally pulled low
through 4MΩ resistors to ground and can be left floating. The
In a USB application, the situation can exist where the V
BUS
voltage from the computer could be applied at the VBUS pin
before the V voltage is up to its normal operating voltage
CTRL control pin is only active when V
is logic “0”.
BUS
DD
range and current will flow through the clamp into the V
Logic control voltage levels:
DD
power supply bus. This current could be quite high when
is OFF or at 0V and could potentially damage other
V
= Logic “0” (Low) when V
≤ V
+ 0.2V or
+ 0.8V
BUS
Floating.
= Logic “1” (High) when V
BUS
DD
V
DD
components connected in the circuit. In the application
circuit, a 22kΩ resistor has been put in series with the VBUS
pin to limit the current to a safe level during this situation.
V
≥ V
BUS
BUS
DD
CTRL = Logic “0” (Low) when ≤ 0.5V or floating.
CTRL = Logic “1” (High) when ≥ 1.4V
It is recommended that a current limiting resistor in the range
of 10kΩ to 50kΩ be connected in series with the VBUS pin. It
will have minimal impact on the logic level at the VBUS pin
during normal USB operation and protect the circuit during
the time VBUS is present before VDD is up to its normal
operating voltage.
Audio Mode
If the VBUS pin = Logic “0” and CTRL pin = Logic “1,” the
part will be in the Audio mode. In Audio mode the L (left) and
R (right) 3Ω audio switches are ON and the D- and D+ 5Ω
switches are OFF (high impedance). In a typical application,
V
will be in the range of 2.7V to 3.6V and will be
DD
connected to the battery or LDO of the MP3 player or cell
phone. When a headphone is plugged into the common
connector, nothing gets connected at the VBUS pin (it is
floating) and as long as the CTRL = Logic “1,” the
ISL54205A part remains in the audio mode and the audio
drivers of the player can drive the headphones and play
music.
Note: No external resistor is required in applications where
V
will not exceed V by more than 2.55V.
DD
BUS
POWER
The power supply connected at VDD (pin 1) provides power
to the ISL54205A part. Its voltage should be kept in the
range of 2.7V to 3.6V when used in a USB/Audio application
to ensure you get proper switching when the V
at its lower limit of 4.4V.
voltage is
BUS
USB Mode
If the VBUS pin = Logic “1” and CTRL pin = Logic “0” or
Logic “1,” the part will go into USB mode. In USB mode, the
D- and D+ 5Ω switches are ON and the L and R 3Ω audio
switches are OFF (high impedance). When a USB cable
from a computer or USB hub is connected at the common
connector, the voltage at the VBUS pin will be driven to be in
the range of 4.4V to 5.25V. The ISL54205A part will go into
the USB mode. In USB mode, the computer or USB hub
transceiver and the MP3 player or cell phone USB
transceiver are connected and digital data will be able to be
transmitted back and forth.
When the USB cable is disconnected, the ISL54205A
automatically turns the D+ and D- switches OFF.
FN6342.1
December 7, 2006
9
ISL54205A
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.4
0.3
0.2
0.1
0
R
V
= 32Ω
R
V
= 32Ω
= 0.707V
LOAD
= 3V
LOAD
LOAD
DD
RMS
3V
P-P
V
= 2.6V
DD
2.5V
V
= 2.7V
P-P
DD
V
= 3.6V
DD
2V
P-P
V
= 3V
DD
1V
P-P
20
200
FREQUENCY (Hz)
2k
20k
20
200
FREQUENCY (Hz)
2k
20k
FIGURE 8. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY
0.5
0.5
0.4
0.3
0.2
0.1
R
= 32Ω
R
= 32Ω
LOAD
FREQ = 1kHz
= 3V
LOAD
FREQ = 1kHz
= 3V
V
V
DD
DD
0.4
0.3
0.2
0.1
0
0
0
10
20
30
40
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (mW)
OUTPUT VOLTAGE (V
)
P-P
FIGURE 10. THD+N vs OUTPUT VOLTAGE
FIGURE 11. THD+N vs OUTPUT POWER
FN6342.1
December 7, 2006
10
ISL54205A
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
TIME (10ns/DIV)
FIGURE 12. EYE PATTERN: 480Mbps WITH SWITCH IN THE SIGNAL PATH
FN6342.1
December 7, 2006
11
ISL54205A
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
1
USB SWITCH
Die Characteristics
0
-1
-2
-3
-4
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
98
PROCESS:
Submicron CMOS
R
= 50Ω
L
V
= 0.2V
to 2V
IN
P-P P-P
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE
FN6342.1
December 7, 2006
12
ISL54205A
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L10.2.1x1.6A
D
A
B
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
6
MILLIMETERS
INDEX AREA
N
E
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
2X
0.10 C
A
A1
A3
b
0.50
-
1
2
2X
0.10 C
-
-
0.05
-
TOP VIEW
0.127 REF
-
0.15
2.05
1.55
0.20
0.25
2.15
1.65
5
0.10 C
0.05 C
D
2.10
-
C
A
E
1.60
-
SEATING PLANE
e
0.50 BSC
-
A1
k
0.20
0.35
-
0.40
10
4
-
-
SIDE VIEW
L
0.45
-
(DATUM A)
N
2
PIN #1 ID
Nd
Ne
θ
3
4xk
1
2
NX L
1
3
N
0
-
12
4
(DATUM B)
Rev. 3 6/06
N-1
NOTES:
5
NX b
e
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
0.10 M C A B
0.05 M C
3
(ND-1) X e
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
C
L
(A1)
NX (b)
L
5
7. Maximum package warpage is 0.05mm.
e
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
SECTION "C-C"
TERMINAL TIP
C C
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
FOR ODD TERMINAL/SIDE
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
b
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
0.25
0.50
DETAIL “A” PIN 1 ID
10
LAND PATTERN
FN6342.1
December 7, 2006
13
ISL54205A
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
MILLIMETERS
2X
0.10
C B
SYMBOL
MIN
0.70
-
NOMINAL
MAX
0.80
0.05
NOTES
A
A1
A3
b
0.75
-
-
0.20 REF
0.25
3.0
-
E
-
6
INDEX
AREA
0.20
2.95
2.25
2.95
1.45
0.30
3.05
2.35
3.05
1.55
5, 8
D
-
TOP VIEW
B
A
D2
E
2.30
3.0
7, 8
-
// 0.10
0.08
C
E2
e
1.50
0.50 BSC
-
7, 8
-
C
k
0.25
0.25
-
-
A3
C
SIDE VIEW
L
0.30
10
0.35
8
SEATING
PLANE
N
2
D2
D2/2
2
Nd
5
3
7
8
(DATUM B)
Rev. 3 3/06
NOTES:
1
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
NX k
E2
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
NX b
5
8
e
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
(A1)
NX (b)
L1
L
9
5
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6342.1
December 7, 2006
14
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