ISL54051IHZ-T_技术文档

Ultra Low ON-Resistance, Low Voltage, Single

Supply, Single SPST Analog Switches

ISL54051, ISL54052

Features

• ON-resistance (r

)

The Intersil ISL54051 and ISL54052 devices are low

ON-resistance, low voltage, bidirectional, single

pole/single throw (SPST) analog switches designed to

operate from a single +1.8V to +5.5V supply. Targeted

applications include battery powered equipment, which

ON

- V

= +5.0V. . . . . . . . . . . . . . . . . . . . . 0.8Ω

= +3.0V. . . . . . . . . . . . . . . . . . . . . 1.1Ω

= +1.8V. . . . . . . . . . . . . . . . . . . . . 2.3Ω

CC

benefit from low r

resistance (0.8Ω), excellent r

• r flatness (+4.5V supply) . . . . . . . . . . . . 0.25Ω

ON

• Single supply operation . . . . . . . . +1.8V to +5.5V

• Fast switching action (+4.5V supply)

ON

flatness, and fast switching speeds (t

= 24ns,

= 10ns). The digital logic input is 1.8V logic

ON

t

OFF

compatible when using a single +3.0V supply.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . 24ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns

ON

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins

may be limited and digital geometries are not well suited

to analog switch performance. This family of parts may

be used to switch in additional functionality while

reducing ASIC design risk. The ISL54051 and the

ISL54052 are offered in a 6 Ld 1.2mmx1.0mmx0.5mm

µTDFN package and a 6 Ld SOT-23 package, alleviating

board space limitations.

OFF

• ESD HBM rating. . . . . . . . . . . . . . . . . . . . . . >6kV

• 1.8V, CMOS logic compatible (+3V supply)

• Available in 6 Ld µTDFN and 6Ld SOT-23 Packages

• Pb-free (RoHS compliant)

Applications

• Battery powered, handheld, and portable equipment

- Cellular/mobile phones

The ISL54051 has one normally open (NO) switch and

ISL54052 has one normally closed (NC) switch.

- Pagers

- Laptops, notebooks, palmtops

TABLE 1. FEATURES AT A GLANCE

ISL54051

1

ISL54052

1

• Portable test and measurement

• Medical equipment

Number of Switches

SW

NO

NC

• Audio and video switching

1.8V r

ON

2.3Ω

Related Literature

1.8V t

/t

ON OFF

68ns/45ns

1.1Ω

68ns/45ns

1.1Ω

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

3V r

ON

3V t

/t

ON OFF

29ns/12ns

0.8Ω

29ns/12ns

0.8Ω

5V r

ON

5V t

/t

24ns/10ns

ON OFF

Packages

6 Ld µTDFN, 6Ld SOT-23

October 19, 2009

FN6459.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL54051, ISL54052

Ordering Information

PART NUMBER

PART

TEMP. RANGE

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 4)

MARKING

(°C)

ISL54051IRUZ-T (Note 2)

ISL54051IHZ-T (Note 3)

ISL54052IRUZ-T (Note 2)

ISL54052IHZ-T (Note 3)

NOTES:

A

-40 to +85

6 Ld (0.40mm pitch) 1.2x1.0x0.5 μTDFN, Tape and Reel L6.1.2x1.0A

6 Ld SOT-23, Tape and Reel MDP0038

6 Ld (0.40mm pitch) 1.2x1.0x0.5 μTDFN, Tape and Reel L6.1.2x1.0A

6 Ld SOT-23, Tape and Reel MDP0038

4051

B

4052

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54051, ISL54052. For more information on

MSL please see techbrief TB363.

Pin Configurations (Note 5)

ISL54051

(6 LD µTDFN)

TOP VIEW

ISL54051

(6 LD SOT-23)

TOP VIEW

N.C.

IN

1

2

3

6

GND

COM

V+

1

2

3

6

5

4

IN

NO

GND

N.C.

5

4

V+

NO

COM

ISL54052

(6 LD µTDFN)

(6 LD SOT-23)

TOP VIEW

NC

IN

1

2

3

6

GND

COM

V+

1

2

3

6

5

4

IN

N.C.

GND

5

4

N.C.

V+

COM

NC

NOTE:

5. Switches Shown for Logic “0” Input.

Truth Table

Pin Descriptions

LOGIC

ISL54051

ISL54052

FUNCTION

0

1

Off

On

Off

V+

System Power Supply Input (+1.8V to +5.5V)

Ground Connection

GND

IN

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 2V to 5V

Digital Control Input

supply.

COM

NO

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

No Connect

NC

N.C.

FN6459.3

October 19, 2009

2

ISL54051, ISL54052

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V

Input Voltages

NO, NC, IN (Note 6) . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COM (Note 6) . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Continuous Current NO, NC, or COM. . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ± 600mA

ESD Rating

Thermal Resistance (Typical)

θ_JA(°C/W) θ_JC(°C/W)

6 Ld µTDFN (Note 7) . . . . . . . . . .

6 Ld SOT-23 (Notes 7, 8) . . . . . . .

Maximum Junction Temperature (Plastic Package). . +150°C

Maximum Storage Temperature Range. . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

175

260

N/A

120

Operating Conditions

V+ (Positive DC Supply Voltage). . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . 0V to V+

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . .>2.2kV

V

(Digital Logic Input Voltage (IN) . . . . . . . . . . . 0V to V+

IN

Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum

current ratings.

7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

JA

TB379 for details.

8. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

= 2.4V, V = 0.8V (Note 9),

INL

Unless Otherwise Specified. Boldface limits apply over the operating temperature

INH

range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 4.5V, I

= 100mA, V

or

= 0V to V+, (See Figure 4, Note 13)

25

Full

25

-

0.86

1

-

Ω

ON

COM

NO

V

NC

-

r

Flatness, r

V+ = 4.5V, I

COM

= 100mA, V

NO

or

0.25

0.27

5

-

Ω

ON

FLAT(ON)

V

= 0V to V+, (Notes 12, 13)

NC

Full

25

-

Ω

NO or NC OFF Leakage

Current, I or

V+ = 5.5V, V

COM

= 0.3V, 5V, V

NO

or

-10

-150

10

150

nA

V

= 5V, 0.3V

NO(OFF)

NC

Full

-

I

NC(OFF)

COM ON Leakage Current, V+ = 5.5V, V

= 0.3V, 5V, or V

NO

or

25

-20

9

-

20

nA

COM

= 0.3V, 5V, or floating

I

V

COM(ON)

NC

Full

-300

300

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 4.5V, V

or V

= 3.0V, R = 50Ω,

25

Full

25

-

24

30

10

15

26

80

-

ns

pC

dB

ON

NO

NC

L

C = 35pF (See Figure 1, Note 13)

L

Turn-OFF Time, t

OFF

V+ = 4.5V, V

NO

L

or V

= 3.0V, R = 50Ω,

L

NC

C = 35pF (See Figure 1, Note 13)

Full

Charge Injection, Q

OFF Isolation

V = 0V, R = 0Ω, C = 1.0nF (See Figure 2) 25

G G L

R = 50Ω, C = 5pF, f = 100kHz,

25

L

RMS

V

= 1V

(See Figure 3)

COM

Total Harmonic Distortion f = 20Hz to 20kHz, V

COM

= 0.5V

,

25

-

0.012

-

%

P-P

R = 600Ω

L

-3dB Bandwidth

NO or NC OFF

R = 50Ω

25

-

190

16

-

MHz

pF

L

V+ = 4.5V, f = 1MHz, V or V = V

(See Figure 5)

= 0V

NO

NC

COM

Capacitance, C

OFF

FN6459.3

October 19, 2009

3

ISL54051, ISL54052

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

= 2.4V, V = 0.8V (Note 9),

INL

Unless Otherwise Specified. Boldface limits apply over the operating temperature

INH

range, -40°C to +85°C. (Continued)

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

COM ON Capacitance,

V+ = 4.5V, f = 1MHz, V or V = V

(See Figure 5)

= 0V

25

-

48

-

pF

NO NC COM

C

COM(ON)

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.8

-

0.075

-

5.5

0.1

2.5

V

Positive Supply Current, I+ V+ = 5.5V, V = 0V or V+

IN

-

µA

Full

-

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

INL

Full

-

0.8

-

V

Input Voltage High, V

INH

2.4

-0.1

Input Current, I

, I

V+ = 5.5V, V = 0V or V+

IN

0.1

µA

INH INL

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

= 1.4V, V

INL

= 0.5V (Note

INH

9), Unless Otherwise Specified. Boldface limits apply over the operating tem-

perature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

0

-

V+

V

ANALOG

ON-Resistance, r

(μTDFN)

,

V+ = 3V, I

COM

= 100mA, V

NO

or V

= 0V

25

Full

25

-

1.1

-

1.2

1.5

1.3

Ω

ON

NC

to V+, (See Figure 4, Note 13)

ON-Resistance, r

(SOT-23)

V+ = 3V, I

COM

to V+, (See Figure 4, Note 13)

= 100mA, V

NO

1.1

-

ON

Full

25

1.6

0.35

0.4

r

Flatness, r

FLAT(ON)

V+ = 3V, I

COM

to V+, (Notes 12, 13)

= 100mA, V

NO

0.33

-

ON

Full

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 2.7V, V

or V

= 1.5V, R = 50Ω,

25

Full

25

-

29

35

12

17

32

80

-

ns

pC

dB

ON

NO

NC

L

C = 35pF (See Figure 1, Note 13)

L

Turn-OFF Time, t

V+ = 2.7V, V

NO

L

or V

= 1.5V, R = 50Ω,

L

OFF

NC

C = 35pF (See Figure 1, Note 13)

Full

Charge Injection, Q

OFF Isolation

V

= 0V, R = 0Ω,C = 1.0nF (See Figure 2) 25

G G L

R = 50Ω, C = 5pF, f = 100kHz,

V

25

L

= 1V

(See Figure 3)

COM

RMS

NO or NC OFF Capacitance, f = 1MHz, V

NO

or V

= V

= 0V

-

16

48

-

pF

NC

COM

C

(See Figure 5)

OFF

COM ON Capacitance,

f = 1MHz, V

or V

= V

NO

(See Figure 5)

NC

COM

C

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.5

-

V

INL

Input Voltage High, V

1.4

-0.1

INH

, I

Input Current, I

V+ = 3.6V, V = 0V or V+

IN

0.1

µA

INH INL

FN6459.3

October 19, 2009

4

ISL54051, ISL54052

Electrical Specifications - 1.8V SupplyTest Conditions: V+ = +1.8V, GND = 0V, V

= 1V, V = 0.4V (Note 4),

INL

Unless Otherwise Specified. Boldface limits apply over the operating tempera-

INH

ture range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 1.8V, I

COM

= 100mA, V

or

25

-

2.33

2.54

-

Ω

ON

NO

= 0V to V+ (See Figure 4, Note 13)

V

NC

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 1.8V, V

Full

-

or V

NC

= 1.5V, R = 50Ω,

25

Full

25

-

68

93

45

71

18

-

ns

pC

ON

NO

L

C = 35pF (See Figure 1, Note 13)

L

Turn-OFF Time, t

V+ = 1.8V, V

NO

L

or V = 1.5V, R = 50Ω,

NC L

OFF

C = 35pF (See Figure 1, Note 13)

Full

25

Charge Injection, Q

V

= V+/2, R = 0Ω, C = 1.0nF

G G L

(See Figure 2)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.4

-

V

INL

Input Voltage High, V

NOTES:

1

INH

9. V = input voltage to perform proper function.

IN

10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this

data sheet.

11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal

range.

13. Limits established by characterization and are not production tested.

FN6459.3

October 19, 2009

5

ISL54051, ISL54052

Test Circuits and Waveforms

V+

V

t < 20ns

r

t < 20ns

f

INH

C

LOGIC

INPUT

50%

V

INL

t

V

OFF

OUT

NO OR NC

IN

SWITCH

INPUT

COM

SWITCH

INPUT

V

NX

0V

V

OUT

90%

R

50Ω

C

L

35pF

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Repeat test for all switches. C includes fixture and stray

L

Logic input waveform is inverted for switches that have the

opposite logic sense.

capacitance.

R

L

----------------------------

V

= V

OUT

(NO or NC)

R

+ r

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

V

R

OUT

G

COM

SWITCH

OUTPUT

NO OR NC

ΔV

OUT

V

OUT

V

INH

V

GND

IN

G

ON

C

L

ON

LOGIC

INPUT

OFF

V

INL

LOGIC

INPUT

Q = ΔV

x C

L

OUT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

FIGURE 2B. TEST CIRCUIT

V+

C

r

= V /100mA

1

ON

SIGNAL

GENERATOR

NO or NC

V

NX

100mA

IN

0V OR V+

V

OR V

INH

INL

IN

V

1

COM

ANALYZER

GND

R

L

FIGURE 3. OFF ISOLATION TEST CIRCUIT

FIGURE 4. r TEST CIRCUIT

ON

FN6459.3

October 19, 2009

6

ISL54051, ISL54052

Test Circuits and Waveforms(Continued)

V+

C

V

NO OR NC

OR V

INH

IN

INL

IMPEDANCE

ANALYZER

COM

GND

FIGURE 5. CAPACITANCE TEST CIRCUIT

protecting the switch. These schottky diodes must be

sized to handle the expected fault current.

Detailed Description

The ISL54051 and ISL54052 are bidirectional, single

pole/single throw (SPST) analog switches. They offer

precise switching capability from a single 1.8V to 5.5V

supply with low ON-resistance and high speed operation.

With a single supply of 5V the typical ON-resistance is

only 0.8Ω, with a typical turn-on and turn-off time

OPTIONAL

SCHOTTKY

DIODE

V+

OPTIONAL

PROTECTION

of: t

= 24ns, t = 10ns. The devices are especially

RESISTOR

IN

V

ON

OFF

X

well suited for portable battery powered equipment due

to their low operating supply voltage (1.8V), low power

consumption (5.5µW), low leakage currents (300nA

max) and tiny µTDFN and SOT-23 packages.

V

NX

COM

GND

The ISL54051 is a single normally open (NO) SPST

analog switch. The ISL54052 is a single normally closed

(NC) SPST analog switch.

OPTIONAL

SCHOTTKY

DIODE

FIGURE 6. OVERVOLTAGE PROTECTION

Supply Sequencing and Overvoltage

Protection

Power-Supply Considerations

With any CMOS device, proper power supply sequencing

is required to protect the device from excessive input

currents, which might permanently damage the IC. All

I/O pins contain ESD protection diodes from the pin to

V+ and to GND (see Figure 6). To prevent forward

biasing these diodes, V+ must be applied before any

input signals, and the input signal voltages must remain

between V+ and GND. If these conditions cannot be

guaranteed, then one of the following two protection

methods should be employed.

The constuction of the ISL54051 and the ISL54052 is

typical of most single supply CMOS analog switches in

that they have two supply pins: V+ and GND. V+ and

GND drive the internal CMOS switches and set their

analog voltage limits. Unlike switches with a 4.5V

maximum supply voltage, the ISL54051 and the

ISL54052’s 5.5V maximum supply voltage provides

plenty of room for the 10% tolerance of 4.3V supplies, as

well as room for overshoot and noise spikes.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 6). The

resistor limits the input current below the threshold that

produces permanent damage, and the sub-microamp

input current produces an insignificant voltage drop

during normal operation.

The minimum recommended supply voltage is 1.8V but

the part will operate with a supply below 1.8V. It is

important to note that the input signal range, switching

times, and ON-resistance degrade at lower supply

voltages. Refer to the “Electrical Specifications” tables

starting on page 3 and “Typical Performance Curves”

starting on page 8 for details.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low rON switch. Connecting schottky

diodes to the signal pins (as shown in Figure 6) will shunt

the fault current to the supply or to ground thereby

V+ and GND also power the internal logic and level

shiftier. The level shiftier converts the input logic levels to

switched V+ and GND signals to drive the analog switch

gate terminals.

FN6459.3

October 19, 2009

7

ISL54051, ISL54052

This family of switches cannot be operated with bipolar

supplies because the input switching point becomes

negative in this configuration.

systems, decreasing approximately 20dB per decade as

frequency increases. Higher load impedances decrease

off isolation and crosstalk rejection due to the voltage

divider action of the switch OFF impedance and the load

impedance.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and

1.4V) over a supply range of 2V to 5V (see Figure 13). At

Leakage Considerations

5V the V level is about 1.2V. This is still below the 1.8V

CMOS guaranteed high output minimum level of 1.4V,

but noise margin is reduced.

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND.

One of these diodes conducts if any analog signal

exceeds V+ or GND.

IH

The digital input stages draw supply current whenever

the digital input voltage is not at one of the supply rails.

Driving the digital input signals from GND to V+ with a

fast transition time minimizes power dissipation.

Virtually all the analog leakage current comes from the

ESD diodes to V+ or GND. Although the ESD diodes on a

given signal pin are identical and therefore fairly well

balanced, they are reverse biased differently. Each is

biased by either V+ or GND and the analog signal. This

means their leakages will vary as the signal varies. The

difference in the two diode leakages to the V+ and GND

pins constitutes the analog-signal-path leakage current.

All analog leakage current flows between each pin and

one of the supply terminals, not to the other switch

terminal. This is why both sides of a given switch can

show leakage currents of the same or opposite polarity.

There is no connection between the analog signal paths

and V+ or GND.

High-Frequency Performance

In 50Ω systems, the ISL54051 and the ISL54052 have a

-3dB bandwidth of 190MHz (see Figure 14). The

frequency response is very consistent over a wide V+

range, and for varying analog signal levels.

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off

isolation is the resistance to this feedthrough. Figure 15

details the high off isolation rejection provided by this

family. At 100kHz, off isolation is about 80dB in 50Ω

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

2.5

1.0

I

= 100mA

COM

V+ = 1.8V

0.9

0.8

0.7

0.6

0.5

0.4

2.0

1.5

+85°C

+25°C

V+ = 2.7V

1.0

0.5

0

V+ = 4.5V

V+ = 3V

V+ = 5V

-40°C

0.3

0.2

V+ = 5V

I

= 100mA

COM

0

1

2

3

4

5

0

1

2

3

4

5

V

(V)

V

(V)

COM

FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE

FN6459.3

October 19, 2009

8

ISL54051, ISL54052

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

3.0

2.5

2.0

1.5

1.0

0.5

1.5

V+ = 1.8V

= 10mA

I

COM

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

+85°C

+25°C

-40°C

+85°C

+25°C

-40°C

1.5

V+ = 3.0V

= 100mA

0.6

0.5

I

COM

0

0.5

1.0

(V)

1.5

1.8

0

0.5

1.0

2.0

2.5

3.0

V

COM

V

(V)

COM

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE

80

100

90

-40°C

80

70

60

50

40

30

20

10

0

60

-40°C

+25°C

40

+85°C

+25°C

20

0

+85°C

-40°C

2.8

3.8

4.8

1.8

2.8

3.8

4.8

V+ (V)

FIGURE 11. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 12. TURN-OFF TIME vs SUPPLY VOLTAGE

1.6

1.4

1.2

GAIN

0

-1

-2

-3

V

INH

1.0

0.8

V

INL

0.6

0.4

0.2

V+ = 5.0V

R

= 50Ω

L

IN

V

= 0.2V

to 2V

P-P P-P

2.0

2.5

3.0

3.5

4.0

V+ (V)

4.5

5.0

5.5

0.01k

0.1k

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY

VOLTAGE

FIGURE 14. FREQUENCY RESPONSE

FN6459.3

October 19, 2009

9

ISL54051, ISL54052

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0

40

V+ = 1.8V to 5.5V

V+ = 3.0V

30

-20

20

10

-40

-60

-40

0

ISOLATION

-10

-20

-30

-40

-50

-60

V+ = 5V

V+ = 1.8V

-80

V+ = 3.0V

-100

-120

-100

-120

0

1

2

3

4

5

1k

10k

100k

1M

10M

100M 500M

V

(V)

FREQUENCY (Hz)

COM

FIGURE 15. OFF ISOLATION

FIGURE 16. CHARGE INJECTION vs SWITCH

VOLTAGE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

57

PROCESS:

Submicron CMOS

FN6459.3

October 19, 2009

10

ISL54051, ISL54052

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

L6.1.2x1.0A

A

E

B

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

PIN 1

REFERENCE

D

SYMBOL

MIN

0.45

-

NOMINAL

MAX

0.55

0.05

NOTES

2X

0.10 C

A

A1

A3

b

0.50

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

0.95

1.15

0.20

0.25

1.05

1.25

5

DETAIL A

0.10 C

0.08 C

D

1.00

-

A

E

1.20

-

7X

e

0.40 BSC

-

C

A1 A3

L

0.30

0.40

0.35

0.40

0.50

-

SEATING

PLANE

SIDE VIEW

L1

N

0.45

-

4X

e

DETAIL B

6

3

-

2

5X

L

Ne

θ

3

1

3

0

12

4

L1

Rev. 2 8/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

6

4

b 6X

0.10 C A B

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

0.05 C

NOTE 3

BOTTOM VIEW

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

0.1x45°

CHAMFER

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

A3

A1

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

DETAIL A

DETAIL B PIN 1 LEAD

1.00

1.40

0.20

0.30

0.35

0.45

0.20

0.40

10

LAND PATTERN

FN6459.3

October 19, 2009

11

ISL54051, ISL54052

SOT-23 Package Family

MDP0038

e1

D

SOT-23 PACKAGE FAMILY

A

MILLIMETERS

SOT23-5

6

4

N

SYMBOL

SOT23-6

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

6

TOLERANCE

MAX

A

A1

A2

b

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

5

±0.05

E1

E

±0.15

2

3

±0.05

0.15

2X

C

D

c

±0.06

1

2

3

0.20

2X

C

D

Basic

5

e

E

Basic

E1

e

Basic

0.20

C

A-B

D

M

B

b

NX

Basic

e1

L

Basic

±0.10

L1

N

Reference

Rev. F 2/07

0.15

2X

C

A-B

1

3

D

NOTES:

C

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

A2

SEATING

PLANE

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

A1

0.10

NX

C

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).

(L1)

H

A

GAUGE

PLANE

0.25

c

+3°

-0°

L

0°

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6459.3

October 19, 2009

12


型号：	ISL54051IHZ-T
厂家：	Intersil
描述：	Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST Analog Switches 超低导通电阻，低电压，单电源，单路SPST模拟开关开关光电二极管
文件：	总12页 (文件大小：397K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54051IHZ-T [INTERSIL]

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