ISL22323UFR16Z [INTERSIL]
Dual Digitally Controlled Potentiometer XDCP; 双路数字电位XDCP型号: | ISL22323UFR16Z |
厂家: | Intersil |
描述: | Dual Digitally Controlled Potentiometer XDCP |
文件: | 总18页 (文件大小:697K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL22323
®
Dual Digitally Controlled Potentiometer (XDCP™)
Data Sheet
March 13, 2008
FN6422.1
2 ®
Low Noise, Low Power, I C Bus,
256 Taps
Features
• Two potentiometers in one package
• 256 resistor taps
The ISL22323 integrates two digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
2
• I C serial interface
- Three address pins, up to eight devices per bus
• Non-volatile EEPROM storage of wiper position
• 13 General Purpose non-volatile registers
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2
I C bus interface. The potentiometer has an associated
• High reliability
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
corresponding wiper. At power up the device recalls the
contents of the DCP’s IVRi to the correspondent WRi.
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55°C
• Wiper resistance: 70Ω typical @ 1mA
• Standby current <4µA max
• Shut-down current <4µA max
• Dual power supply
The ISL22323 also has 13 general purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
- V
CC
- V- = -2.25V to -5.5V
= 2.25V to 5.5V
The ISL22323 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40 to +125°C
• 14 Ld TSSOP or 16 Ld QFN
Each DCP can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Pb-free (RoHS compliant)
Ordering Information
RESISTANCE
TEMPERATURE
PART NUMBER
(Notes 1, 2)
OPTION
(kΩ)
RANGE
(°C)
PACKAGE
(Pb-Free)
PART MARKING
22323 TFVZ
PKG. DWG. #
M14.173
ISL22323TFV14Z
ISL22323TFR16Z
ISL22323UFV14Z
ISL22323UFR16Z
ISL22323WFV14Z
ISL22323WFR16Z
NOTES:
100
100
50
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
14 Ld TSSOP
223 23TFRZ
16 Ld QFN
L16.4x4A
M14.173
L16.4x4A
M14.173
L16.4x4A
22323 UFVZ
223 23UFRZ
22323 WFVZ
223 23WFRZ
14 Ld TSSOP
16 Ld QFN
50
10
14 Ld TSSOP
16 Ld QFN
10
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22323
Block Diagram
RH0
RH1
V-
VCC
SCL
POWER UP
SDA
A2
INTERFACE,
CONTROL
AND
STATUS
LOGIC
2
I C
INTERFACE
WR0
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
A1
A0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
NON-VOLATILE
REGISTERS
RW0
RL0
RW1
RL1
GND
Pinouts
ISL22323
ISL22323
(14 LD TSSOP)
(16 LD QFN)
TOP VIEW
TOP VIEW
RH0
RL0
RW0
RH1
RL1
RW1
A2
1
2
3
4
5
6
7
14
VCC
A0
16 15 14 13
13
12
11
10
9
1
2
3
4
12
RL0
A1
A2
NC
NC
V-
GND
SCL
SDA
V-
11
10
9
RH0
VCC
A0
8
5
6
7
8
FN6422.1
March 13, 2008
2
ISL22323
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
RH0
RL0
RW0
RH1
RL1
RW1
A2
DESCRIPTION
1
2
11
12
13
14
15
16
1
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
“High” terminal of DCP1
“Low” terminal of DCP1
“Wiper” terminal of DCP1
3
4
5
6
2
7
Device address input for the I C interface
8
4
V-
Negative power supply pin
2
9
5
SDA
SCL
GND
A1
Open drain Serial data I/O for the I C interface
2
10
11
12
13
14
6
I C interface clock input
7
Device ground pin
2
8
Device address input for the I C interface
2
9
A0
Device address input for the I C interface
10
2, 3
EPAD*
VCC
NC
Positive power supply pin
No connection
Exposed Die Pad internally connected to V-
NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
FN6422.1
March 13, 2008
3
ISL22323
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
θ
(°C/W)
JC
JA
14 Lead TSSOP. . . . . . . . . . . . . . . . . .
16 Lead QFN (Note 4) . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
105
39
N/A
3.0
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP Pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V
CC
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Recommended Operating Conditions
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C
Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
ESD
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Analog Specifications Over recommended operating conditions unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
RHi to RLi Resistance
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
kΩ
R
W option
U option
T option
10
50
TOTAL
kΩ
100
kΩ
RHi to RLi Resistance Tolerance
-20
V-
+20
%
End-to-End Temperature Coefficient
W option
±85
±45
ppm/°C
ppm/°C
V
U, T option
V
, V
RHi RLi
DCP Terminal Voltage
Wiper Resistance
V
and V to GND
RL
V
RH
CC
R
RH - floating, V = V-, force Iw current to
RL
the wiper, I = (V
70
10/10/25
0.1
250
Ω
W
- V )/R
W
CC
RL TOTAL
C /C /C
W
(Note 19)
Potentiometer Capacitance
Leakage on DCP Pins
See Macro Model below.
pF
µA
H
L
I
Voltage at pin from V- to V
@ RHi; measured at RWi, unloaded)
W option
1
LkgDCP
CC
VOLTAGE DIVIDER MODE (V- @ RLi; V
CC
INL
Integral Non-linearity
-1.5
-1.0
-1.0
-0.5
±0.5
±0.2
1.5
1.0
1.0
0.5
LSB
(Note 6)
(Note 10)
Monotonic Over All Tap Positions
U, T option
W option
LSB
(Note 6)
DNL
Differential Non-linearity
Monotonic Over All Tap Positions
±0.4
LSB
(Note 6)
(Note 9)
U, T option
±0.15
LSB
(Note 6)
ZSerror
(Note 7)
Zero-scale Error
W option
0
0
1
0.5
-1
5
2
0
0
2
LSB
(Note 6)
U, T option
W option
FSerror
(Note 8)
Full-scale Error
-5
-2
-2
LSB
(Note 6)
U, T option
-1
V
DCP-to-DCP Matching
Wipers at the same tap position, the same
voltage at all RH terminals and the same
voltage at all RL terminals
LSB
(Note 6)
MATCH
(Note 11, 19)
FN6422.1
March 13, 2008
4
ISL22323
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
DCP register set to 80 hex
(Note 21) (Note 5) (Note 21)
UNIT
TC (Note 12, Ratiometric Temperature Coefficient
V
±4
ppm/°C
19)
f
-3dB Cut Off Frequency
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
Wiper at midpoint (80hex) T option (100k)
1000
250
kHz
kHz
kHz
cutoff
(Note 19)
120
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected)
RINL
(Note 16)
Integral Non-linearity
Differential Non-linearity
Offset
W option
-3
±1.5
±0.4
±0.5
±0.15
1
3
MI
(Note 13)
U, T option
W option
-1
1
MI
(Note 13)
RDNL
(Note 15)
-1.5
-0.5
0
1.5
0.5
5
MI
(Note 13)
U, T option
W option
MI
(Note 13)
Roffset
MI
(Note 14)
(Note 13)
U, T option
0
0.5
2
MI
(Note 13)
R
DCP-to-DCP Matching
Wipers at the same tap position with the
same terminal voltages
-2
2
MI
(Note 13)
MATCH
(Note 17)
TC
Resistance Temperature Coefficient
DCP register set between 32hex and FF hex
±40
ppm/°C
R
(Notes 18, 19)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
2
I
V
Supply Current (Volatile
V
= 5.5V, f = 400kHz; (for I C Active,
SCL
0.01
0.005
-0.05
0.2
mA
CC1
CC
CC
Write/Read)
Read and Volatile Write states only)
2
V
= 2.25V, f
= 400kHz; (for I C Active,
SCL
0.1
mA
mA
CC
Read and Volatile Write states only)
I
V- Supply Current (Volatile
Write/Read)
V- = -5.5V, V = 5.5V, f = 400kHz; (for
I C Active, Read and Volatile Write states
-0.2
-0.1
V-1
CC
SCL
2
only)
V- = -2.25V, V
= 2.25V, f
SCL
= 400kHz;
(for I C Active, Read and Volatile Write
states only)
-0.02
1.0
mA
mA
mA
mA
mA
CC
2
I
V
Supply Current (Non-volatile
V = 5.5V, V- = 5.5V, f
CC SCL
= 400kHz; (for
I C Active, Read and Non-volatile Write
states only)
2.0
1.0
CC2
CC
2
Write/Read)
V
= 2.25V, V- = -2.25V, f
SCL
= 400kHz;
0.3
CC
2
(for I C Active, Read and Non-volatile Write
states only)
I
V- Supply Current (Non-volatile
Write/Read)
V- = -5.5V, V
= 5.5V, f
CC SCL
= 400kHz; (for
I C Active, Read and Non-volatile Write
states only)
-2.0
-1.0
-1.2
-0.4
V-2
2
V- Supply Current (Non-volatile
Write/Read)
V- = -2.25V, V
= 2.25V, f = 400kHz;
SCL
(for I C Active, Read and Non-volatile Write
CC
2
states only)
FN6422.1
March 13, 2008
5
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
= +5.5V, V- = -5.5V @ +85°C, I C
(Note 21) (Note 5) (Note 21)
UNIT
2
I
V
Current (Standby)
V
0.5
1.0
2.0
4.0
1.0
2.0
µA
SB
CC
CC
interface in standby state
2
V
= +5.5V, V- = -5.5V @ +125°C, I C
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC
interface in standby state
2
V
= +2.25V, V- = -2.25V @ +85°C, I C
0.2
CC
interface in standby state
2
V
= +2.25V, V- = -2.25V @ +125°C, I C
0.5
CC
interface in standby state
2
I
V- Current (Standby)
V- = -5.5V, V = +5.5V @ +85°C, I C
-3.0
-5.0
-2.0
-3.0
-0.7
-1.5
-0.3
-0.4
0.5
V-SB
CC
interface in standby state
2
V- = -5.5V, V
= +5.5V @ +125°C, I C
CC
interface in standby state
2
V- = -2.25V, V = +2.25V @ +85°C, I C
CC
interface in standby state
2
V- = -2.25V, V = +2.25V @ +125°C, I C
CC
interface in standby state
2
I
V
Current (Shut-down)
V
= +5.5V, V- = -5.5V @ +85°C, I C
2.0
4.0
1.0
2.0
SD
CC
CC
interface in standby state
2
V
= +5.5V, V- = -5.5V @ +125°C, I C
1.0
CC
interface in standby state
2
V
= +2.25V, V- = -2.25V @ +85°C, I C
0.2
CC
interface in standby state
2
V
= +2.25V, V- = -2.25V @ +125°C, I C
0.5
CC
interface in standby state
2
I
V- Current (Standby)
V- = -5.5V, V = +5.5V @ +85°C, I C
-3.0
-5.0
-2.0
-3.0
-1
-0.7
-1.5
-0.3
-0.4
V-SB
CC
interface in standby state
2
V- = -5.5V, V
= +5.5V @ +125°C, I C
CC
interface in standby state
2
V- = -2.25V, V = +2.25V @ +85°C, I C
CC
interface in standby state
2
V- = -2.25V, V = +2.25V @ +125°C, I C
CC
interface in standby state
I
Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to V
SDA, and SCL
1
LkgDig
CC
t
DCP Wiper Response Time
SCL falling edge of last bit of DCP data byte
to wiper new position
1.5
1.5
WRT
(Note 19)
t
DCP Recall Time from Shut-down
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
µs
ShdnRec
(Note 19) Mode
Vpor
Power-on Recall Voltage
Ramp Rate
Minimum V
at which memory recall occurs
1.9
0.2
2.1
5
V
CC
VCCRamp
V
V/ms
ms
CC
t
Power-up Delay
V
above Vpor, to DCP Initial Value
CC
D
2
Register recall completed, and I C Interface
in standby state
FN6422.1
March 13, 2008
6
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
EEPROM SPECIFICATION
EEPROM Endurance
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T ≤ +55°C
t
Non-volatile Write Cycle Time
12
20
WC
(Note 20)
SERIAL INTERFACE SPECS
V
A0, A1, A2, SDA, and SCL Input
Buffer LOW Voltage
0.3*V
V
V
IL
CC
V
A0, A1, A2, SDA, and SCL Input
Buffer HIGH Voltage
0.7*V
CC
IH
Hysteresis SDA and SCL Input Buffer Hysteresis
(Note 19)
0.05*V
0
V
CC
V
SDA Output Buffer LOW Voltage,
0.4
10
V
OL
(Note 19) Sinking 4mA
Cpin
A0, A1, A2, SDA, and SCL Pin
pF
(Note 19) Capacitance
f
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
400
50
kHz
ns
SCL
t
sp
and SCL Inputs suppressed
t
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V , until
CC
900
ns
ns
AA
(Note 19) Valid
SDA exits the 30% to 70% of V
window
CC
t
Time the Bus Must be Free Before The SDA crossing 70% of V
during a STOP
1300
BUF
(Note 19) Start of a New Transmission
CC
condition, to SDA crossing 70% of V
CC
during the following START condition
t
Clock LOW Time
Measured at the 30% of V
Measured at the 70% of V
crossing
crossing
1300
600
ns
ns
ns
LOW
CC
t
Clock HIGH Time
HIGH
CC
t
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of V
600
SU:STA
HD:STA
SU:DAT
CC
From SDA falling edge crossing 30% of V
t
t
START Condition Hold Time
Input Data Setup Time
600
100
ns
ns
CC
to SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
t
Input Data Hold Time
From SCL rising edge crossing 70% of V
0
ns
HD:DAT
CC
to SDA entering the 30% to 70% of V
window
CC
t
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
,
600
1300
0
ns
ns
ns
SU:STO
CC
CC
t
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
HD:STO
or Volatile Only Write
Output Data Hold Time
both crossing 70% of V
CC
t
From SCL falling edge crossing 30% of V
,
DH
(Note 19)
CC
CC
until SDA enters the 30% to 70% of V
window
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
20 +
0.1*Cb
250
250
ns
ns
R
CC
(Note 19)
t
From 70% to 30% of V
20 +
F
CC
(Note 19)
0.1*Cb
FN6422.1
March 13, 2008
7
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
Total on-chip and off-chip
(Note 21) (Note 5) (Note 21)
UNIT
Cb
(Note 19)
Capacitive Loading of SDA or SCL
10
1
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Maximum is determined by t and t
kΩ
R
F
(Note 19) Off-chip
For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ
For Cb = 40pF, max is about 15kΩ ~ 20kΩ
t
A0, A1, and A2 Setup Time
A0, A1, and A2 Hold Time
Before START condition
After STOP condition
600
600
ns
ns
SU:A
t
HD:A
NOTES:
5. Typical values are for T = +25°C and 3.3V supply voltage.
A
6. LSB: [V(R
)
– V(R ) ]/255. V(R
)
and V(R ) are V(R ) for the DCP register set to FF hex and 00 hex respectively. LSB is the
W 0
W 255
W 0 W 255
W
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW) /LSB.
0
8. FS error = [V(RW)
255
– V ]/LSB.
CC
9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
10. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255
i
0
11. V
12.
= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
MATCH
Max(V(RW) ) – Min(V(RW) )
6
10
i
i
for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
--------------------------------------------------------------------------------------------- ----------------
TC
=
×
V
+
i
i
13. MI = |RW
– RW |/255. MI is a minimum increment. RW
and RW are the measured resistances for the DCP register set to FF hex and 00
255 0
255
hex respectively.
0
14. R
= RW /MI, when measuring between RW and RL.
OFFSET
0
R
= RW
/MI, when measuring between RW and RH.
OFFSET
255
15. RDNL = (RW – RW )/MI -1, for i = 16 to 255.
i-1
i
16. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.
i
0
17. R
18.
= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
6
MATCH
for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
the minimum value of the resistance over the temperature range.
[Max(Ri) – Min(Ri)]
10
--------------------------------------------------------------- ----------------
TC
=
×
R
165°C
[Max(Ri) + Min(Ri)] ⁄ 2
+
19. This parameter is not 100% tested.
2
20. t
is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-volatile
WC
write cycle.
21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
FN6422.1
March 13, 2008
8
ISL22323
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
10pF
10pF
25pF
RW
SDA vs SCL Timing
t
sp
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
BUF
AA
DH
SDA
(OUTPUT TIMING)
A0, A1 and A2 Pin Timing
STOP
START
SCL
CLK 1
SDA
t
t
HD:A
SU:A
A0, A1, A2
Typical Performance Curves
80
2.0
1.5
1.0
0.5
0
T = +125°C
70
60
50
40
30
20
10
0
T = +25°C
I
CC
-0.5
-1.0
-1.5
-2.0
I
V-
T = -40°C
0
50
100
150
200
250
-40
0
40
TEMPERATURE (°C)
80
120
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY I
CC
and I vs TEMPERATURE
V-
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10kΩ (W)
CC TOTAL
FN6422.1
March 13, 2008
9
ISL22323
Typical Performance Curves (Continued)
0.50
0.50
0.25
0
V
= 5.5V
CC
T = +25°C
T = +25°C
V
= 2.25V
CC
0.25
0
-0.25
-0.50
-0.25
-0.50
V
= 5.5V
V
= 2.25V
100
CC
100
TAP POSITION (DECIMAL)
CC
0
50
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
MODE FOR 10kΩ (W)
2.0
0
10k
1.6
1.2
-1
V
= 2.25V
CC
50k
V
= 5.5V
CC
-2
-3
-4
0.8
50k
10k
V
= 2.25V
V
= 5.5V
CC
CC
0.4
0
-5
-40
0
40
80
120
-40
0
40
TEMPERATURE (ºC)
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FIGURE 5. ZS ERROR vs TEMPERATURE
2.0
0.5
0.25
0
T = +25°C
T = +25°C
1.5
1.0
V
= 5.5V
CC
V
= 2.25V
CC
0.5
0
-0.25
-0.50
V
= 2.25V
100
CC
V
= 5.5V
CC
-0.5
0
50
100
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
10kΩ (W)
10kΩ (W)
FN6422.1
March 13, 2008
10
ISL22323
Typical Performance Curves (Continued)
200
160
120
80
1.60
10k
1.20
10k
0.80
5.5V
0.40
0.00
50k
40
50k
2.25V
0
-0.40
16
66
116
166
216
266
-40
0
40
80
120
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
500
400
300
INPUT
OUTPUT
10k
200
100
50k
WIPER AT MID POINT (POSITION 80h)
R
= 10kΩ
TOTAL
0
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (1MHz)
CS
SCL
WIPER UNLOADED,
WIPER
MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
FN6422.1
March 13, 2008
11
ISL22323
loaded into the corresponding WRi to set the wipers to their
initial positions.
Pin Description
Potentiometers Pins
RHI AND RLi
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi)
is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper
terminal (RWi) is closest to its “High” terminal (RHi). As the
value of the WRi increases from all zeroes (0) to all ones
(255 decimal), the wiper moves monotonically from the
position closest to RLi to the position closest to RHi. At the
same time, the resistance between RWi and RLi increases
monotonically, while the resistance between RHi and RWi
decreases monotonically.
The high (RHi) and low (RLi) terminals of the ISL22323 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
RWi
RWi is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
2
The SDA is a bidirectional serial data input/output pin for I C
interface. It receives device address, operation code, wiper
2
address and data from an I C external master device at the
While the ISL22323 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WRi will be reloaded with the value stored in
corresponding non-volatile Initial Value Register (IVRi).
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
2
This input is the serial clock of the I C serial interface. SCL
The WRi and IVRi can be read or written to directly using the
I C serial interface as described in the following sections.
2
requires an external pull-up resistor.
DEVICE ADDRESS (A2, A1, A0)
Memory Description
The address inputs are used to set the least significant 3 bits
of the 7-bit I C interface slave address. A match in the slave
The ISL22323 contains two non-volatile 8-bit Initial Value
Register (IVRi), thirteen General Purpose non-volatile 8-bit
registers and three volatile 8-bit registers: two Wiper Registers
(WRi) and Access Control Register (ACR). Memory map of
ISL22323 is in Table 1. The non-volatile registers (IVRi) at
address 0 and 1, contain initial wiper position and volatile
registers (WRi) contain current wiper position.
2
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22323. A maximum of eight ISL22323 devices may
2
occupy the I C serial bus (See Table 3).
Principles of Operation
TABLE 1. MEMORY MAP
The ISL22323 is an integrated circuit incorporating two
DCPs with its associated registers, non-volatile memory and
an I C serial interface providing direct communication
between a host and the potentiometer and memory. The
resistor arrays are comprised of individual resistors
connected in a series. At either end of the array and
between each resistor is an electronic switch that transfers
the potential at that point to the wiper.
ADDRESS
(hex)
10
F
NON-VOLATILE
VOLATILE
2
N/A
ACR
Reserved
E
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
N/A
N/A
N/A
N/A
N/A
N/A
N/A
D
C
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
B
A
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
9
8
FN6422.1
March 13, 2008
12
ISL22323
TABLE 1. MEMORY MAP (Continued)
transmit and receive operations. Therefore, the ISL22323
operates as a slave device in all applications.
ADDRESS
(hex)
NON-VOLATILE
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
IVR1
VOLATILE
2
All communication over the I C interface is conducted by
7
6
5
4
3
2
1
0
N/A
N/A
sending the MSB of each byte of data first.
Protocol Conventions
N/A
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22323, the SDA pin is in
the input mode.
N/A
N/A
N/A
WR1
WR0
2
All I C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22323 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
IVR0
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
2
All I C interface operations must be terminated by a STOP
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
0
NAME
VOL
SHDN WIP
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shut-down mode.
When this bit is 0, DCPs are in Shut-down mode. Default value
of the SHDN bit is 1.
The ISL22323 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22323 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
RHi
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1 and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation and “0” for a Write
operation (See Table 3).
RWi
RLi
FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE
TABLE 3. IDENTIFICATION BYTE FORMAT
The WIP bit (ACR[5]) is a read-only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
2
1
0
1
0
A2
A1
A0
R/W
I C Serial Interface
(MSB)
(LSB)
2
The ISL22323 supports an I C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
FN6422.1
March 13, 2008
13
ISL22323
SCL
SDA
START
DATA
STABLE
DATA
CHANGE STABLE
DATA
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
SIGNALS FROM
THE MASTER
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT SDA
1 0 1 0 A2A1A0 0
0 0 0 0
SIGNALS FROM
THE SLAVE
A
C
K
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
ADDRESS
BYTE
SIGNAL AT SDA
1 0 1 0 A2A1A0 0
0 0 0 0
1 0
1
A2A1A0 1
0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
FN6422.1
March 13, 2008
14
ISL22323
Write Operation
Applications Information
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22323 responds with an ACK. At this time, the device
enters its standby state (See Figure 18).
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients (or overshoot/undershoot) resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note that all switching transients will
settle well within the settling time as stated on the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus this may not
be a good solution for some applications. It may be a good
idea, in that case, to use fast amplifiers in a signal chain for
fast recovery.
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22323 responds with an ACK. Then the ISL22323
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The Data Bytes are from the registers indicated by an
internal pointer. This pointers initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 0Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.The master terminates the read
Application Example
Figure 20 shows an example of using ISL22323 for gain
setting and offset correction in high side current
measurement application. DCP0 applies a programmable
offset voltage of ±25mV to the FB+ pin of the Instrumentation
Amplifier EL8173 to adjust output offset to zero voltages.
DCP1 programs the gain of the EL8173 from 90 to 110 with
5V output for 10A current through current sense resistor.
More application examples can be found at:
http://www.intersil.com/data/an/AN1145.pdf
operation issuing a NACK (ACK) and a STOP condition
following the last bit of the last Data Byte (See Figure 19).
FN6422.1
March 13, 2008
15
ISL22323
1.2V
DC/DC CONVERTER
OUTPUT
PROCESSOR LOAD
10A, MAX
0.005Ω
+5V
10k
10k
0.1µF
8
EL8173IS
1
V +
S
3
2
7
5
IN+
IN-
EN
6
V
V
= 0V TO +5V to ADC
OUT
OUT
FB+
+5V
R
4
FB-
V -
S
150k, 1%
R
1
4
50k, 1%
RH1
RL1
RH0
RW1
R
5
309, 1%
R
2
1k, 1%
RW0
RL0
50k
50k
DCP0 (1/2 ISL22323U)
PROGRAMMABLE OFFSET ±25mV
DCP1 (1/2 ISL22323U)
PROGRAMMABLE GAIN 90 TO 110
R
6
R
3
1.37k, 1%
50k, 1%
-5V
ISL22323UFV14Z
14
1
2
3
+5V
I C BUS
VCC
RH0
RL0
RW0
DCP0
DCP1
10
9
7
12
13
2
SCL
SDA
A2
A1
A0
4
5
6
RH1
RL1
RW1
11
8
GND
-5V
V-
FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
FN6422.1
March 13, 2008
16
ISL22323
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGD-10)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
2.30
2.30
0.25
0.30
2.55
2.55
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.40
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.40
7, 8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 2 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present.
L minus L1 to be equal to or greater than 0.3mm.
FN6422.1
March 13, 2008
17
ISL22323
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M14.173
INDEX
AREA
0.25(0.010)
M
B M
E
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
1
2
3
A
A1
A2
b
-
-
L
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
D
9
c
-
-C-
α
D
3
A2
e
A1
E1
e
4
c
b
0.10(0.004)
0.026 BSC
0.65 BSC
-
0.10(0.004) M
C
A M B S
E
0.246
0.256
6.25
0.45
6.50
0.75
-
L
0.0177
0.0295
6
NOTES:
N
14
14
7
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
o
o
o
o
0
8
0
8
-
α
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6422.1
March 13, 2008
18
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