ISL22323UFV14Z_技术文档

NOT RECOMMENDED FOR NEW DESIGNS

NO RECOMMENDED REPLACEMENT

contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

DATASHEET

ISL22323

Dual Digitally Controlled Potentiometer (XDCP)

Low Noise, Low Power, I C Bus, 256 Taps

FN6422

Rev.2.00

Aug 17, 2015

2

The ISL22323 integrates two digitally controlled

potentiometers (DCP), control logic and non-volatile memory

on a monolithic CMOS integrated circuit.

Features

• Two potentiometers in one package

• 256 resistor taps

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

2

• I C serial interface

- Three address pins, up to eight devices per bus

• Non-volatile EEPROM storage of wiper position

• 13 General Purpose non-volatile registers

2

I C bus interface. The potentiometer has an associated

volatile Wiper Register (WRi) and a non-volatile Initial Value

Register (IVRi) that can be directly written to and read by the

user. The contents of the WRi control the position of the

corresponding wiper. At power up the device recalls the

contents of the DCP’s IVRi to the correspondent WRi.

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T +55°C

The ISL22323 also has 13 general purpose non-volatile

registers that can be used as storage of lookup table for

multiple wiper position or any other valuable information.

• Wiper resistance: 70 typical @ 1mA

• Standby current <4µA max

• Shut-down current <4µA max

• Dual power supply

The ISL22323 features a dual supply, that is beneficial for

applications requiring a bipolar range for DCP terminals

between V- and VCC.

- V

CC

= 2.25V to 5.5V

- V- = -2.25V to -5.5V

Each DCP can be used as three-terminal potentiometers or

as two-terminal variable resistors in a wide variety of

applications including control, parameter adjustments, and

signal processing.

• 10k 50kor 100k total resistance

• Extended industrial temperature range: -40 to +125°C

• 14 Ld TSSOP or 16 Ld QFN

• Pb-free (RoHS compliant)

Block Diagram

RH0

RH1

V-

VCC

SCL

SDA

POWER UP

INTERFACE

CONTROL

AND

,

2

I C

A2

A1

WR0

WR1

INTERFACE

VOLATILE

REGISTER

AND

WIPER

CONTROL

CIRCUITRY

VOLATILE

REGISTER

AND

WIPER

CONTROL

CIRCUITRY

STATUS

LOGIC

A0

NON-VOLATILE

REGISTERS

RW0

RL0

RW1

RL1

GND

FN6422 Rev.2.00

Aug 17, 2015

Page 1 of 19

ISL22323

Ordering Information

RESISTANCE

OPTION

(k)

TEMPERATURE

RANGE

PART NUMBER

PACKAGE

(RoHS Compliant)

(Notes 1, 2)

ISL22323TFV14Z

ISL22323TFR16Z

PART MARKING

(°C)

PKG. DWG. #

M14.173

22323 TFVZ

223 23TFRZ

22323 UFVZ

100

50

-40 to +125

14 Ld TSSOP

16 Ld QFN

L16.4x4A

M14.173

ISL22323UFV14Z

(No longer available,

recommended

14 Ld TSSOP

replacement:

ISL22323TFV14Z-TK)

ISL22323UFR16Z

(No longer available,

recommended

replacement:

ISL22323TFV14Z-TK)

223 23UFRZ

22323 WFVZ

223 23WFRZ

50

10

-40 to +125

16 Ld QFN

14 Ld TSSOP

16 Ld QFN

L16.4x4A

M14.173

L16.4x4A

ISL22323WFV14Z

(No longer available,

recommended

replacement:

ISL22323TFV14Z-TK)

ISL22323WFR16Z

(No longer available,

recommended

replacement:

ISL22323TFV14Z-TK)

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte

tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

Pinouts

ISL22323

(14 LD TSSOP)

TOP VIEW

ISL22323

(16 LD QFN)

TOP VIEW

RH0

RL0

RW0

RH1

RL1

RW1

A2

1

2

3

4

5

6

7

14

VCC

A0

16 15 14 13

13

12

11

10

9

1

2

3

4

12

11

10

9

A1

A2

NC

V-

RL0

RH0

VCC

GND

SCL

SDA

V-

A0

8

5

6

7

8

FN6422 Rev.2.00

Aug 17, 2015

Page 2 of 19

ISL22323

Pin Descriptions

TSSOP PIN

QFN PIN

SYMBOL

RH0

RL0

RW0

RH1

RL1

RW1

A2

DESCRIPTION

1

2

11

12

13

14

15

16

1

“High” terminal of DCP0

“Low” terminal of DCP0

“Wiper” terminal of DCP0

“High” terminal of DCP1

“Low” terminal of DCP1

“Wiper” terminal of DCP1

3

4

5

6

2

7

Device address input for the I C interface

8

4

V-

Negative power supply pin

2

9

5

SDA

SCL

GND

A1

Open drain Serial data I/O for the I C interface

2

10

11

12

13

14

6

I C interface clock input

7

Device ground pin

2

8

Device address input for the I C interface

2

9

A0

Device address input for the I C interface

10

2, 3

EPAD*

VCC

NC

Positive power supply pin

No connection

Exposed Die Pad internally connected to V-

NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to

http://www.intersil.com/data/tb/TB389.pdf

FN6422 Rev.2.00

Aug 17, 2015

Page 3 of 19

ISL22323

Absolute Maximum Ratings

Thermal Information

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

Thermal Resistance (Typical, Note 3)



(°C/W)



(°C/W)

JC

JA

14 Lead TSSOP. . . . . . . . . . . . . . . . . .

16 Lead QFN (Note 4) . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

105

39

N/A

3.0

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V

CC

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Recommended Operating Conditions

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C

Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V

CC

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V

Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

3.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Analog Specifications Over recommended operating conditions unless otherwise stated.

MIN

TYP

MAX

SYMBOL

PARAMETER

RHi to RLi Resistance

TEST CONDITIONS

(Note 21) (Note 5) (Note 21)

UNIT

k

R

W option

U option

T option

10

50

TOTAL

k

100

k

RHi to RLi Resistance Tolerance

-20

V-

+20

%

End-to-End Temperature Coefficient

W option

±85

±45

ppm/°C

V

U, T option

V

, V

RHi RLi

DCP Terminal Voltage

Wiper Resistance

V

and V to GND

RL

V

RH

CC

R

RH - floating, V = V-, force Iw current to

RL

the wiper, I = (V

70

10/10/25

0.1

250



W

- V )/R

W

CC RL TOTAL

C /C /C

W

Potentiometer Capacitance

Leakage on DCP Pins

See Macro Model below.

pF

µA

H

L

(Note 19)

I

Voltage at pin from V- to V

1

LkgDCP

CC

VOLTAGE DIVIDER MODE (V- @ RLi; V

@ RHi; measured at RWi, unloaded)

W option

CC

INL

Integral Non-linearity

-1.5

-1.0

-0.5

±0.5

±0.2

1.5

1.0

0.5

LSB

(Note 6)

(Note 10)

Monotonic Over All Tap Positions

U, T option

W option

LSB

(Note 6)

DNL

(Note 9)

Differential Non-linearity

Monotonic Over All Tap Positions

±0.4

LSB

(Note 6)

U, T option

±0.15

LSB

(Note 6)

ZSerror

(Note 7)

Zero-scale Error

W option

0

1

0.5

-1

5

2

0

2

LSB

(Note 6)

U, T option

W option

FSerror

(Note 8)

Full-scale Error

-5

-2

LSB

(Note 6)

U, T option

-1

V

DCP-to-DCP Matching

Wipers at the same tap position, the same

voltage at all RH terminals and the same

voltage at all RL terminals

LSB

(Note 6)

MATCH

(Note 11, 19)

FN6422 Rev.2.00

Aug 17, 2015

Page 4 of 19

ISL22323

Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

DCP register set to 80 hex

(Note 21) (Note 5) (Note 21)

UNIT

TC (Note 12, Ratiometric Temperature Coefficient

V

±4

ppm/°C

19)

f

-3dB Cut Off Frequency

Wiper at midpoint (80hex) W option (10k)

Wiper at midpoint (80hex) U option (50k)

Wiper at midpoint (80hex) T option (100k)

1000

250

kHz

cutoff

(Note 19)

120

RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected)

RINL

(Note 16)

Integral Non-linearity

Differential Non-linearity

Offset

W option

-3

±1.5

±0.4

±0.5

±0.15

1

3

MI

(Note 13)

U, T option

W option

-1

1

MI

(Note 13)

RDNL

(Note 15)

-1.5

-0.5

0

1.5

0.5

5

MI

(Note 13)

U, T option

W option

MI

(Note 13)

Roffset

MI

(Note 14)

(Note 13)

U, T option

0

0.5

2

MI

(Note 13)

R

DCP-to-DCP Matching

Wipers at the same tap position with the

same terminal voltages

-2

2

MI

(Note 13)

MATCH

(Note 17)

TC

Resistance Temperature Coefficient

DCP register set between 32hex and FF hex

±40

ppm/°C

R

(Notes 18, 19)

Operating Specifications Over the recommended operating conditions unless otherwise specified.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 21) (Note 5) (Note 21)

UNIT

2

I

V

Supply Current (Volatile

V

= 5.5V, f = 400kHz; (for I C Active,

SCL

0.01

0.005

-0.05

0.2

mA

CC1

CC

Write/Read)

Read and Volatile Write states only)

2

V

= 2.25V, f

= 400kHz; (for I C Active,

SCL

0.1

mA

CC

Read and Volatile Write states only)

I

V- Supply Current (Volatile

Write/Read)

V- = -5.5V, V = 5.5V, f = 400kHz; (for

I C Active, Read and Volatile Write states

-0.2

-0.1

V-1

CC

SCL

2

only)

V- = -2.25V, V

= 2.25V, f

= 400kHz;

SCL

(for I C Active, Read and Volatile Write

states only)

-0.02

1.0

mA

CC

2

I

V

Supply Current (Non-volatile

V = 5.5V, V- = 5.5V, f

CC SCL

= 400kHz; (for

I C Active, Read and Non-volatile Write

states only)

2.0

1.0

CC2

CC

2

Write/Read)

V

= 2.25V, V- = -2.25V, f

SCL

= 400kHz;

0.3

CC

2

(for I C Active, Read and Non-volatile Write

states only)

I

V- Supply Current (Non-volatile

Write/Read)

V- = -5.5V, V

= 5.5V, f

CC SCL

= 400kHz; (for

I C Active, Read and Non-volatile Write

states only)

-2.0

-1.0

-1.2

-0.4

V-2

2

V- Supply Current (Non-volatile

Write/Read)

V- = -2.25V, V

= 2.25V, f

= 400kHz;

SCL

(for I C Active, Read and Non-volatile Write

states only)

CC

2

FN6422 Rev.2.00

Aug 17, 2015

Page 5 of 19

ISL22323

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

= +5.5V, V- = -5.5V @ +85°C, I C

(Note 21) (Note 5) (Note 21)

UNIT

2

I

V

Current (Standby)

V

0.5

1.0

2.0

4.0

1.0

2.0

µA

SB

CC

interface in standby state

2

V

= +5.5V, V- = -5.5V @ +125°C, I C

µA

µs

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +85°C, I C

0.2

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +125°C, I C

0.5

CC

interface in standby state

2

I

V- Current (Standby)

V- = -5.5V, V = +5.5V @ +85°C, I C

-3.0

-5.0

-2.0

-3.0

-0.7

-1.5

-0.3

-0.4

0.5

V-SB

CC

interface in standby state

2

V- = -5.5V, V

= +5.5V @ +125°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +85°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +125°C, I C

CC

interface in standby state

2

I

V

Current (Shut-down)

V

= +5.5V, V- = -5.5V @ +85°C, I C

2.0

4.0

1.0

2.0

SD

CC

interface in standby state

2

V

= +5.5V, V- = -5.5V @ +125°C, I C

1.0

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +85°C, I C

0.2

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +125°C, I C

0.5

CC

interface in standby state

2

I

V- Current (Standby)

V- = -5.5V, V = +5.5V @ +85°C, I C

-3.0

-5.0

-2.0

-3.0

-1

-0.7

-1.5

-0.3

-0.4

V-SB

CC

interface in standby state

2

V- = -5.5V, V

= +5.5V @ +125°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +85°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +125°C, I C

CC

interface in standby state

I

Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to V

SDA, and SCL

1

LkgDig

CC

t

DCP Wiper Response Time

SCL falling edge of last bit of DCP data byte

to wiper new position

1.5

WRT

(Note 19)

t

DCP Recall Time from Shut-down

SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

µs

ShdnRec

(Note 19) Mode

Vpor

Power-on Recall Voltage

Ramp Rate

Minimum V

at which memory recall occurs

1.9

0.2

2.1

5

V

CC

VCCRamp

V

V/ms

ms

CC

t

Power-up Delay

V

above Vpor, to DCP Initial Value

CC

D

2

Register recall completed, and I C Interface

in standby state

FN6422 Rev.2.00

Aug 17, 2015

Page 6 of 19

ISL22323

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

MIN

TYP

MAX

SYMBOL

EEPROM SPECIFICATION

EEPROM Endurance

PARAMETER

TEST CONDITIONS

(Note 21) (Note 5) (Note 21)

UNIT

1,000,000

50

Cycles

Years

ms

EEPROM Retention

Temperature T +55°C

t

Non-volatile Write Cycle Time

12

20

WC

(Note 20)

SERIAL INTERFACE SPECS

V

A0, A1, A2, SDA, and SCL Input

Buffer LOW Voltage

0.3*V

V

IL

CC

V

A0, A1, A2, SDA, and SCL Input

Buffer HIGH Voltage

0.7*V

CC

IH

Hysteresis SDA and SCL Input Buffer Hysteresis

(Note 19)

0.05*V

0

V

CC

V

SDA Output Buffer LOW Voltage,

0.4

10

V

OL

(Note 19) Sinking 4mA

Cpin

A0, A1, A2, SDA, and SCL Pin

pF

(Note 19) Capacitance

f

SCL Frequency

Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is

400

50

kHz

ns

SCL

t

sp

and SCL Inputs suppressed

t

SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V , until

CC

900

ns

AA

(Note 19) Valid

SDA exits the 30% to 70% of V

window

CC

during a STOP

condition, to SDA crossing 70% of V

t

Time the Bus Must be Free Before The SDA crossing 70% of V

CC

1300

BUF

(Note 19) Start of a New Transmission

CC

during the following START condition

t

Clock LOW Time

Measured at the 30% of V

Measured at the 70% of V

crossing

1300

600

ns

LOW

CC

t

Clock HIGH Time

HIGH

t

START Condition Setup Time

SCL rising edge to SDA falling edge; both

crossing 70% of V

600

SU:STA

HD:STA

SU:DAT

CC

From SDA falling edge crossing 30% of V

t

START Condition Hold Time

Input Data Setup Time

600

100

ns

CC

to SCL falling edge crossing 70% of V

CC

From SDA exiting the 30% to 70% of V

CC

window, to SCL rising edge crossing 30% of

V

CC

t

Input Data Hold Time

From SCL rising edge crossing 70% of V

0

ns

HD:DAT

CC

to SDA entering the 30% to 70% of V

window

CC

t

STOP Condition Setup Time

From SCL rising edge crossing 70% of V

,

600

1300

0

ns

SU:STO

CC

to SDA rising edge crossing 30% of V

CC

t

STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;

HD:STO

or Volatile Only Write

Output Data Hold Time

both crossing 70% of V

CC

t

From SCL falling edge crossing 30% of V

,

DH

(Note 19)

CC

until SDA enters the 30% to 70% of V

window

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

20 +

0.1*Cb

250

ns

R

CC

(Note 19)

t

From 70% to 30% of V

20 +

F

CC

(Note 19)

0.1*Cb

FN6422 Rev.2.00

Aug 17, 2015

Page 7 of 19

ISL22323

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

Total on-chip and off-chip

(Note 21) (Note 5) (Note 21)

UNIT

Cb

(Note 19)

Capacitive Loading of SDA or SCL

10

1

400

pF

Rpu

SDA and SCL Bus Pull-up Resistor

Maximum is determined by t and t

k

R

F

(Note 19) Off-chip

For Cb = 400pF, max is about 2k~ 2.5k

For Cb = 40pF, max is about 15k~ 20k

t

A0, A1, and A2 Setup Time

A0, A1, and A2 Hold Time

Before START condition

After STOP condition

600

ns

SU:A

t

HD:A

NOTES:

5. Typical values are for T = +25°C and 3.3V supply voltage.

A

6. LSB: [V(R

)

– V(R ) ]/255. V(R

)

and V(R ) are V(R ) for the DCP register set to FF hex and 00 hex respectively. LSB is the

W 0 W

W 255

W 0 W 255

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW) /LSB.

0

8. FS error = [V(RW)

– V ]/LSB.

CC

255

9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

10. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255

i

0

11. V

12.

= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1.

MATCH

MaxVRW  – MinVRW 

6

10

i

for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

MaxVRW  + MinVRW   2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

--------------------------------------------------------------------------------------------- ----------------

TC

=



V

+

i

13. MI = |RW

– RW |/255. MI is a minimum increment. RW

and RW are the measured resistances for the DCP register set to FF hex and 00

255 0

255

hex respectively.

0

14. R

= RW /MI, when measuring between RW and RL.

OFFSET

0

R

= RW

/MI, when measuring between RW and RH.

OFFSET

255

15. RDNL = (RW – RW )/MI -1, for i = 16 to 255.

i-1

i

16. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.

i

0

17. R

18.

= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1.

6

MATCH

for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is

the minimum value of the resistance over the temperature range.

MaxRi – MinRi

10

--------------------------------------------------------------- ----------------

TC

=



R

165°C

MaxRi + MinRi  2

+

19. This parameter is not 100% tested.

2

20. t

is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-volatile

WC

write cycle.

21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

FN6422 Rev.2.00

Aug 17, 2015

Page 8 of 19

ISL22323

DCP Macro Model

R

TOTAL

RH

RL

C

L

C

H

C

W

10pF

25pF

RW

SDA vs SCL Timing

t

sp

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

A0, A1 and A2 Pin Timing

STOP

START

SCL

CLK 1

SDA

t

HD:A

SU:A

A0, A1, A2

Typical Performance Curves

80

2.0

1.5

1.0

0.5

0

T = +125°C

70

60

50

40

30

20

10

0

T = +25°C

I

CC

-0.5

-1.0

-1.5

-2.0

I

V-

T = -40°C

0

50

100

150

200

250

-40

0

40

TEMPERATURE (°C)

80

120

TAP POSITION (DECIMAL)

FIGURE 2. STANDBY I

and I vs TEMPERATURE

V-

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 10k (W)

CC

CC TOTAL

FN6422 Rev.2.00

Aug 17, 2015

Page 9 of 19

ISL22323

Typical Performance Curves (Continued)

0.50

0.25

0

V

= 5.5V

CC

T = +25°C

V

= 2.25V

CC

0.25

0

-0.25

-0.50

-0.25

-0.50

V

= 5.5V

V

= 2.25V

100

CC

100

TAP POSITION (DECIMAL)

CC

0

50

150

200

250

0

50

150

200

250

TAP POSITION (DECIMAL)

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10k (W)

2.0

0

10k

1.6

1.2

-1

V

= 2.25V

CC

50k

V

= 5.5V

CC

-2

-3

-4

0.8

50k

10k

V

= 2.25V

V

= 5.5V

CC

0.4

0

-5

-40

0

40

80

120

-40

0

40

TEMPERATURE (ºC)

80

120

TEMPERATURE (ºC)

FIGURE 6. FS ERROR vs TEMPERATURE

FIGURE 5. ZS ERROR vs TEMPERATURE

2.0

0.5

0.25

0

T = +25°C

1.5

1.0

V

= 5.5V

CC

V

= 2.25V

CC

0.5

0

-0.25

-0.50

V

= 2.25V

100

CC

V

= 5.5V

CC

-0.5

0

50

100

150

200

250

0

50

150

200

250

TAP POSITION (DECIMAL)

FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

10k (W)

FN6422 Rev.2.00

Aug 17, 2015

Page 10 of 19

ISL22323

Typical Performance Curves (Continued)

200

160

120

80

1.60

10k

1.20

10k

0.80

5.5V

0.40

0.00

50k

40

50k

2.25V

0

-0.40

16

66

116

166

216

266

-40

0

40

80

120

TAP POSITION (DECIMAL)

TEMPERATURE (ºC)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. END TO END R

% CHANGE vs

TOTAL

TEMPERATURE

500

400

300

INPUT

OUTPUT

10k

200

100

50k

WIPER AT MID POINT (POSITION 80h)

R

= 10k

TOTAL

0

16

66

116

166

216

TAP POSITION (DECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

FIGURE 12. FREQUENCY RESPONSE (1MHz)

CS

SCL

WIPER UNLOADED,

WIPER

MOVEMENT FROM 0h to FFh

FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h

FIGURE 14. LARGE SIGNAL SETTLING TIME

FN6422 Rev.2.00

Aug 17, 2015

Page 11 of 19

ISL22323

the corresponding WRi to set the wipers to their initial

positions.

Pin Description

Potentiometers Pins

RHI AND RLi

DCP Description

The DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each DCP

are equivalent to the fixed terminals of a mechanical

The high (RHi) and low (RLi) terminals of the ISL22323 are

equivalent to the fixed terminals of a mechanical

potentiometer. RHi and RLi are referenced to the relative

position of the wiper and not the voltage potential on the

terminals. With WRi set to 255 decimal, the wiper will be

closest to RHi, and with the WRi set to 0, the wiper is closest to

RLi.

potentiometer (RHi and RLi pins). The RWi pin of the DCP is

connected to intermediate nodes, and is equivalent to the

wiper terminal of a mechanical potentiometer. The position of

the wiper terminal within the DCP is controlled by an 8-bit

volatile Wiper Register (WRi). When the WRi of a DCP

contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is

closest to its “Low” terminal (RLi). When the WRi register of a

DCP contains all ones (WRi[7:0] = FFh), its wiper terminal

(RWi) is closest to its “High” terminal (RHi). As the value of the

WRi increases from all zeroes (0) to all ones (255 decimal), the

wiper moves monotonically from the position closest to RLi to

the position closest to RHi. At the same time, the resistance

between RWi and RLi increases monotonically, while the

resistance between RHi and RWi decreases monotonically.

RWi

RWi is the wiper terminal, and it is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WRi register.

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

2

The SDA is a bidirectional serial data input/output pin for I C

interface. It receives device address, operation code, wiper

address and data from an I C external master device at the

rising edge of the serial clock SCL, and it shifts out data after

each falling edge of the serial clock.

2

While the ISL22323 is being powered up, the WRi is reset to

80h (128 decimal), which locates RWi roughly at the center

between RLi and RHi. After the power supply voltage becomes

large enough for reliable non-volatile memory reading, the WRi

will be reloaded with the value stored in corresponding non-

volatile Initial Value Register (IVRi).

SDA requires an external pull-up resistor, since it is an open

drain input/output.

SERIAL CLOCK (SCL)

The WRi and IVRi can be read or written to directly using the

I C serial interface as described in the following sections.

2

This input is the serial clock of the I C serial interface. SCL

requires an external pull-up resistor.

Memory Description

DEVICE ADDRESS (A2, A1, A0)

The ISL22323 contains two non-volatile 8-bit Initial Value Register

(IVRi), thirteen General Purpose non-volatile 8-bit registers and

three volatile 8-bit registers: two Wiper Registers (WRi) and

Access Control Register (ACR). Memory map of ISL22323 is in

Table 1. The non-volatile registers (IVRi) at address 0 and 1,

contain initial wiper position and volatile registers (WRi) contain

current wiper position.

The address inputs are used to set the least significant 3 bits of

the 7-bit I C interface slave address. A match in the slave

2

address serial data stream must match with the Address input

pins in order to initiate communication with the ISL22323. A

2

maximum of eight ISL22323 devices may occupy the I C serial

bus (See Table 3).

TABLE 1. MEMORY MAP

Principles of Operation

The ISL22323 is an integrated circuit incorporating two DCPs

with its associated registers, non-volatile memory and an I C

serial interface providing direct communication between a host

and the potentiometer and memory. The resistor arrays are

comprised of individual resistors connected in a series. At

either end of the array and between each resistor is an

electronic switch that transfers the potential at that point to the

wiper.

ADDRESS

(hex)

10

F

NON-VOLATILE

VOLATILE

2

N/A

ACR

Reserved

E

General Purpose

N/A

D

C

B

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions.

A

9

When the device is powered down, the last value stored in IVRi

will be maintained in the non-volatile memory. When power is

restored, the contents of the IVRi are recalled and loaded into

8

7

FN6422 Rev.2.00

Aug 17, 2015

Page 12 of 19

ISL22323

2

TABLE 1. MEMORY MAP (Continued)

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

ADDRESS

(hex)

NON-VOLATILE

General Purpose

IVR1

VOLATILE

Protocol Conventions

6

5

4

3

2

1

0

N/A

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 16). On power-up of the ISL22323, the SDA pin is in the

input mode.

N/A

2

All I C interface operations must begin with a START

WR1

WR0

condition, which is a HIGH to LOW transition of SDA while SCL

is HIGH. The ISL22323 continuously monitors the SDA and

SCL lines for the START condition and does not respond to

any command until this condition is met (see Figure 16). A

START condition is ignored during the power-up of the device.

IVR0

The non-volatile IVRi and volatile WRi registers are accessible

with the same address.

2

The Access Control Register (ACR) contains information and

control bits described in Table 2.

All I C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL

is HIGH (see Figure 16). A STOP condition at the end of a read

operation, or at the end of a write operation places the device

in its standby mode.

The VOL bit (ACR[7]) determines whether the access to wiper

registers WRi or initial value registers IVRi.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

An ACK (Acknowledge) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after transmitting

eight bits. During the ninth clock cycle, the receiver pulls the

SDA line LOW to acknowledge the reception of the eight bits of

data (see Figure 17).

BIT #

7

6

5

4

0

3

0

2

0

1

0

NAME

VOL

SHDN WIP

If VOL bit is 0, the non-volatile IVRi registers are accessible. If

VOL bit is 1, only the volatile WRi are accessible. Note: value

is written to IVRi register also is written to the corresponding

WRi. The default value of this bit is 0.

The ISL22323 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22323 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

The SHDN bit (ACR[6]) disables or enables Shut-down mode.

When this bit is 0, DCPs are in Shut-down mode. Default value of

the SHDN bit is 1.

RHi

A valid Identification Byte contains 1010 as the four MSBs, and

the following three bits matching the logic values present at

pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is

“1” for a Read operation and “0” for a Write operation (See

Table 3).

RWi

TABLE 3. IDENTIFICATION BYTE FORMAT

RLi

FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE

LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY

The WIP bit (ACR[5]) is a read-only bit. It indicates that

non-volatile write operation is in progress. It is impossible to

write to the WRi or ACR while WIP bit is 1.

1

0

1

0

A2

A1

A0

R/W

(MSB)

(LSB)

2

I C Serial Interface

2

The ISL22323 supports an I C bidirectional bus oriented

protocol. The protocol defines any device that sends data onto

the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both transmit

and receive operations. Therefore, the ISL22323 operates as a

slave device in all applications.

FN6422 Rev.2.00

Aug 17, 2015

Page 13 of 19

ISL22323

SCL

SDA

START

DATA

STOP

STABLE

CHANGE STABLE

FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

SIGNALS FROM

THE MASTER

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 0 1 0 A2A1A0 0

0 0 0 0

SIGNALS FROM

THE SLAVE

A

C

K

A

C

K

A

C

K

FIGURE 18. BYTE WRITE SEQUENCE

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

A

C

K

A

C

K

IDENTIFICATION

BYTE WITH

R/W = 0

IDENTIFICATION

BYTE WITH

R/W = 1

A

C

K

ADDRESS

BYTE

SIGNAL AT SDA

1 0 1 0 A2A1A0 0

0 0 0 0

1 0 1 A2A1A0 1

0

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 19. READ SEQUENCE

FN6422 Rev.2.00

Aug 17, 2015

Page 14 of 19

ISL22323

More application examples can be found at:

http://www.intersil.com/data/an/AN1145.pdf

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte, and

a STOP condition. After each of the three bytes, the ISL22323

responds with an ACK. At this time, the device enters its

standby state (See Figure 18).

The non-volatile write cycle starts after STOP condition is

determined and it requires up to 20ms delay for the next non-

volatile write. Thus, non-volatile registers must be written

individually.

Read Operation

A Read operation consist of a three byte instruction followed by

one or more Data Bytes (See Figure 19). The master initiates

the operation issuing the following sequence: a START, the

Identification byte with the R/W bit set to “0”, an Address Byte,

a second START, and a second Identification byte with the R/W

bit set to “1”. After each of the three bytes, the ISL22323

responds with an ACK. Then the ISL22323 transmits Data

Bytes as long as the master responds with an ACK during the

SCL cycle following the eighth bit of each byte. The Data Bytes

are from the registers indicated by an internal pointer. This

pointers initial value is determined by the Address Byte in the

Read operation instruction, and increments by one during

transmission of each Data Byte. After reaching the memory

location 0Fh, the pointer “rolls over” to 00h, and the device

continues to output data for each ACK received.The master

terminates the read operation issuing a NACK (ACK) and a

STOP condition following the last bit of the last Data Byte (See

Figure 19).

Applications Information

Wiper Transition

When stepping up through each tap in voltage divider mode,

some tap transition points can result in noticeable voltage

transients (or overshoot/undershoot) resulting from the sudden

transition from a very low impedance “make” to a much higher

impedance “break within an extremely short period of time

(<50ns). Two such code transitions are EFh to F0h, and 0Fh to

10h. Note that all switching transients will settle well within the

settling time as stated on the datasheet. A small capacitor can

be added externally to reduce the amplitude of these voltage

transients, but that will also reduce the useful bandwidth of the

circuit, thus this may not be a good solution for some

applications. It may be a good idea, in that case, to use fast

amplifiers in a signal chain for fast recovery.

Application Example

Figure 20 shows an example of using ISL22323 for gain setting

and offset correction in high side current measurement

application. DCP0 applies a programmable offset voltage of

±25mV to the FB+ pin of the Instrumentation Amplifier EL8173

to adjust output offset to zero voltages. DCP1 programs the

gain of the EL8173 from 90 to 110 with 5V output for 10A

current through current sense resistor.

FN6422 Rev.2.00

Aug 17, 2015

Page 15 of 19

ISL22323

1.2V

DC/DC CONVERTER

OUTPUT

PROCESSOR LOAD

10A, MAX

0.005

+5V

10k

0.1µF

8

EL8173IS

1

V +

S

3

2

7

5

IN+

IN-

EN

6

V

= 0V TO +5V to ADC

OUT

FB+

+5V

R

4

FB-

V -

S

150k, 1%

R

1

4

50k, 1%

RH1

RL1

RH0

RW1

R

5

309, 1%

R

2

1k, 1%

RW0

RL0

50k

DCP0 (1/2 ISL22323U)

PROGRAMMABLE OFFSET ±25mV

DCP1 (1/2 ISL22323U)

PROGRAMMABLE GAIN 90 TO 110

R

6

R

3

1.37k, 1%

50k, 1%

-5V

ISL22323UFV14Z

14

1

2

3

+5V

I C BUS

VCC

RH0

RL0

RW0

DCP0

DCP1

10

9

7

12

13

2

SCL

SDA

A2

A1

A0

4

5

6

RH1

RL1

RW1

11

8

GND

-5V

V-

FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL

FN6422 Rev.2.00

Aug 17, 2015

Page 16 of 19

ISL22323

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make

sure that you have the latest revision.

DATE

REVISION

CHANGE

August 17, 2015

FN6422.2

- Ordering Information Table on page 2.

- Added Revision History

- Added About Intersil Verbiage.

- Updated POD L16.4X4A to latest revision changes are as follow:

Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing.

Added Typical Recommended Land Pattern. Removed package option.

- Updated POD M14.173 to most current version changes are as follow:

Updated drawing to remove table and added land pattern.

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6422 Rev.2.00

Aug 17, 2015

Page 17 of 19

ISL22323

Package Outline Drawing

L16.4x4A

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 03/15

2.40

4.00

A

4X 1.50

6

B

PIN #1

INDEX AREA

13

16

6

PIN 1

INDEX AREA

12

0.50

1

4

12X

2.40

9

(4X)

0.15

5

8

0.10 M C A B

TOP VIEW

16x 0.40±0.01

+0.05

0.25

4

-0.07

BOTTOM VIEW

SEE

DETAIL "X"

0.90±0.10

C

0.10

SEATING

PLANE

0.08 C

C

SIDE VIEW

(3.8 TYP)

(

2.40)

(12x 0.50)

5

C

0.20 REF

(16x 0.25)

(16x 0.60)

+0.03/-0.02

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance: Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be either

a mold or mark feature.

FN6422 Rev.2.00

Aug 17, 2015

Page 18 of 19

ISL22323

Package Outline Drawing

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09

A

1

3

5.00 ±0.10

SEE

DETAIL "X"

14

8

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

1

7

0.20 C B A

B

0.65

0.09-0.20

TOP VIEW

END VIEW

1.00 REF

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

SEATING

PLANE

GAUGE

PLANE

0.25

5

0.25 +0.05/-0.06

0.10 CBA

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

0.10 C

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

(5.65)

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.80mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead is 0.07mm.

6. Dimension in ( ) are for reference only.

(0.65 TYP)

(0.35 TYP)

7. Conforms to JEDEC MO-153, variation AB-1.

TYPICAL RECOMMENDED LAND PATTERN

FN6422 Rev.2.00

Aug 17, 2015

Page 19 of 19


型号：	ISL22323UFV14Z
厂家：	RENESAS TECHNOLOGY CORP
描述：	Dual Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN16, TSSOP14; Temp Range: -40° to 125°C 光电二极管转换器电阻器
文件：	总19页 (文件大小：1145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL22323UFV14Z [RENESAS]

相关型号：

ISL22323WFR16Z

ISL22323WFR16Z

ISL22323WFV14Z

ISL22323WFV14Z

ISL22323WFV14Z-TK

ISL22326

ISL22326

ISL22326UFR16Z

ISL22326UFR16Z

ISL22326UFR16Z-TK

ISL22326UFV14Z

ISL22326UFV14Z