ICL7129_00_技术文档

®

ICL7129

1

4 / Digit LCD,

2

July 2000

Single-Chip A/D Converter

Features

Description

1

• ±19,999 Count A/D Converter Accurate to ±4 Count

• 10µV Resolution on 200mV Scale

• 110dB CMRR

• Direct LCD Display Drive

• True Differential Input and Reference

• Low Power Consumption

The Intersil ICL7129 is a very high performance 4 / -digit,

2

analog-to-digital converter that directly drives a multiplexed

liquid crystal display. This single chip CMOS integrated

circuit requires only a few passive components and a

reference to operate. It is ideal for high resolution hand-held

digital multimeter applications.

• Decimal Point Drive Outputs

• Overrange and Underrange Outputs

• Low Battery Detection and Indication

• 10:1 Range Change Input

The performance of the ICL7129 has not been equaled

before in a single chip A/D converter. The successive integra-

tion technique used in the ICL7129 results in accuracy better

than 0.005% of full scale and resolution down to 10µV/count.

The ICL7129, drawing only 1mA from a 9V battery, is well

suited for battery powered instruments. Provision has been

made for the detection and indication of a “LOW/BATTERY”

condition. Autoranging instruments can be made with the

ICL7129 which provides overrange and underrange outputs

and 10:1 range changing input. The ICL7129 instantly checks

for continuity, giving both a visual indication and a logic level

output which can enable an external audible transducer. These

features and the high performance of the ICL7129 make it an

extremely versatile and accurate instrument-on-a-chip.

Ordering Information

TEMP.

o

PART NUMBER RANGE ( C)

PACKAGE

40 Ld PDIP

44 Ld MQFP

PKG. NO.

E40.6

ICL7129CPL

ICL7129RCPL

ICL7129CM44

0 to 70

E40.6

Q44.10x10

NOTE: “R” indicates device with reversed leads.

Pinouts

ICL7129 (PDIP)

ICL7129 (MQFP)

TOP VIEW

1

2

40 OSC2

OSC1

OSC3

39 DP

1

ANNUNCIATOR

3

38 DP

2

DRIVE

4

37 RANGE

36 DGND

35 REF LO

B , C , CONT

1

5

A , G , D

1

44 43 42 41 40 39 38 37 36 35 34

6

F , E , DP

1

2

3

4

5

6

7

8

9

V+

V-

DGND

33

32

31

30

29

REF HI

34

7

B , C , LO BAT

2

RANGE

8

33 IN HI

32 IN LO

31 BUFF

A , G , D

2

NC

DP

2

9

F , E , DP

2

NC

LATCH/

HOLD

1

10

11

12

13

14

15

16

17

18

19

20

B , C , MINUS

3

OSC 2

OSC 1

OSC 3

NC

30

29

C

A , G , D

REF-

3

5

4

28

27

26

25

24

23

DP /UR

3

F , E , DP

REF+

3

DP /OR

4

28 COMMON

B , C , BC

4

V

DISP

27 CONTINUITY

26 INT OUT

25 INT IN

A , D , G

4

NC

BP1

BP2

BP3

F , E , DP

4

ANNUNCE

DRIVE

B , C , CONT

10

11

BP3

1

12 13 14 15 16 17 18 19 20 21 22

24 V+

BP2

BP1

23 V-

22 LATCH/HOLD

V

DISP

21 DP /UR

3

DP /OR

4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

File Number 3085.2

1

ICL7129

Functional Block Diagram

LOW BATTERY CONTINUITY

BACKPLANE

DRIVES

SEGMENT DRIVES

ANNUNCIATOR DRIVE

LATCH, DECODE DISPLAY MULTIPLEXER

V

DISP

OSC1

OSC2

OSC3

UP/DOWN RESULTS COUNTER

SEQUENCE COUNTER/DECODER

CONTROL LOGIC

ANALOG SECTION

RANGE L/H CONT

V+

V-

DGND

OR

DP

UR DP

DP

2

1

DP

3

Typical Application Schematic

LOW BATTERY CONTINUITY

V+

5pF

(MICA)

120kHz

ICL7129

270K

560pF

(MICA)

10pF

1.2kΩ

V+

+

0.1µF

20K

1.0µF

6.8µF

0.1µF

150kΩ

10kΩ

+

ICL8069

100kΩ

9V

+

-

V

IN

2

ICL7129

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

Reference Voltage (REF HI or REF LO) . . . . . . . . . . . . . . . V+ to V-

Input Voltage (Note 1), IN HI or IN LO . . . . . . . . . . . . . . . . . V+ to V-

Thermal Resistance (Typical, Note 2)

θ

( C/W)

JA

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C

50

80

o

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND -0.3V to V+

DISP

o

Digital Input Pins

1, 2, 19, 20, 21, 22, 27, 37, 38, 39, 40 . . . . . . . . . . . . .DGND to V+

(MQFP - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltages provided that input current is limited to 1400mA. Currents above this value may result in

valid display readings but will not destroy the device if limited to ±1mA.

2. θ is measured with the component mounted on an evaluation PC board in free air.

JA

o

Electrical Specifications V- to V+ = 9V, V

= 1.00V, T = 25 C, f

= 120kHz, Unless Otherwise Specified

REF

A

CLK

PARAMETER

Zero Input Reading

TEST CONDITIONS

= 0V, 200mV Scale

MIN

-0000

-

TYP

0000

±0.5

MAX

+0000

-

UNITS

V

Counts

IN

o

Zero Reading Drift

V

= 0V, 0 C To 70 C

= V = 1000mV, RANGE = 2V

µV/ C

Ratiometric Reading

9996

0.9999

9999

1.0000

10000

1.0001

Counts

Ratio

REF

= 0.10000V on Low,

Range Change Accuracy

Range ≈ V = 1.0000V on High Range

IN

Rollover Error

-V = +V = 199mV

IN IN

-

1.5

1.0

110

3.0

Counts

dB

Linearity Error

200mV Scale

-

Input Common-Mode Rejection Ratio

Input Common-Mode Voltage Range

V

= 1V,V = 0V, 200mV Scale

IN

CM

= 0V, 200mV Scale

(V-) +1.5

(V+) -1.0

V

IN

Noise (Peak-To-Peak Value not Exceeded 95% of

Time)

V

= 0V 200mV Scale

-

14

-

µV

IN

Input Leakage Current

Scale Factor Tempco

V

= 0V, Pin 32, 33

o

-

1

2

10

7

pA

IN

o

= 199mV 0 C To 70 C

ppm/ C

IN

External V

= 0ppm/ C

REF

COMMON Voltage

V+ to Pin 28

2.8

3.2

0.6

10

3.5

V

mA

µA

V

COMMON Sink Current

COMMON Source Current

DGND VoItage

∆Common = + 0.1V

∆Common = -0.1V

V+ to Pin 36, V+ to V- = 9V

∆DGND = +0.5V

V+ to V- (Note 3)

V+ to V- = 9V

-

4.5

5.3

1.2

9

5.8

-

DGND Sink Current

-

mA

V

Supply Voltage Range

Supply Current Excluding COMMON Current

Clock Frequency

6

12

1.5

360

-

1.0

120

50

mA

kHz

kΩ

V

(Note 3)

-

V

Resistance

V

to V+

-

DISP

Low Battery Flag Activation Voltage

V+ to V-

6.3

7.2

200

2

7.7

-

CONTINUITY Comparator Threshold Voltages

V

Pin 27 = HI

Pin 27 = LO

100

mV

µA

OUT

-

400

10

-

OUT

Pull-Down Current

Pins 37, 38, 39

“Weak Output” Current Sink/Source

Pins 20, 21 Sink/Source

Pin 27 Sink/Source

3/3

3/9

40

-

Pin 22 Source Current

Pin 22 Sink Current

-

3

-

3

ICL7129

o

Electrical Specifications V- to V+ = 9V, V

= 1.00V, T = 25 C, f

= 120kHz, Unless Otherwise Specified

CLK

REF

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

NOTE:

3. Device functionality is guaranteed at the stated Min/Max limits. However, accuracy can degrade under these conditions.

Pin Descriptions

1

SYMBOL

DESCRIPTION

Input to first clock inverter.

Output of second clock inverter.

SYMBOL

DESCRIPTION

OSC

22

LATCH/HOLD

INPUT: When floating, A/D converter

operates in the free-run mode. When

pulled HI, the last displayed reading is

held. When pulled LO, the result

1

3

2

3

ANNUNCIATOR Backplane squarewave output for

counter

contents

are

shown

DRIVE

driving annunciators.

incrementing during the de-integrate

phase of cycle.

4

B , C , CONT

Output to display segments.

1

OUTPUT: Negative going edge

occurs when the data latches are

updated. Can be used for converter

status signal.

5

A , G , D

1 1 1

6

F , E , DP

1 1 1

23

24

V-

Negative power supply terminal.

7

B , C , LO BATT Output to display segments.

2 2

V+

Positive power supply terminal, and

positive rail for display drivers.

8

A , G , D

2

Output to display segments.

2

9

F , E , DP

2 2 2

25

26

27

INT IN

INT OUT

Input to integrator amplifier.

Output of integrator amplifier.

10

11

12

13

14

15

16

17

18

19

20

B , C , MINUS Output to display segments.

3 3

A , G , D

3

Output to display segments.

Backplane #3 output to display.

Backplane #2 output to display.

Backplane #1 output to display.

Negative rail for display drivers.

3

CONTINUITY

INPUT: When LO, continuity flag on

the display is off. When HI,

continuity flag is on.

F , E , DP

3

B , C , BC

4

5

OUTPUT: HI when voltage between

inputs is less than +200mV. LO

when voltage between inputs is

more than +200mV.

A , D , G

4

F , E , DP

4

28

COMMON

Sets common-mode voltage of 3.2V

below V+ for DE, 10X, etc., Can be

used as pre-regulator for external

reference.

BP

3

2

1

BP

29

30

C

+

Positive side of external reference

capacitor.

REF

V

DlSP

C

-

Negative side of external reference

capacitor.

REF

DP /OR

INPUT: When HI, turns on most

significant decimal point.

4

31

32

33

34

BUFFER

IN LO

Output of buffer amplifier.

OUTPUT: Pulled HI when result

count exceeds ±19,999.

Negative input voltage terminal.

Positive input voltage terminal.

21

DP /UR

INPUT: Second most significant

decimal point on when HI.

3

IN HI

OUTPUT: Pulled HI when result

count is less than ±1,000.

REF HI

Positive reference voltage input

terminal.

35

36

REF LO

DGND

Negative reference voltage input

terminal.

Ground reference for digital section.

4

ICL7129

SYMBOL

DESCRIPTION

SYMBOL

DP

DESCRIPTION

37

RANGE

3µA pull-down for 200mV scale.

39

Internal 3µA pull-down. When HI,

1

Pulled HIGH externally for 2V scale.

decimal point 1 will be on.

38

DP

Internal 3µA pull-down. When HI,

decimal point 2 will be on.

40

OSC2

Output of first clock inverter. Input of

second clock inverter.

2

C

R

C

INT

REF

REF LO

INT

REF HI

BUFFER

INT, IN

INT OUT

DE DE

X10

COMPARATOR 1

10

INT

-

1

-

+

IN HI

+

TO DIGITAL

SECTION

-

Detailed Description

-

DE-

DE+

INT , INT

DE+

DE-

BUFFER

Z1, X10

100

INTEGRATOR

COMPARATOR 2

COMMON

IN LO

1

2

REST, INT

INT

2

FIGURE 1. ANALOG BLOCK DIAGRAM

DE

ZERO-INTEGRATE

AND LATCH

INT

1

INTEGRATE

DE-INTEGRATE REST X10 DE REST X10

2

DE ZERO-INTEGRATE

3

INTEGRATOR

RESIDUE

VOLTAGE

NOTE: Shaded area greatly expanded

in time and amplitude.

1000 CLOCKS

2000

CLOCKS

1000 CLOCKS

10,000 CLOCKS

FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND

RESIDUE VOLTAGE

COMMON, DGND, and “Low Battery”

capability of the DGND pin. If more supply current is

required, the buffer in Figure 5 can be used to keep the load-

ing on DGND to a minimum. COMMON can source approxi-

The COMMON and DGND (Digital GrouND) outputs of the

ICL7129 are generated from internal zener diodes

(Figure 3). COMMON is included primarily to set the com-

mon-mode voltage for battery operation or for any system

where the input signals float with respect to the power sup-

plies. It also functions as a pre-regulator for an external pre-

cision reference voltage source. The voltage between

DGND and V+ is the supply voltage for the logic section of

the ICL7129 including the display multiplexer and drivers.

Both COMMON and DGND are capable of sinking current

from external loads, but caution should be taken to ensure

that these outputs are not overloaded. Figure 4 shows the

connection of external logic circuitry to the ICL7129. This

connection will work providing that the supply current

requirements of the logic do not exceed the current sink

5

ICL7129

mately 12mA while DGND has no source capability.

not desired in an application it can easily be overridden by

connecting the pin to V+ (HI) or DGND (LO). This connection

will not damage the device because the output impedance of

these pins is quite high. A simplified schematic of these

input/output pins is shown in Figure 6. Since there is approx-

imately 500kΩ in series with the output driver, the pin (when

used as an output) can only drive very light loads such as

4000 series, 74CXX type CMOS logic, or other high input

impedance devices. The output drive capability of these four

pins is limited to 3µA, nominally, and the input switching

threshold is typically DGND + 2V.

24

V+

3.2V

28

COMMON

5V

-

N

+

LOGIC

SECTION

“LOW

BATTERY”

36

P

DGND

N

23

V-

≈500kΩ

DP4/OR PIN 20

DP3/UR PIN 21

FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND

LATCH/HOLD PIN 22

CONTINUITY PIN 27

ICL7129

V+

24

FIGURE 6. “WEAK OUTPUT”

LATCH/HOLD, Overrange, and Underrange Timing

EXTERNAL

LOGIC

The LATCH/HOLD output (pin 22) will be pulled low during

the last 100 clock cycles of each full conversion cycle. Dur-

ing this time the final data from the ICL7129 counter is

latched and transferred to the display decoder and multi-

plexer. The conversion cycle and LATCH/HOLD timing are

directly related to the clock frequency. A full conversion

cycle takes 30,000 clock cycles which is equivalent to

60,000 oscillator cycles. OverRange (OR pin 20) and Under-

Range (UR pin 21) outputs are latched on the falling edge of

LATCH/HOLD and remain in that state until the end of the

next conversion cycle. In addition, digits 1 through 4 are

blanked during overrange. All three of these pins are “weak

outputs” and can be overridden with external drivers or pull-

up resistors to enable their input functions as described in

the Pin Description table.

ICL7129

36

DGND

I

LOGIC

23

V-

FIGURE 4. DGND SINK CURRENT

V+

24

EXTERNAL

LOGIC

ICL7129

EXTERNAL

LOGIC

CURRENT

-

36

+

Instant Continuity

DGND

A comparator with a built-in 200mV offset is connected

directly between INPUT HI and INPUT LO of the ICL7129

(Figure 7). The CONTINUITY output (pin 27) will be pulled

high whenever the voltage between the analog inputs is less

than 200mV. This will also turn on the “CONTINUITY”

annunciator on the display. The CONTINUITY output may

be used to enable an external alarm or buzzer, thereby giv-

23

V-

FIGURE 5. BUFFERED DGND

The “LOW BATTERY” annunciator of the display is turned

on when the voltage between V+ and V- drops below 7.2V

typically. The exact point at which this occurs is determined

by the 6.3V zener diode and the threshold voltage of the

N-Channel transistor connected to the V- rail in Figure 3. As

the supply voltage decreases, the N-Channel transistor

connected to the V-rail eventually turns off and the “LOW

BATTERY” input to the logic section is pulled HIGH, turning

on the “LOW BATTERY” annunciator.

I/O Ports

Four pins of the ICL7129 can be used as either inputs or out-

puts. The specific pin numbers and functions are described

in the Pin Description table. If the output function of the pin is

6

ICL7129

ing the ICL7129 an audible continuity checking capability.

display. This type of display has three backplanes and is driven

in a multiplexed format similar to the ICM7231 display driver

family. The specific display format is shown in Figure 8. Notice

that the polarity sign, decimal points, “LOW BATTERY”, and

“CONTINUITY” annunciators are directly driven by the

ICL7129. The individual segments and annunciators are

addressed in a manner similar to row-column addressing. Each

backplane (row) is connected to one-third of the total number of

segments. BP1 has all F, A, and B segments of the four least

significant digits. BP2 has all of the C, E, and G segments. BP3

has all D segments, decimal points, and annunciators. The

segment lines (columns) are connected in groups of three

bringing all segments of the display out on just 12 lines.

-

+

IN HI

BUFFER

COMMON

IN LO

500kΩ

Annunciator Drive

200mV

-

+

V

A special display driver output is provided on the ICL7129

which is intended to drive various kinds of annunciators on

custom multiplexed liquid crystal displays. The ANNUNClA-

TOR DRIVE output (pin 3) is a squarewave signal running at

the backplane frequency, approximately 100Hz. This signal

TO DISPLAY

DRIVER

(NOT LATCHED)

CONTINUITY

FIGURE 7. “INSTANT CONTINUITY” COMPARATOR AND

OUTPUT STRUCTURE

swings from V

to V+ and is in sync with the three back-

DISP

plane outputs BP1, BP2, and BP3. Figure 9 shows these

four outputs on the same time and voltage scales.

Since the CONTINUITY output is one of the four “weak out-

puts” of the ICL7129, the “continuity” annunciator on the dis-

play can be driven by an external source if desired. The

continuity function can be overridden with a pull-down resistor

connected between CONTINUITY pin and DGND (pin 36).

Any annunciator associated with any of the three backplanes

can be turned on simply by connecting it to the ANNUNClA-

TOR DRIVE pin. To turn an annunciator off connect if to its

backplane. An example of a display and annunciator drive

scheme is shown in Figure 10.

Display Configuration

The ICL7129 is designed to drive a triplexed liquid crystal

LOW BATTERY CONTINUITY

a

f

b

BP1

BP2

BACKPLANE

CONNECTIONS

g

c

e

c

e

d

BP3

LOW BATTERY CONTINUITY

a

f

b

g

c

e

c

e

d

F4, E4, DP4

A4, G4, D4

B1, C1, CONTINUITY

A1, G1, D1

B4, C4, BC5

F3, E3, DP3

A3, G3, D3

F1, E1, DP1

B2, C2, LOW BATTERY

A2, G2, D2

B3, C3, MINUS

F2, E2, DP2

FIGURE 8. TRIPLEXED LIQUID CRYSTAL DISPLAY LAYOUT FOR ICL7129

7

ICL7129

compensation will depend upon the type of liquid crystal used.

Display manufacturers can supply the temperature compen-

sation requirements for their displays. Figure 11 shows two

BP1

BP2

circuits that can be adjusted to give a temperature compensa-

o

tion of ≈ +10mV/ C between V+ and V

. The diode

DISP

between DGND and V

should have a low turn-on voltage

DISP

to assure that no forward current is injected into the chip if

is more negative than DGND.

V

DISP

Component Selection

BP3

There are only three passive components around the

ICL7129 that need special consideration in selection. They

are the reference capacitor, integrator resistor, and integra-

tor capacitor. There is no auto-zero capacitor like that found

in earlier integrating A/D converter designs.

ON SEG.

The integrating resistor is selected to be high enough to

assure good current Iinearity from the buffer amplifier and

integrator and low enough that PC board leakage is not a

problem. A value of 150kΩ should be optimum for most appli-

cations. The integrator capacitor is selected to give an opti-

mum integrator swing at full-scale. A large integrator swing

will reduce the effect of noise sources in the comparator but

will affect rollover error if the swing gets too close to the posi-

tive rail (≈0.7V). This gives an optimum swing of ≈2.5V at full-

scale. For a 150kΩ integrating resistor and 2 conversions per

second the value is 0.1µF. For different conversion rates, the

value will change in inverse proportion. A second requirement

for good linearity is that the capacitor have low dielectric

absorption. Polypropylene caps give good performance at a

reasonable price. Finally the foil side of the cap should be

connected to the integrator output to shield against pickup.

FIGURE 9. TYPICAL BACKPLANE AND ANNUNCIATOR

DRIVE WAVEFORM

ANNUNCIATOR

µ

m

K

M

LOW BATTERY CONTINUITY

BACKPLANE

ANNUNCIATOR

AMPS

VOLTS

Ω

BACKPLANE

The only requirement for the reference cap is that it be low

leakage. In order to reduce the effects of stray capacitance,

a 1µF value is recommended.

FIGURE 10. MULTIMETER EXAMPLE SHOWING USE OF

ANNUNCIATOR DRIVE OUTPUT

Display Temperature Compensation

Clock Oscillator

For most applications an adequate display can be obtained by

The ICL7129 achieves its digital range changing by integrat-

ing the input signal for 1000 clock pulses (2,000 oscillator

cycles) on the 2V scale and 10,000 clock pulses on the

200mV scale. To achieve complete rejection of 60Hz on

both scales, an oscillator frequency of 120kHz is required,

giving two conversions per second.

connecting V

(pin 19) to DGND (pin 36). In applications

DlSP

where a wide temperature range is encountered, the voltage

drive levels for some triplexed liquid crystal displays may need

to vary with temperature in order to maintain good display

contrast and viewing angle. The amount of temperature

V+

1N4148

39K

24

200K

2N2222

20K

ICL7611

19

36

19

36

-

V

DISP

ICL7129

DGND

+

5K

ICL7129

DGND

75K

18K

23

V-

23

V-

FIGURE 11. TWO METHODS FOR TEMPERATURE COMPENSATING THE LIQUID CRYSTAL DISPLAY

8

ICL7129

In low resolution applications, where the converter uses only It is important to notice that in Figure 13, digital ground of the

1

3 / digits and 100µV resolution, an R-C type oscillator is ade- ICL7129 (DGND pin 36) is not directly connected to power

2

quate. In this application a C of 51pF is recommended and the supply ground. DGND is set internally to approximately 5V

resistor value selected from f

= 0.45/RC. However, when less than the V+ terminal and is not intended to be used as a

OSC

1

the converter is used to its full potential (4 / digits and 10µV power input pin. It may be used as the ground reference for

2

resolution) a crystal oscillator is recommended to prevent the external logic, as shown in Figure 4 and 5. In Figure 4, DGND

noise from increasing as the input signal is increased due to fre- is used as the negative supply rail for external logic provided

quency jitter of the R-C oscillator. Both R-C and crystal oscilla- that the supply current for the external logic does not cause

tor circuits are shown in Figure 12.

excessive loading on DGND. The DGND output can be buff-

ered as shown in Figure 5. Here, the logic supply current is

shunted away from the ICL7129 keeping the load on DGND

low. This treatment of the DGND output is necessary to insure

compatibility when the external logic is used to interface

directly with the logic inputs and outputs of the ICL7129.

ICL7129

1

40

2

75kΩ

When a battery voltage between 3.8V and 6V is desired for

operation, a voltage doubling circuit should be used to bring

the voltage on the ICL7129 up to a level within the power sup-

ply voltage range. This operating mode is shown in Figure 14.

51pF

ICL7129

2

24

V+

CRYSTAL MODE:

PARALLEL

27kΩ

120kHz

34

5pF

10pF

REF HI

R

C

< 50kΩ

< 12pF

< 5pF

S

L

O

V-

V+

35

REF LO

ICL7129

COM

+

3.8V TO

6V

FIGURE 12. RC AND CRYSTAL OSCILLATOR CIRCUITS

Powering the ICL7129

28

33

36

DGND

-

8

IN HI

+

2

The ICL7129 may be operated as a battery powered hand-held

instrument or integrated into larger systems that have more

sophisticated power supplies. Figures 13, 14, and 15 show

various powering modes that may be used with the ICL7129.

V

IN

+

32

IN LO

V-

3

-

4

5

ICL7660

10µF

23

10µF

+

The standard supply connection using a 9V battery is shown

in the Typical Application Schematic.

FIGURE 14. POWERING THE ICL7129 FROM A 3.8V TO 6V BAT-

The power connection for systems with +5V and -5V sup-

plies available is shown in Figure 13. Notice that measure-

ments are with respect to ground. COMMON is also tied to

INLO to remove any common-mode voltage swing on the

integrator amplifier inputs.

Again measurements are made with respect to COMMON

since the entire system is floating. Voltage doubling is

accomplished by using an ICL7660 CMOS voltage converter

and two inexpensive electrolytic capacitors. The same princi-

ple applies in Figure 15 where the ICL7129 is being used in

a system with only a single +5V power supply. Here mea-

surements are made with respect to power supply ground.

+5V

24

+5V

V+

24

34

REF HI

V+

0.1µF

ICL8089

34

35

28

33

ICL8089

0.1µF

REF LO

ICL7129

35

28

33

36

COM

ICL7129

DGND

36

8

IN HI

+

2

V

IN

+

V

32

IN

32

IN LO

3

0.1µF

4

5

-

10µF

V-

ICL7660

V-

23

10µF

+

-5V

FIGURE 13. POWERING THE ICL7129 FROM +5V AND -5V

FIGURE 15. POWERING THE ICL7129 FROM A SINGLE

POLARITY POWER SUPPLY

9

ICL7129

A single polarity power supply can be used to power the Integrate Resistor

ICL7129 in applications where battery operation is not

R

= V

/I

INFS INT

INT

appropriate or convenient only if the power supply is isolated

from system ground. Measurements must be made with

respect to COMMON or some other voltage within its input

common-mode range.

(Typ) = 150kΩ

Integrate Capacitor

(t )(I

)

INT INT

C

= ----------------------------------

INT

V

Voltage References

INT

Integrator Output Voltage Swing

The COMMON output of the ICL7129 has a temperature

coefficient of ±80ppm/ C typically. This voltage is only suit-

o

(t

)(I

)

INT INT

C

able as a reference voltage for applications where ambient

temperature variations are expected to be minimal. When

the ICL7129 is used in most environments, other voltage ref-

erences should be considered. The diagram in the Typical

Application Schematic and Figure 15 show the ICL8069

1.2V band-gap voltage source used as the reference for the

ICL7129, and the COMMON output as its pre-regulator. The

reference voltage for the ICL7129 is set to 1.000V for both

2V and 200mV full-scale operation.

V

= ----------------------------------

INT

V

Maximum Swing: (V- + 0.5V) < V

< (V+ - 0.7V)

INT

Display Count

V

IN

COUNT = 10, 000 × ----------------(Range = 1)

V

REF

(2V Range)

V

× 10

IN

COUNT = 10, 000 × ---------------------- (Range = 0)

(200mV Range)

V

REF

Multiple Integration A/D Converter

Equations

Minimum V

: 500mV

REF

Common Mode Input Voltage

(V- + 1V) < V < (V+ - 0.5V)

Oscillator Frequency

IN

f

= 0.45/RC

OSC

C

> 50pF; R > 50kΩ

OSC

(Typ) = 120kHz

OSC

Auto Zero Capacitor: C not used

AZ

f

OSC

or

Reference Capacitor: 0.1µF < C

< 1µF

REF

f

= 120kHz Crystal (Recommended)

OSC

Oscillator Period

= 1/f

V

COM

Biased Between V+ and V-.

V

≅ V+ -2.9V

COM

Regulation lost when V+ to V- < ≅ 6.4V.

t

OSC

Integration Clock Period

= 2*t

If V

V

is externally pulled down to (V+ to V-)/2, the

COM

circuit will turn off.

t

COM

CLOCK

OSC

Power Supply: Single 9V

Integration Period

V+ - V- = 9V

Digital supply is generated internally

t

= 1000*t

INT(200mV)

(Range = 1)

(Range = 0)

INT(2V)

CLOCK

= 10,000*t

CLOCK

V

≅ V+ - 4.5V

GND

60/50Hz Rejection Criterion

/t or t /t = Integer

Display: Triplexed LCD

t

INT 60Hz INT 50Hz

Continuity Output On if

Optimum Integration Current

= 13µA

V

to V

< 200mV

INHI

INLO

I

INT

Conversion Cycle (In Both Ranges)

= t x 30,000

Full Scale Analog Input Voltage

t

CYC

CLOCK

V

(Typ) = 200mV or 2V

INFS

ZERO-INTEGRATE

AND LATCH

INT

INTEGRATE

DE

1

DE-INTEGRATE REST X10 DE REST X10

2

DE ZERO-INTEGRATE

3

INTEGRATOR

RESIDUE

VOLTAGE

NOTE: Shaded area greatly expanded

in time and amplitude.

1000 CLOCKS

2000

CLOCKS

1000 CLOCKS

10,000 CLOCKS

10


型号：	ICL7129_00
厂家：	Intersil
描述：	4 Digit LCD, Single-Chip A/D Converter 4数字LCD ，单芯片A / D转换器转换器 CD
文件：	总10页 (文件大小：728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICL7129_00 [INTERSIL]

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