ICL7135 [INTERSIL]
4 1/2 Digit, BCD Output, A/D Converter; 4 1/2位， BCD输出， A / D转换器
| 型号： | ICL7135 |
| 厂家： | 
Intersil |
| 描述： | 4 1/2 Digit, BCD Output, A/D Converter |
| 文件： | 总15页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL7135
®
Data Sheet
October 25, 2004
FN3093.3
1
4 / Digit, BCD Output, A/D Converter
2
Features
The Intersil ICL7135 precision A/D converter, with its
multiplexed BCD output and digit drivers, combines dual-
slope conversion reliability with ±1 in 20,000 count accuracy
and is ideally suited for the visual display DVM/DPM market.
The 2.0000V full scale capability, auto-zero, and auto-
polarity are combined with true ratiometric operation, almost
ideal differential linearity and true differential input. All
necessary active devices are contained on a single CMOS
lC, with the exception of display drivers, reference, and a
clock.
• Accuracy Guaranteed to ±1 Count Over Entire ±20000
Counts (2.0000V Full Scale)
• Guaranteed Zero Reading for 0V Input
• 1pA Typical Input Leakage Current
• True Differential Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage Required
• Overrange and Underrange Signals Available for Auto-
Range Capability
The ICL7135 brings together an unprecedented combination
of high accuracy, versatility, and true economy. It features
• All Outputs TTL Compatible
o
auto-zero to less than 10µV, zero drift of less than 1µV/ C,
• Blinking Outputs Gives Visual Indication of Overrange
input bias current of 10pA (Max), and rollover error of less
than one count. The versatility of multiplexed BCD outputs is
increased by the addition of several pins which allow it to
operate in more sophisticated systems. These include
STROBE, OVERRANGE, UNDERRANGE, RUN/HOLD and
BUSY lines, making it possible to interface the circuit to a
microprocessor or UART.
• Six Auxiliary Inputs/Outputs are Available for Interfacing to
UARTs, Microprocessors, or Other Circuitry
• Multiplexed BCD Outputs
• Pb-Free Available (RoHS Compliant)
Pinout
Ordering Information
ICL7135
(PDIP)
TEMP.
PKG.
TOP VIEW
PART NUMBER
RANGE (°C)
PACKAGE
28 Ld PDIP
DWG. #
ICL7135CPI
0 to 70
0 to 70
E28.6
E28.6
V-
REFERENCE
NALOG COMMON
INT OUT
1
2
3
4
5
6
7
8
9
28 UNDERRANGE
27 OVERRANGE
26 STROBE
25 R/H
ICL7135CPIZ
(Note 1)
28 Ld PDIP
(Pb-free) (Note 2)
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.
AZ IN
24 DIGITAL GND
23 POL
BUFF OUT
REF CAP -
REF CAP +
IN LO
22 CLOCK IN
21 BUSY
20
(LSD) D1
IN HI 10
V+ 11
19 D2
2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
18 D3
(MSD) D5
12
17 D4
(LSB) B1 13
B2 14
16 (MSB) B8
15 B4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL7135
Typical Application Schematic
SET V
IN
= 1.000V
REF
CLOCK IN
120kHz
-5V
1
2
28
27
26
25
V
REF
100kΩ
ANALOG
GND
3
4
0.47µF
27Ω
0V
6
ANODE
DRIVER
DISPLAY
5
24
23
22
21
20
19
18
17
16
15
100kΩ
1µF
6
TRANSISTORS
100kΩ
1µF
7
ICL7135
8
100K
SIGNAL
INPUT
9
0.1µF
10
11
12
13
14
+5V
SEVEN
SEG.
DECODE
FN3093.3
2
ICL7135
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V
Thermal Resistance (Typical, Note 2) . . . . . . . . . . . . . θJA ( C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
o
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input). . . . . . . . . . . . . . . . . V+ to V-
Clock Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
Operating Conditions
NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to +100µA.
2. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
o
Electrical Specifications V+ = +5V, V- = -5V, T = 25 C, f
Set for 3 Readings/s, Unless Otherwise Specified
A
CLK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG (Notes 3, 4)
Zero Input Reading
V
V
= 0V, V
= 1.000V
-00000 +00000 +00000
Counts
Counts
LSB
lN
lN
REF
= 1.000V
Ratiometric Error (Note 4)
= V
-3
-
0
+3
1
REF
Linearity Over ± Full Scale (Error of Reading from Best Straight Line) -2V ≤ V ≤ +2V
IN
0.5
0.01
Differential Linearity (Difference Between Worse Case Step of
Adjacent Counts and Ideal Step)
-2V ≤ V ≤ +2V
IN
-
-
LSB
Rollover Error (Difference in Reading for Equal Positive and
Negative Voltage Near Full Scale)
-V ≡ +V ≈ 2V
lN lN
-
0.5
1
LSB
Noise (Peak-to-Peak Value Not Exceeded 95% of Time), e
V
V
V
V
= 0V, Full scale = 2.000V
= 0V
-
-
-
-
15
1
-
10
2
µV
N
lN
lN
lN
lN
Input Leakage Current, I
pA
ILK
Zero Reading Drift (Note 7)
o
o
o
= 0V, 0 C to 70 C
0.5
2
µV/ C
o
o
o
Scale Factor Temperature Coefficient, T (Notes 5 and 7)
C
= +2V, 0 C to 70 C
5
ppm/× C
o
Ext. Ref. 0ppm/ C
DIGITAL INPUTS
Clock In, Run/Hold (See Figure 2)
V
V
2.8
2.2
1.6
-
V
V
INH
INL
-
-
-
0.8
0.1
10
I
I
V
V
= 0V
0.02
0.1
mA
µA
INL
INH
IN
IN
= +5V
DIGITAL OUTPUTS
All Outputs, V
OL
I
I
I
= 1.6mA
= -1mA
= -10µA
-
0.25
4.2
0.40
V
V
V
OL
OH
OH
B1, B2, B4, B8, D1, D2, D3, D4, D5, V
OH
2.4
4.9
-
-
BUSY, STROBE, OVERRANGE, UNDERRANGE, POLARITY, V
SUPPLY
4.99
OH
+5V Supply Range, V+
+4
-3
-
+5
-5
+6
-8
V
V
-5V Supply Range, V-
+5V Supply Current, I+
f
f
= 0
1.1
0.8
40
3.0
3.0
-
mA
mA
pF
C
C
-5V Supply Current, I-
= 0
-
Power Dissipation Capacitance, C
CLOCK
vs Clock Frequency
-
PD
Clock Frequency (Note 6)
DC
2000
1200
kHz
NOTES:
1
3. Tested in 4 / digit (20.000 count) circuit shown in Figure 3. (Clock frequency 120kHz.)
2
4. Tested with a low dielectric absorption integrating capacitor, the 27Ω INT OUT resistor shorted, and R
= 0. See Component Value Selection Discussion.
lNT
o
5. The temperature range can be extended to 70 C and beyond as long as the auto-zero and reference capacitors are increased to absorb the higher leakage
of the ICL7135.
6. This specification relates to the clock frequency range over which the lCL7135 will correctly perform its various functions See “Max Clock Frequency”
section for limitations on the clock frequency range in a system.
7. Parameter guaranteed by design or characterization. Not production tested.
FN3093.3
3
ICL7135
SET V
= 1.000V
-5V
REF
ICL7135
V
IN
REF
1
2
V-
28
UNDERRANGE
REF
OVERRANGE 27
100kΩ
STROBE
3
26
ANALOG GND
ANALOG
GND
INT OUT
A-Z IN
RUN/HOLD 25
4
0.47µF
1µF
27Ω
DIGITAL GND
24
5
0V
100kΩ
BUF OUT POLARITY
REF CAP 1 CLOCK IN
6
23
22
21
20
19
18
17
16
15
+
V
CLOCK
IN
120kHz
100kΩ
7
1µF
REF CAP 2
IN LO-
IN HI+
V+
BUSY
LSD DI
D2
8
100K
SIGNAL
INPUT
9
0.1µF
+5V
10
11
12
13
14
PAD
D3
MSD D5
LSB B1
B2
D4
MSB B8
B4
DIG GND
FIGURE 1. ICL7135 TEST CIRCUIT
FIGURE 2. ICL7135 DIGITAL LOGIC INPUT
C
REF
R
C
C
INT
INT
INT
AZ
AUTO
ZERO
5
+
C
REF HI
2
C
V
BUFFER
REF+
REF
8
7
6
11
4
INTEGRATOR
-
+
ZERO-
CROSSING
DETECTOR
-
+
+
INPUT
HIGH
AZ
AZ
10
IN HI
COMPARATOR
POLARITY
F/F
DE(-)
DE(+)
INT
AZ
ZI
A/Z
INPUT
LOW
3
9
DE(+)
DE(-)
ANALOG
COMMON
A/Z, DE(±), ZI
INT
IN LO
1
-
V
FIGURE 3. ANALOG SECTION OF ICL7135
FN3093.3
4
ICL7135
However, since the integrator also swings with the common
Detailed Description
mode voltage, care must be exercised to assure the integrator
output does not saturate. A worst case condition would be a
large positive common-mode voltage with a near full scale
negative differential input voltage. The negative input signal
drives the integrator positive when most of its swing has been
used up by the positive common mode voltage. For these
critical applications the integrator swing can be reduced to
less than the recommended 4V full scale swing with some
loss of accuracy. The integrator output can swing within 0.3V
of either supply without loss of linearity.
Analog Section
Figure 3 shows the Block Diagram of the Analog Section for
the ICL7135. Each measurement cycle is divided into four
phases. They are (1) auto-zero (AZ), (2) signal-integrate
(INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).
Auto-Zero Phase
During auto-zero, three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
Analog COMMON
system to charge the auto-zero capacitor C to compensate
Analog COMMON is used as the input low return during auto-
zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system and
is taken care of by the excellent CMRR of the converter.
However, in most applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The reference voltage is referenced to analog
COMMON.
AZ
for offset voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop, the
AZ accuracy is limited only by the noise of the system. In any
case, the offset referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO for a
fixed time. This differential voltage can be within a wide
common mode range; within one volt of either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog COMMON
to establish the correct common-mode voltage. At the end of
this phase, the polarity of the integrated signal is latched into
the polarity F/F.
Reference
The reference input must be generated as a positive voltage
with respect to COMMON, as shown in Figure 4.
V+
De-Integrate Phase
6.8V
REF HI
ZENER
The third phase is de-integrate or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the inte-
grator output to return to zero. The time required for the out-
put to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
ICL7135
I
Z
COMMON
V-
FIGURE 4A.
V
IN
--------------
OUTPUT COUNT = 10,000
.
V
REF
V+
Zero Integrator Phase
The final phase is zero integrator. First, input low is shorted
to analog COMMON. Second, a feedback loop is closed
around the system to input high to cause the integrator
output to return to zero. Under normal condition, this phase
lasts from 100 to 200 clock pulses, but after an overrange
conversion, it is extended to 6200 clock pulses.
6.8kΩ
V+
20kΩ
ICL8069
1.2V
REFERENCE
REF HI
ICL7135
Differential Input
COMMON
The input can accept differential voltages anywhere within the
common mode range of the input amplifier; or specifically
from 0.5V below the positive supply to 1V above the negative
supply. In this range the system has a CMRR of 86dB typical.
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
FN3093.3
5
ICL7135
Digital Section
previous signal was overrange) but no additional STROBE
pulses will be sent until a new measurement is available.
Figure 5 shows the Digital Section of the ICL7135. The
ICL7135 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
BUSY (Pin 21)
BUSY goes high at the beginning of signal integrate and
stays high until the first clock pulse after zero crossing (or
after end of measurement in the case of an overrange). The
internal latches are enabled (i.e., loaded) during the first
clock pulse after busy and are latched at the end of this clock
pulse. The circuit automatically reverts to auto-zero when not
BUSY, so it may also be considered a (Zl + AZ) signal. A
very simple means for transmitting the data down a single
wire pair from a remote location would be to AND BUSY with
clock and subtract 10,001 counts from the number of pulses
received - as mentioned previously there is one “NO-count”
pulse in each reference integrate cycle.
Run/HOLD (Pin 25)
When high (or open) the A/D will free-run with equally
spaced measurement cycles every 40,002 clock pulses. If
taken low, the converter will continue the full measurement
cycle that it is doing and then hold this reading as long as
R/H is held low. A short positive pulse (greater than 300ns)
will now initiate a new measurement cycle, beginning with
between 1 and 10,001 counts of auto zero. If the pulse
occurs before the full measurement cycle (40,002 counts) is
completed, it will not be recognized and the converter will
simply complete the measurement it is doing. An external
indication that a full measurement cycle has been completed
is that the first strobe pulse (see below) will occur 101 counts
after the end of this cycle. Thus, if Run/HOLD is low and has
been low for at least 101 counts, the converter is holding and
ready to start a new measurement when pulsed high.
OVERRANGE (Pin 27)
This pin goes positive when the input signal exceeds the
range (20,000) of the converter. The output F/F is set at the
end of BUSY and is reset to zero at the beginning of
reference integrate in the next measurement cycle.
STROBE (Pin 26)
UNDERRANGE (Pin 28)
This is a negative going output pulse that aids in transferring
the BCD data to external latches, UARTs, or
This pin goes positive when the reading is 9% of range or
less. The output F/F is set at the end of BUSY (if the new
reading is 1800 or less) and is reset at the beginning of
signal integrate of the next reading.
microprocessors. There are 5 negative going STROBE
pulses that occur in the center of each of the digit drive
pulses and occur once and only once for each measurement
cycle starting 101 clock pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at the end of
the measurement cycle and stays on for 201 counts. In the
center of this digit pulse (to avoid race conditions between
POLARlTY (Pin 23)
This pin is positive for a positive input signal. It is valid even
for a zero reading. In other words, +0000 means the signal is
positive but less than the least significant bit. The converter
can be used as a null detector by forcing equal frequency of
(+) and (-) readings. The null at this point should be less than
0.1 LSB. This output becomes valid at the beginning of
reference integrate and remains correct until it is revalidated
for the next measurement.
changing BCD and digit drives) the first STROBE pulse goes
1
negative for / clock pulse width. Similarly, after digit 5, digit
2
4 goes high (for 200 clock pulses) and 100 pulses later the
STROBE goes negative for the second time. This continues
through digit 1 (LSD) when the fifth and last STROBE pulse
is sent. The digit drive will continue to scan (unless the
+
POLARITY
23
V
D5
12
D4
17
D3
18
D2
D1
11
19
20
13
14
15
16
B1
B2
B4
B8
MSB
LSB
ANALOG
SECTION
MULTIPLEXER
POLARITY
FF
LATCH
LATCH
LATCH
LATCH
LATCH
ZERO
CROSS.
DET.
COUNTERS
CONTROL LOGIC
24
22
25
27
28
26
21
DIGITAL
GND
CLOCK
IN
RUN/
HOLD
OVER UNDER
RANGE RANGE
BUSY
STROBE
FIGURE 5. DIGITAL SECTION OF THE ICL7135
FN3093.3
6
ICL7135
Digit Drives (Pins 12, 17, 18, 19 and 20)
Auto-Zero and Reference Capacitor
Each digit drive is a positive going signal that lasts for 200 clock
pulses. The scan sequence is D5 (MSD), D4, D3, D2, and D1
(LSD). All five digits are scanned and this scan is continuous
unless an overrange occurs. Then all digit drives are blanked
from the end of the strobe sequence until the beginning of
Reference Integrate when D5 will start the scan again. This can
give a blinking display as a visual indication of overrange.
The physical size of the auto-zero capacitor has an influence
on the noise of the system. A larger capacitor value reduces
system noise. A larger physical size increases system noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference cap and auto-zero
cap are only important at power-on or when the circuit is
recovering from an overload. Thus, smaller or cheaper caps
can be used here if accurate readings are not required for
the first few seconds of recovery.
BCD (Pins 13, 14, 15 and 16)
The Binary coded Decimal bits B8, B4, B2, and B1 are
positive logic signals that go on simultaneously with the digit
driver signal.
Reference Voltage
The analog input required to generate a full scale output is
Component Value Selection
V
= 2V .
REF
lN
For optimum performance of the analog section, care must
be taken in the selection of values for the integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommended that a high quality reference be used where
high-accuracy absolute measurements are being made.
Rollover Resistor and Diode
Integrating Resistor
A small rollover error occurs in the ICL7135, but this can be
easily corrected by adding a diode and resistor in series
between the INTegrator OUTput and analog COMMON or
ground. The value shown in the schematics is optimum for
the recommended conditions, but if integrator swing or clock
frequency is modified, adjustment may be needed. The
diode can be any silicon diode such as 1N914. These
components can be eliminated if rollover error is not
important and may be altered in value to correct other
(small) sources of rollover as needed.
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. Both the buffer amplifier and the
integrator have a class A output stage with 100µA of
quiescent current. They can supply 20µA of drive current
with negligible non-linearity. Values of 5µA to 40µA give
good results, with a nominal of 20µA, and the exact value of
integrating resistor may be chosen by:
full scale voltage
R
= ------------------------------------------- .
INT
20µA
Max Clock Frequency
Integrating Capacitor
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3µs delay, and at a clock frequency of
160kHz (6µs period) half of the first reference integrate clock
period is lost in delay. This means that the meter reading will
change from 0 to 1 with a 50µV input, 1 to 2 with a 150µV
input, 2 to 3 with a 250µV input, etc. This transition at mid-
point is considered desirable by most users; however, if the
clock frequency is increased appreciably above 160kHz, the
instrument will flash “1” on noise peaks even when the input
is shorted.
The product of integrating resistor and capacitor should be
selected to give the maximum voltage swing which ensures
that the tolerance built-up will not saturate the integrator
swing (approx. 0.3V from either supply). For ±5V supplies
and analog COMMON tied to supply ground, a ±3.5V to ±4V
full scale integrator swing is fine, and 0.47µF is nominal. In
general, the value of C
is given by:
lNT
,
× I
10,000 × clock period
---------------------------------------------------------------------------------
=
INT
C
INT
integrator output voltage swing
(10,000) (clock period) (20µA)
.
= ---------------------------------------------------------------------------------
integrator output voltage swing
For many dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non-linearity and noise do not
increase substantially with frequency, clock rates of up to
~1MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be constant
and can be subtracted out digitally.
A very important characteristic of the integrating capacitor is
that it has low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale 0.9999, and
any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.
The clock frequency may be extended above 160kHz without
this error, however, by using a low value resistor in series
FN3093.3
7
ICL7135
with the integrating capacitor. The effect of the resistor is to
shown in the Typical Applications section. The multiplexed
output means that if the display takes significant current from
the logic supply, the clock should have good PSRR.
introduce a small pedestal voltage on to the integrator output
at the beginning of the reference integrate phase. By careful
selection of the ratio between this resistor and the integrating
resistor (a few tens of ohms in the recommended circuit), the
comparator delay can be compensated and the maximum
clock frequency extended by approximately a factor of 3. At
higher frequencies, ringing and second order breaks will
cause significant non-linearities in the first few counts of the
instrument. See Application Note AN017.
Zero-Crossing Flip-Flop
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by up to one count in every instance, and
if a correction were not made, the display would always be
one count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one-count
delay compensates for the delay of the zero-crossing
flip-flop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
phase 1 gives an overload display of 0000 instead of 0001.
No delay occurs during phase 2, so that true ratiometric
readings result.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices,
measurement cycles as long as 10s give no measurable
leakage error.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
1
40kHz, 33 / kHz, etc. should be selected. For 50Hz
3
2
rejection, oscillator frequencies of 250kHz, 166 / kHz,
3
Evaluating The Error Sources
Errors from the “ideal” cycle are caused by:
125kHz, 100kHz, etc. would be suitable. Note that 100kHz
(2.5 readings/sec) will reject both 50Hz and 60Hz.
1. Capacitor droop due to leakage.
2. Capacitor voltage change due to charge “suck-out” (the
reverse of charge injection) when the switches turn off.
INTEGRATOR
OUTPUT
AUTO SIGNAL REFERENCE
3. Non-linearity of buffer and integrator.
ZERO
10,001/ 10,000/
INT.
INTEGRATE
20,001/
4. High-frequency limitations of buffer, integrator, and
comparator.
COUNTS COUNTS COUNTS MAX.
FULL MEASUREMENT
CYCLE 40,002 COUNTS
5. Integrating capacitor non-linearity (dielectric absorption).
BUSY
6. Charge lost by C
in charging C
.
REF
STRAY
to charge C
OVER-RANGE
WHEN APPLICABLE
7. Charge lost by C and C
.
STRAY
AZ lNT
UNDER-RANGE
WHEN APPLICABLE
Each error is analyzed for its error contribution to the
converter in application notes listed on the back page,
specifically Application Note AN017 and Application Note
AN032.
EXPANDED SCALE
BELOW
DIGIT SCAN
FOR OVER-RANGE
D5
D4
D3
D2
D1
Noise
The peak-to-peak noise around zero is approximately 15µV
(peak-to-peak value not exceeded 95% of the time). Near full
scale, this value increases to approximately 30µV. Much of
the noise originates in the auto-zero loop, and is proportional
to the ratio of the input signal to the reference.
1000†/
†FIRST D5 OF AZ AND
COUNTS
REF INT ONE COUNT LONGER
STROBE
AUTO ZERO
SIGNAL INTEGRATE
REFERENCE
INTEGRATE
DIGIT SCAN
FOR OVER-RANGE
D5
D4
D3
D2
D1
Analog And Digital Grounds
Extreme care must be taken to avoid ground loops in the
layout of ICL7135 circuits, especially in high-sensitivity
circuits. It is most important that return currents from digital
loads are not fed into the analog ground line.
FIGURE 6. TIMING DIAGRAM FOR OUTPUTS
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
FN3093.3
8
ICL7135
decoder. The 2-gate clock circuit should use CMOS gates to
maintain good power supply rejection.
Power Supplies
The ICL7135 is designed to work from ±5V supplies.
However, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
A suitable circuit for driving a plasma-type display is shown
in Figure 8. The high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving “BI” are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted if not needed. The 2.5kΩ and 3kΩ resistors
set the current levels in the display. A similar arrangement
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5V.
®
See “differential input” for a discussion of the effects this will
have on the integrator swing without loss of linearity.
can be used with Nixie tubes.
The popular LCD displays can be interfaced to the outputs of
the ICL7135 with suitable display drivers, such as the
Typical Applications
ICM7211A as shown in Figure 9. A standard CMOS 4030
1
The circuits which follow show some of the wide variety of
possibilities and serve to illustrate the exceptional versatility
of this A/D converter.
QUAD XOR gate is used for displaying the / digit, the
2
polarity, and an “overrange” flag. A similar circuit can be
used with the ICL7212A LED driver and the ICM7235A
vacuum fluorescent driver with appropriate arrangements
made for the “extra” outputs. Of course, another full driver
circuit could be ganged to the one shown if required. This
1
Figure 7 shows the complete circuit for a 4 / digit (±2.000V)
2
full scale) A/D with LED readout using the ICL8069 as a
1.2V temperature compensated voltage reference. It uses
the band-gap principal to achieve excellent stability and low
noise at reverse currents down to 50µA. The circuit also
shows a typical R-C input filter. Depending on the
would be useful if additional annunciators were needed. The
1
Figure shows the complete circuit for a 4 / digit (±2.000V)
2
A/D.
application, the time-constant of this filter can be made
1
Figure 10 shows a more complicated circuit for driving LCD
displays. Here the data is latched into the ICM7211 by the
STROBE signal and “Overrange” is indicated by blanking the
4 full digits.
faster, slower, or the filter deleted completely. The / digit
2
LED is driven from the 7 segment decoder, with a zero
reading blanked by connecting a D5 signal to RBl input of the
+5V
+5V
-5V
6.8kΩ
5
4
3
2
1
V
=
REF
1.000V
(NOTE 1)
27Ω
1
2
28
27
26
25
V-
UR
OR
150Ω
ICL7135
7447
ICL8069
1
2
REF
ANALOG
COMMON
150Ω
10kΩ
150Ω
A
B
C
D
E
3
STROBE
R/H
ANALOG
GND
B1
B2
B4
B8
4
INT OUT
4.7K
0.47µF
1µF
5
DIG. GND 24
POL 23
AZ
IN
100kΩ
6
BUF OUT
RC1
F
G
100kΩ
1µF
7
CLOCK 22
BUSY 21
D1 20
100K
RBI
SIGNAL
INPUT
8
RC2
9
INPUT LO
INPUT HI
0.1µF
47K
10
11
12
13
14
19
18
17
16
15
D2
D3
D4
B8
B4
+5V
V+
D5
B1
B2
C
RC NETWORK
ƒOSC = 0.45/RC
R
NOTE:
1. For finer resolution on scale factor adjust, use a 10 turn pot or a small pot in series with
a fixed resistor.
1
FIGURE 7. 4 / DIGIT A/D CONVERTER WITH A MULTIPLEXED COMMON ANODE LED DISPLAY
2
FN3093.3
9
ICL7135
This shift occurs during the reference integrate phase of
A
G
+
A
V
+5
conversion causing a low display reading just after overrange
recovery. Both of the above circuits have considerable current
flowing in the digital supply from drivers, etc. A clock source
using an LM311 voltage comparator with positive feedback
(Figure 11) could minimize any clock frequency shift problem.
POL
3K
DM
8880
RB0
BI
G
RBI
PROG
D A
0V
HI VOLTAGE BUFFER D1 505
+5V
47K
0.02µF
5K
The ICL7135 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated with an ICL7660 and two capacitors (Figure 12).
2.5K
GATES
ARE
7409
Interfacing with UARTs and
Microprocessors
Figure 13 shows a very simple interface between a free-running
ICL7135 and a UART. The five STROBE pulses start the
transmission of the five data words. The digit 5 word is
0000XXXX, digit 4 is 1000XXXX, digit 3 is 0100XXXX, etc. Also
the polarity is transmitted indirectly by using it to drive the Even
Parity Enable Pin (EPE). If EPE of the receiver is held low, a
parity flag at the receiver can be decoded as a positive signal,
no flag as negative. A complex arrangement is shown in Figure
14. Here the UART can instruct the A/D to begin a
0.02µF
D1
POL D5
B8
B1
V+
ICL7135
+5
0V
DGND
FIGURE 8. ICL7135 PLASMA DISPLAY CIRCUIT
1
+5V
4 / DIGIT LCD DISPLAY
2
measurement sequence by a word on RRl. The BUSY signal
resets the Data Ready Reset (DRR). Again STROBE starts the
transmit sequence. A quad 2 input multiplexer is used to
superimpose polarity, over-range, and under-range onto the D5
word since in this instance it is known that B2 = B4 = B8 = 0.
BP
1
/
CD4030
23 POL
2
5 BP
CD4081
20 D1
1/4 CD4030
31 D1
32 D2
For correct operation it is important that the UART clock be fast
enough that each word is transmitted before the next STROBE
pulse arrives. Parity is locked into the UART at load time but
does not change in this connection during an output stream.
19 D2
18 D3
17 D4
33 D3
34 D4
Circuits to interface the ICL7135 directly with three popular
microprocessors are shown in Figure 15 and Figure 16. The
8080/8048 and the MC6800 groups with 8-bit buses need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 Sword - as in the UART circuit. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.
CD4071
16 B8
15 B4
30 B3
29 B2
14 B2
13 B1
28 B1
27 B0
12 D5
CD4011
ICM7211A
Application Notes
26 STROBE
27 OR
AnswerFAX
NOTE #
DESCRIPTION
DOC. #
ICL7135
AN016 “Selecting A/D Converters”
9016
+5V
AN017 “The Integrating A/D Converter”
9017
1
/
CD4030
4
AN018 “Do’s and Don’ts of Applying A/D
Converters”
9018
FIGURE 9. LCD DISPLAY WITH DIGIT BLANKING ON
OVERRANGE
AN023 “Low Cost Digital Panel Meter Designs”
9023
9028
AN028 “Building an Auto-Ranging DMM Using
the 8052A/7103A A/D Converter Pair”
A problem sometimes encountered with both LED and plasma-
type display driving is that of clock source supply line variations.
Since the supply is shared with the display, any variation in
voltage due to the display reading may cause clock supply
voltage modulation. When in overrange the display alternates
between a blank display and the 0000 overrange indication.
AN030 “The ICL7104 - A Binary Output A/D
Converter for Microprocessors”
9030
9032
AN032 “Understanding the Auto-Zero and
Common Mode Performance of the
ICL7136/7/9 Family”
FN3093.3
10
ICL7135
1
4 / DIGIT LCD DISPLAY
2
REF
28 SEGMENTS D1-D4
VOLTAGE
+5V
-5V
1
2
3
4
5
6
7
8
9
V-
UR 28
OR 27
ICL7135
REF
ANALOG
COMMON
1 16151412 5 3 4
CD4054A
STROBE 26
R/H 25
7
8 131110 9 2 6
27Ω
INT OUT
ANALOG
GND
0.47µF
1µF
DIG. GND 24
POL 23
CLOCK 22
BUSY 21
D1 20
AZ
IN
BACKPLANE
100kΩ
BUF OUT
RC1
120kC = 3 READINGS/SEC
CLOCK IN
100kΩ
1µF
RC2
5BP
ICM7211A
31 D1
32 D2
33 D3
34 D4
30 B3
29 B2
INPUT LO
100kΩ
10 INPUT HI
11
D2 19
INPUT
0.1µF
2,3,4
6-26
37-40
+5V
D3 18
V+
12 D5
13 B1
14 B2
D4 17
B8 16
OPTIONAL
CAPACITOR
B4 15
OSC 36
V+ 1
+5V
28 B1
27 B0
35 V-
22-100pF
300pF
0V
+5V
FIGURE 10. DRIVING LCD DISPLAYS
+5V
16kΩ
1kΩ
56kΩ
+5V
1
2
3
4
8
8
+
2
7
7
6
5
LM311
0.22µF
+
ICL7660
1
-
10µF
4
30kΩ
3
-
V
= -5V
OUT
16kΩ
-
+
390pF
10µF
FIGURE 11. LM311 CLOCK SOURCE
FIGURE 12. GENERATING A NEGATIVE SUPPLY FROM +5V
FN3093.3
11
ICL7135
TRO
IM6402/3
TBR
RRI
DRR
SERIAL OUTPUT
TO RECEIVING UART
DR
TBRL
EPE
TRO
1
2
3
4
5
6
7
8
UART
IM6402/3
EPE
TBRL
8
1Y 2Y 3Y
ENABLE
TBR
74C157
1A 2A 3A
1B 2B 3B
1
2
3
4
5
6
7
D4
D5
D3 D2
D1 B1 B2 B4 B8
D4 D3 D2 D1 B1 B2 B4 B8
NC
STROBE
ICL7135
D5
ICL7135
STROBE
RUN/HOLD
BUSY
RUN/HOLD
+5V
POL
+5V
10K
100pF
FIGURE 13. ICL7135 TO UART INTERFACE
FIGURE 14. COMPLEX ICL7135 TO UART INTERFACE
1Y
2Y
3Y
PA0
PA1
PA2
1Y
2Y
3Y
PA0
PA1
PA2
EN
EN
74C157
74C157
80C48
MC680X
OR
MCS650X
1B 2B 3B
1A 2A 3A
1B 2B 3B
1A 2A 3A
8080
8085,
ETC.
PA3
PA3
MC6820
8255
(MODE1)
D5 B8 B4 B2B1
D1
D5 B8 B4 B2B1
D1
PA4
PA5
PA6
PA7
PA4
ICL7135
ICL7135
D2
D2
PA5
PA6
PA7
D3
D3
RUN/
RUN/
D4
HOLD STROBE
D4
HOLD STROBE
CA1 CA2
STB PB0
A
FIGURE 15. ICL7135 TO MC6800, MCS650X INTERFACED
FIGURE 16. ICL7135 TO MCS-48, -80, -85 INTERFACE
FN3093.3
12
ICL7135
Design Information Summary Sheet
• CLOCK INPUT
• DISPLAY COUNT
V
IN
The ICL7135 does not have an internal oscillator. It
requires an external clock.
----------------
COUNT = 10, 000 ×
V
REF
f
(Typ) = 120kHz
CLOCK
• CLOCK PERIOD
= 1/f
• CONVERSION CYCLE
= t x 40002
t
CYC
when f
CL0CK
= 120kHz, t
t
= 333ms
CYC
CLOCK
• INTEGRATION PERIOD
= 10,000 x t
CLOCK
CLOCK
• COMMON MODE INPUT VOLTAGE
t
(V- + 1V) < V < (V+ - 0.5V)
lN
INT
• 60/50Hz REJECTION CRITERION
/t or t /t = Integer
CLOCK
• AUTO-ZERO CAPACITOR
t
0.01µF < C < 1µF
INT 60Hz INT 50Hz
AZ
• OPTIMUM INTEGRATION CURRENT
= 20µA
• REFERENCE CAPACITOR
I
0.1µF < C
REF
< 1µF
INT
• FULL-SCALE ANALOG INPUT VOLTAGE
(Typ) = 200mV or 2V
• POWER SUPPLY: DUAL ±5V
V
V+ = +5V to GND
V- = -5V to GND
lNFS
• INTEGRATE RESISTOR
V
• OUTPUT TYPE
INFS
R
= ----------------
INT
I
INT
4 BCD Nibbles with Polarity and Overrange Bits
• INTEGRATE CAPACITOR
There is no internal reference available on the ICL7135. An
1
external reference is required due to the ICL7135’s 4 /
2
(t
)(I
)
INT INT
V
C
= -------------------------------
digit resolution.
INT
INT
• INTEGRATOR OUTPUT VOLTAGE SWING
(t
)(I
)
INT INT
C
V
= -------------------------------
INT
INT
• V
MAXIMUM SWING:
INT
(V- + 0.5) < V
< (V+ - 0.5V)
Typically = 2.7V
INT
V
INT
Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE
(COUNTS)
INTEGRATE
PHASE FIXED
10000 COUNTS
DE-INTEGRATE PHASE
1 - 20001 COUNTS
30001 - 10001
TOTAL CONVERSION TIME = 40002 x t
CLOCK
FN3093.3
13
ICL7135
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride/Silox Sandwich
(120 mils x 130 mils) x 525µm ±25µm
Thickness: 8k Nitride over 7k Silox
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
Metallization Mask Layout
ICL7135
REF
CAP+
REF
CAP+
BUFF
OUT
AZ
IN
V+
IN HI
IN LO
INT OUT
ANALOG COMMON
REFERENCE
(MSD) D5
V-
(LSB) B1
B2
UNDERRANGE
OVERRANGE
B4
(MSB) B8
D4
D3
STROBE
D2
(LSD)D1 BUSY
CLOCK IN POL DIGITAL
GND
R/H
FN3093.3
14
ICL7135
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3093.3
15
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