HSP48410GC-33_技术文档

HSP48410

Data Sheet

May 1999

File Number 3185.2

Histogrammer/Accumulating Buffer

Features

The Intersil HSP48410 is an 84 lead Histogrammer IC

intended for use in image and signal analysis. The on-board

memory is conﬁgured as 1024 x 24 array. This translates to

a pixel resolution of 10 bits and an image size of 4k x 4k with

no possibility of overﬂow.

• 10-Bit Pixel Data

• 4k x 4k Frame Sizes

• Asynchronous Flash Clear Pin

• Single Cycle Memory Clear

In addition to Histogramming, the HSP48410 can generate

and store the Cumulative Distribution Function for use in

Histogram Equalization applications. Other capabilities of

the HSP48410 include: Bin Accumulation, Look Up Table,

24-bit Delay Memory, and Delay and Subtract mode.

• Fully Asynchronous 16 or 24-Bit Host Interface

• Generates and Stores Cumulative Distribution Function

• Look Up Table Mode

• 1024 x 24-Bit Delay Memory

A Flash Clear pin is available in all modes of operation and

performs a single cycle reset on all locations of the internal

memory array and all internal data paths.

• 24-Bit Three State I/O Bus

• DC to 40MHz Clock Rate

The HSP48410 includes a fully asynchronous interface

which provides a means for communications with a host,

such as a microprocessor. The interface includes dedicated

Read/Write pins and an address port which are

asynchronous to the system clock. This allows random

access of the Histogram Memory Array for analysis or

conditioning of the stored data.

Applications

• Histogramming

• Histogram Equalization

• Image and Signal Analysis

• Image Enhancement

• RGB Video Delay Line

Ordering Information

TEMP.

PKG.

NO.

o

PART NUMBER RANGE ( C)

PACKAGE

84 Ld PLCC

HSP48410JC-33

HSP48410JC-40

HSP48410GC-33

HSP48410GC-40

0 to 70

N84.1.15

G84.A

84 Ld PLCC

84 Ld PGA

G84.A

Block Diagram

24

HISTOGRAM

MEMORY

ARRAY

DATA

OUT

DIO0-23

24

DIO

DATA

IN

ADDER

MUX

INTERACE

24

DIN0-23

10

ADDRESS

PIN0-9

ADDRESS

10

GENERATOR

IOADD0-9

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HSP48410

Pinouts

84 PGA

TOP VIEW

11

10

9

DIN8

DIN5

DIN4

DIN2

PIN9

DIN10

DIN7

DIN6

DIN3

DIN0

DIN1

PIN7

PIN4

PIN1

FC

DIN11

DIN9

DIN13

DIN12

DIN16

DIN17

DIN21

GND

DIN19

DIN20

DIN18

DIN22

DIN23

DIO23

DIO21

DIO22

DIO20

DIO18

DIO15

DIO12

DIO8

DIO19

DIO17

DIO16

DIO14

DIO11

DIO13

GND

DIN15

DIN14

8

7

GND

CLK

PIN6

DIO10

DIO9

DIO6

6

V

CC

5

PIN8

PIN5

PIN3

PIN2

DIO7

4

DIO4

DIO5

3

FCT0 IOADD9 IOADD8

DIO1

DIO3

2

RD

FCT2

WR

UWS IOADD6 IOADD3 IOADD0

DIO0

DIO2

1

PIN0

A

START

B

LD

C

FCT1

D

GND

E

IOADD5 IOADD7 IOADD4 IOADD IOADD1

V

CC

PIN ‘A1’

ID

F

G

H

J

K

L

84 PGA

BOTTOM VIEW

DIO19

DIO22

DIO23

DIN22

DIN19

DIN20

DIN18

DIN17

DIN21

GND

DIN16

DIN15

DIN14

DIN13

DIN12

DIN11

DIN9

DIN10

DIN7

DIN6

DIN3

DIN0

DIN1

PIN7

PIN4

PIN1

FC

DIN8

DIN5

DIN4

DIN2

PIN9

11

10

9

DIO17 DIO20

DIO16 DIO18

DIO14 DIO15

DIO11 DIO12

DIO21

DIN23

8

DIO10

DIO9

DIO6

GND

CLK

PIN6

7

DIO13

GND

DIO5

DIO3

DIO2

DIO8

DIO7

DIO4

DIO1

DIO0

V

6

CC

PIN8

PIN5

PIN3

PIN2

5

4

IOADD8 IOADD9 FCT0

3

IOADD0 IOADD3 IOADD6

UWS

WR

FCT2

RD

2

V

IOADD1 IOADD2 IOADD4 IOADD7 IOADD5 GND

FCT1

H

LD

J

START

K

PIN0

L

1

CC

A

B

C

D

E

F

G

2

HSP48410

Pinouts (Continued)

84 LEAD PLCC

11 10

9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

FC

RD

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

DIN8

DIN9

START

LD

DIN10

DIN11

DIN12

DIN13

DIN14

DIN15

DIN16

DIN17

GND

FCT2

FCT1

FCT0

WR

GND

UWS

IOADD9

IOADD8

IOADD7

IOADD6

IOADD5

IOADD4

IOADD3

IOADD2

IOADD1

IOADD0

DIN18

DIN19

DIN20

DIN21

DIN22

DIN23

DIO23

DIO22

DIO21

DIO20

V

CC

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

3

HSP48410

Pin Description

NAME

PLCC PIN

TYPE

DESCRIPTION

CLK

1

I

Clock Input. This input has no effect on the chips functionality when the chip is programmed

to an asynchronous mode. All signals denoted as synchronous have their timing specified

with reference to this signal.

PIN0-9

3-11, 83

I

Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM

with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchro-

nous modes it is unused.

LD

15

I

The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below).

FCT0-2

16-18

These three pins are decoded to determine the mode of operation for the chip. The signals

are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the

loading of this function is asynchronous to CLK, it is necessary to disable the START pin dur-

ing loading and enable START at least 1 CLK cycle following the LD pulse.

START

14

I

This pin informs the on-chip circuitry which clock cycle will start and/or stop the current mode

of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously

started and stopped. This input is sampled by the rising edge of CLK. The actual function of

this input depends on the mode that is selected. START must always be held high (disabled)

when changing modes. This will provide a smooth transition from one mode to the next by

allowing the part to reconfigure itself before a new mode begins. When START is high,

LUT(read) mode is enabled except for Delay and Delay and Subtract modes.

FC

12

I

Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits

in the RAM Array and the input and output data paths to zero.

DIN0-23

DIO0-23

58-63,

65-82

Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and

Delay and Subtract modes. Synchronous to CLK.

33-40,

42-57

I/O

Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the

memory array and reading the results of the previous operation. Configurable as either a 24

or 16-bit bus.

IOADD0-9

UWS

22-31

21

I

RAM address in asynchronous modes. Sampled on the falling edge of WR or RD.

Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of

DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means

that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect.

WR

RD

19

13

I

Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one

of the asynchronous modes. Asynchronous to CLK.

Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23

in other modes. Asynchronous to CLK.

V

2, 32

+5V. 0.1µF capacitors between the V

and GND pins are recommended.

CC

GND

NOTES:

CC

20, 41, 64, 84

Ground

1. An overbar denotes an active low signal.

2. Bit 0 is the LSB on all busses.

4

HSP48410

DIO Interface

Functional Description

The DIO Interface Section transfers data between the

Histogrammer and the outside world. In the synchronous

modes, DIO acts as a synchronous output for the data

currently being processed by the chip; RD acts as the output

enable for the DIO bus; WR and IOADD0-9 have no effect.

When either of the Asynchronous modes are selected (16 or

24-bit), the RAM output is passed directly to the DIO bus on

read cycles, and on write cycles, data input on DIO goes to

the RAM input port. In this case, data reads and writes are

controlled by RD, WR and IOADD0-9.

The Histogrammer is intended for use in signal and image

processing applications. The on-board RAM is 24 bits by

1024 locations. For histogramming, this translates to an

image size of 4k x 4k with 10-bit data. A Functional Block

Diagram of the part is shown in Figure 1.

In addition to histogramming, the HSP48410 will also

perform Histogram Accumulation while feeding the results

back into the memory array. The on-board RAM will then

contain the Cumulative Distribution Function and can be

used for further operation such as histogram equalization.

Function Decode

Other modes are: Bin Accumulate, Look Up Table (LUT),

Delay Memory, and Delay and Subtract. The part can also

be accessed as a 24-bit by 1024 word asynchronous RAM

for preconditioning or reading the results of the histogram.

This section provides the signals needed to conﬁgure the

part for the different modes. The eight modes are decoded

from FCT0-2 on the rising edge of LD (see Table 1). The

output of this section is a set of signals which control the

path of data through the part.

The Histogrammer can be accessed both synchronously

and asynchronously to the system clock (CLK). It was

designed to be conﬁgured asynchronously by a

microprocessor, then switched to a synchronous mode to

process data. The result of the processing can then be read

out synchronously, or the part can be switched to one of the

asynchronous modes so the data may be read out by a

microprocessor. All modes are synchronous except for the

Asynchronous 16 and 24 modes.

The mode should only be changed while START is high.

After changing from one mode to another, START must be

clocked high by the rising edge of CLK at least once.

TABLE 1. FUNCTION DECODE

FCT

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE

A Flash Clear operation allows the user to reset the entire

RAM array and all input and output data paths in a single

cycle.

Histogram

Histogram Accumulate

Delay and Subtract

Look Up Table

Histogram Memory Array

The Histogram Memory Array is a 24-bit by 1024 deep RAM.

Depending on the current mode, its input data comes from

either the synchronous input DIN0-23, from the

asynchronous data bus DIO0-23, or from the output of the

adder. The output data goes to the DIO bus in both

synchronous and asynchronous modes.

Bin Accumulate

Delay Memory

Asynchronous 24

Asynchronous 16

Address Generator

This section of the circuit determines the source of the RAM

address. In the synchronous modes, the address is taken

from either the output of the counter or PIN0-9. The pixel

input bus is used for Histogram, Bin Accumulate, and

LUT(read) modes. All other synchronous modes, i.e.

Histogram Accumulate, LUT(write), Delay, and Delay and

Subtract use the counter output. The counter is reset on the

ﬁrst rising edge of CLK after a falling edge on START.

Flash Clear

Flash Clear allows the user to clear the entire RAM with a

single pin. When the FC pin is low, all bits of the RAM and

the data path from the RAM to DIO0-23 are set to zero. The

FC pin is asynchronous with respect to CLK: the reset

begins immediately following a low on this signal. For

synchronous modes, in order to ensure consistent results,

FC should only be active while START is high. For

asynchronous modes, WR must remain inactive while FC

is low.

During asynchronous modes, the read and write addresses

to the RAM are taken from the IOADD bus on the falling

edge of the RD and WR signals, respectively.

Adder Input

The Adder Input Control Section contains muxes, registers

and other logic that provide the proper data to the adder. The

conﬁguration of this section is controlled by the output of the

Function Decode Section.

5

HSP48410

Functional Block Diagram

DIO 0-23

DIO

I/F

MUX

24X1024

RAM

IN

OUT

MUX

DIN 0-23

ADDRESS

ADDER

INPUT

CONTROL

∑

IOADD 0-9

PIN 0-9

ADDRESS

GENERATOR

COUNTER

CLK

WR

RD

TO ADDRESS GENERATOR

TO OUTPUT STAGE

TO RAM

UWS

CONTROL

START

FC

FCT 0-2

LD

MUX

CONTROL

SIGNALS

FUNCTION

DECODE

ALL REGISTERS ARE CLOCKED BY CLK

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

At the same time, the new value is also displayed on the DIO

bus. This procedure continues until the circuit is interrupted

by START returning high. When START is high, the RAM

write is disabled, the read address is taken from the Pixel

Input bus, and the chip acts as if it is in LUT(read) mode.

Figure 3 shows histogram mode timing. START is used to

disregard the data on PIN0-9 at DATA2. START is sampled

on the rising edge of clock, but is delayed internally by 3

cycles to match the latency of the Address Generator. Data

is clocked onto the DIO bus on the rising edge of CLK. RD

acts as output enable.

Histogram Mode

This is the fundamental operation for which this chip was

intended. When this mode is selected, the chip conﬁgures

itself as shown in the Block Diagram of Figure 2. The pixel

data is sampled on the rising edge of clock and used as the

read address to the RAM array. The data contained in that

address (or bin) is then incremented by 1 and written back

into the RAM at the same address.

RAM

IN

OUT

WR

DIO

0-23

DIO

I/F

ADDRESS

CLK

S

“0”

“1”

START

RD

ADDRESS

GENERATOR

DATA 5

DATA 0 DATA 1 DATA 2 DATA 3 DATA 4

PIN 0-9

START

DIO 0-23

(RD LOW)

OUT 0 OUT 1 OUT 2

ORIGINAL BIN CONTENTS

CONTROL

ARE NOT UPDATED

FIGURE 3. HISTOGRAM MODE TIMING

FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM

6

HSP48410

RAM is disabled and the part is in LUT(read) mode. Note

Histogram Accumulate Mode

that the counter is not reset at this point. The counter will be

reset on the ﬁrst cycle of CLK that START is detected low. To

prevent invalid data from being written to the RAM, when the

counter reaches its maximum value (1023), further writing to

the RAM is disabled and the counter remains at this value

until the mode is changed.

This function is very similar to the Histogram function. In this

case, a counter is used to provide the address data to the

RAM. The RAM is sequentially accessed, and the data from

each bin is added to the data from the previous bins. This

accumulation of data continues until the function is halted.

The results of the accumulation are displayed on the DIO

bus while simultaneously being written back to the RAM.

When the operation is complete, the RAM will contain the

Cumulative Distribution Function (CDF) of the image.

At the end of the histogram accumulation, the DIO output

bus will contain the last accumulated value. The chip will

remain in this state until START becomes inactive. The

results of the accumulation can then be read out

synchronously by keeping START high, or asynchronously in

either of the asynchronous modes.

Figure 4 shows the conﬁguration for this mode. Once this

function is selected, the START pin is used to reset the

counter and enable writing to the RAM. Write enable is

delayed 3 cycles to match the delay in the Address

Generator. The START pin determines when the

accumulation will begin. Before this pin is activated, the

counter will be in an unknown state and the DIO bus will

contain unpredictable data. Once the START pin is sampled

low, the data registers are reset in order to clear the

accumulation. The output (DIO bus) will then be zero until a

nonzero data value is read from the RAM. Timing for this

operation is shown in Figure 5.

Bin Accumulate Mode

The functionality of this mode is also similar to the Histogram

function. The only difference is that instead of incrementing

the bin data by 1, the bin data is added to the incoming DIN

bus data. The DIN bus is delayed internally by 3 cycles to

match the latency in the address generator. Figure 6 shows

the block diagram of the internal conﬁguration for this mode,

while the timing is given in Figure 7. Note that in this ﬁgure,

START is used to disregard the data on DIN0-23 during

DATA2.

RAM

IN

OUT

RAM

DIO

0-23

IN

OUT

ADDRESS

DIO

I/F

S

ADDRESS

DIO

I/F

DIO 0-23

Σ

DIN 0-23

PIN 0-9

RD

ADDRESS

GENERATOR

“0”

RD

ADDRESS

GENERATOR

CLK

COUNTER

START

CONTROL

START

CONTROL

FIGURE 6. BIN ACCUMULATE BLOCK DIAGRAM

FIGURE 4. HISTOGRAM ACCUMULATE MODE BLOCK

DIAGRAM

CLK

START

CLK

START

ADDRESS

PIN 0-9

ADD. 0 ADD. 1 ADD. 2 ADD. 3 ADD. 4 ADD. 5

DATA

DATA 5

DIN 0-23

DATA 0 DATA 1 DATA 2 DATA 3 DATA 4

OUTPUT

DIO 0-23

(RD LOW)

OUT 0 OUT 1 OUT 2

DIO 0-23

(RD LOW)

OUT 0

OUT 1

OUT 2

FIGURE 5. HISTOGRAM ACCUMULATE MODE TIMING

ORIGINAL BIN CONTENTS

ARE NOT UPDATED

The START pin must remain low in order to allow the

accumulated data to overwrite the original histogram data

contained in the RAM. When the START pin returns to a high

state, the conﬁguration remains intact, but writing to the

FIGURE 7. BIN ACCUMULATE TIMING

7

HSP48410

Look Up Table Mode

CLK

A Look Up Table (LUT) is used to perform a ﬁxed

transformation function on pixel values. This is particularly

useful when the transformation is nonlinear and cannot be

realized directly with hardware. An example is the remapping

of the original pixel values to a new set of values based on

the CDF obtained through Histogram Accumulation.

(WRITE)

START

DIN 0-23

PIN 0-9

(READ)

DATA

0

1

2

3

4

5

ADDRESS

0

1

2

3

OUTPUT

The transformation function can be loaded into the LUT in

one of three ways: in LUT mode, through DIN0-23; in either

asynchronous mode, over the DIO bus as described below

under Asynchronous 16/24 Modes; in the Histogram

Accumulate mode the transformation function is calculated

internally (see description above). The transformation

function can then be utilized by deactivating START, putting

the part in LUT mode and clocking the data to be

transformed onto the PIN bus. Note that it is necessary to

wait one clock cycle after changing the mode before clocking

data into the part.

DIO 0-23

0

⁰* ¹* 2* 3*

* PREVIOUS CONTENTS OF BIN LOCATION.

FIGURE 9. LOOK UP TABLE MODE TIMING

Delay Memory (Row Buffer) Mode

As seen by comparing Figures 8 and 10, the conﬁguration

for this mode is nearly identical to the LUT mode. In this

mode, however, the counter is always providing the address

and the write function is always enabled.

In order to force this conﬁguration to act as a row delay

register, the START signal must be used to reset the internal

counter each time a new row of pixels is being sampled.

Because of the inherent latency in the address and data

paths, the counter must be reset every N-4 cycles, where N

is the desired delay length. For example, if a delay from DIN

to DIO of ten cycles is desired, the START signal must be set

low every six cycles (see Figure 11). If the internal address

counter reaches its maximum count (1023), it holds that

value and further writes to the RAM are disabled.

The Block Diagram and Timing Diagram for this mode are

shown in Figures 8 and 9. The left half of the timing diagram

shows LUT(write) mode. On the ﬁrst CLK that detects

START low, the counter is reset and the write enable is

activated for the RAM. As long as START remains low, the

counter provides the write address to the RAM and data is

sequentially loaded through the DIN bus. The DIN bus is

delayed internally by 3 cycles to match the latency in the

Address Generator. The DIO bus will contain the previous

contents of the memory location being updated. When 1024

words have been written to the RAM, the counter stops and

further writes to the RAM are disabled. The part stays in this

state while START remains low.

RAM

DIN 0-23

IN

OUT

ADDRESS

DIO

I/F

When START returns high, the RAM write is disabled, the

read address is taken from the PIN bus, and the chip acts as

a synchronous LUT. (This is known as LUT(read) mode.) In

order to ensure that the internal pipelines are clear, data

should not be input to PIN0-9 until the third clock after

START goes high

DIO 0-23

Σ

CLK

COUNTER

“0”

RD

START

CONTROL

RAM

DIN 0-23

IN

OUT

WR

FIGURE 10. DELAY MEMORY BLOCK DIAGRAM

ADDRESS

DIO

I/F

DIO 0-23

Σ

CLK

PIN 0-9

RD

ADDRESS

“0”

GENERATOR

START

DATA

DIN 0-23

1

2

3

4

5

6

7

8

9

10

11 12 13 14

CLK

COUNTER

DIO 0-23

1

2

3

4

5

START

CONTROL

FIGURE 11. DELAY MEMORY MODE TIMING FOR ROW

LENGTH OF TEN

FIGURE 8. LOOK UP TABLE BLOCK DIAGRAM

8

HSP48410

The difference between the Async 16 mode and the Async

Delay and Subtract Mode

24 mode is the number of data bits available to the user. In

16-bit mode, the user can connect the system data bus to

the lower 16 bits of the Histogrammer’s DIO bus. The UWS

pin becomes the LSB of the IO address, which determines if

the lower 16 bits or upper 8 bits of the 24-bit Histogrammer

data is being used. When UWS is low, the data present at

DIO0-15 is the lower 16 bits of the data in the IOADD0-9

location. When UWS is high, the upper 8 bits of the

IOADD09 location are present on DIO0-7. (This is true for

both reading and writing). Thus, it takes 2 cycles for an

asynchronous 24-bit operation when in Async 16 mode.

Unused outputs are zeros.

This mode is similar to the Delay Memory mode, except the

input data is subtracted from the corresponding data stored

in RAM (See Figures 12 and 13).

RAM

DIN 0-23

IN

OUT

DIO 0-23

ADDRESS

DIO

I/F

Σ

TWO’S

COMPLEMENT

RD

CLK

COUNTER

DIO 0-23

DIO

I/F

START

CONTROL

24x1024

RAM

IN

OUT

WR

ADDRESS

FIGURE 12. DELAY AND SUBTRACT BLOCK DIAGRAM

CLK

ADDRESS

GENERATOR

IOADD 0-9

START

DATA

WR

RD

UWS

DIN 0-23

DIO 0-23

1

2

3

4

5

6

7

8

9

10 11 12 13 14

MODIFIED DATA

CONTROL

OUTPUT

1

2

3

4

5

FIGURE 14. ASYNCHRONOUS 16/24 BLOCK DIAGRAM

DATA 1

MINUS

DATA 7

DATA 2

MINUS

DATA 8

WRITE CYCLE TIMING

WR

FIGURE 13. DELAY AND SUBTRACT MODE TIMING FOR ROW

LENGTH OF TEN

Asynchronous 16/24 Modes

RD

IOADD 0-9,

UWS

In the Asynchronous modes, the chip acts like a single port

RAM. In this mode, the user can read (access) any bin

location on the ﬂy by simply setting the 10-bit IO address to

the desired bin location. The RAM is then read or written on

the following RD or WR pulse. A block diagram for this mode

is shown in Figure 14. Note that all registers and pipeline

stages are bypassed; START and CLK have no effect in

this mode.

DIO 0-23

READ CYCLE TIMING

WR

RD

IOADD 0-9,

UWS

Timing waveforms for this mode are also shown in Figure 15.

During reading, the read address is latched (internally) on

the falling edge of RD. During write operations, the address

is latched on the falling edge of WR and data is latched on

the rising edge of WR. Note that reading and writing occur

on different ports, so that, in this mode, the write port always

latches its address and data values from the WR signal,

while the read port always uses RD for latching.

DIO 0-23

FIGURE 15. ASYNCHRONOUS 16/24 MODE TIMING

9

HSP48410

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Thermal Resistance (Typical, Note 3)

θ

( C/W)

θ

( C/W)

JA

JC

o

Input, Output Voltage . . . . . . . . . . . . . . . . . .GND-0.5V to V +0.5V

CC

PGA Package. . . . . . . . . . . . . . . . . . . .

PLCC Package. . . . . . . . . . . . . . . . . . .

N/A

34

8.0 C/W

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

N/A

o

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Junction Temperature . . . . 175 C (PGA), 150 C (PLCC)

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

Operating Conditions

o

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

(PLCC - Lead Tips Only)

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3500 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θ is measured with the component mounted on an evaluation PC board in free air.

JA

DC Electrical Speciﬁcations

PARAMETER

Logical One Input Voltage

Logical Zero Input Voltage

High Level Clock Input

Low Level Clock Input

Output High Voltage

SYMBOL

MIN

2.0

-

MAX

-

UNITS

V

TEST CONDITIONS

= 5.25V

V

IH

CC

V

0.8

-

V

= 4.75V

= 5.25V

IL

V

3.0

-

V

IHC

V

0.8

-

V

= 4.75V

ILC

OH

V

2.6

-

V

I

= -400µA, V

= 4.75V

OH

CC

Output Low Voltage

V

0.4

10

500

V

= +2.0mA, V

CC

OL

Input Leakage Current

I/O Leakage Current

I

-10

D-

µA

V

= V

CC

or GND, V

= 5.25V

L

IN

CC

I

= V

or GND, V

= 5.25V

O

OUT

CC

Standby Supply Current

I

= V

or GND, V

CC

= 5.25V,

CCSB

IN

CC

Outputs Open

Operating Power Supply Current

NOTES:

I

-

396

mA

f = 33 MHz, V = V

or GND

CCOP

IN CC

V

= 5.25V (Notes 4, 5)

CC

4. Power supply current is proportional to operating frequency. Typical rating for I

is 12mA/MHz.

CCOP

5. Maximum junction temperature must be considered when operating part at high clock frequencies.

o

Capacitance T = 25 C, Not tested, but characterized at initial design and at major process or design changes.

A

PARAMETER

Input Capacitance

SYMBOL

MIN

MAX

12

UNITS

pF

TEST CONDITIONS

C

-

FREQ = 1 MHz, V = Open, all

IN

CC

measurements are referenced to

device ground.

Output Capacitance

C

12

pF

OUT

o

AC Electrical Speciﬁcations

V

= 5V ± 5%, T = 0 C to 70 C (Note 6)

CC

A

-40 (40 MHz)

-33 (33 MHz)

PARAMETER

Clock Period

SYMBOL

NOTES

MIN

25

10

12

0

MAX

MIN

30

12

13

0

MAX

UNITS

ns

t

-

CP

Clock Low

t

ns

CH

Clock High

t

-

ns

CL

DS

DH

DO

DIN Setup

t

-

ns

DIN0-23 Hold

t

-

ns

Clock to DIO0-23 Valid

FC Pulse Width

FCT0-2 Setup to LD

t

-

15

-

19

-

ns

t

35

10

35

10

ns

FL

FS

t

-

ns

10

HSP48410

o

AC Electrical Speciﬁcations

V

= 5V ± 5%, T = 0 C to 70 C (Note 6) (Continued)

CC A

-40 (40 MHz)

-33 (33 MHz)

PARAMETER

FCT0-2 Hold from LD

START Setup to CLK

START Hold from CLK

PIN0-9 Setup Time

PIN0-9 Hold Time

LD Pulse Width

SYMBOL

NOTES

MIN

0

MAX

MIN

0

MAX

UNITS

ns

t

-

FH

SS

SH

12

0

13

0

t

-

t

12

0

13

0

-

PS

t

-

PH

t

10

12

-

LL

LS

WL

LD Setup to START

WR Low

t

Note 7

T

-

CP

t

12

13

1

-

15

1

-

WR High

t

-

WH

Address Setup

t

-

AS

AH

Address Hold

t

-

DIO Setup to WR

DIO Hold from WR

RD Low

t

12

1

-

15

1

-

WS

t

-

WH

t

35

15

-

43

17

-

RL

RH

RD

RD High

t

-

RD Low to DIO Valid

Read/Write Cycle Time

DIO Valid after RD High

Output Enable Time

Output Disable Time

Output Rise Time

Output Fall Time

NOTES:

t

35

-

43

-

t

55

-

65

-

CY

t

Note 8

Note 9

Note 8

0

18

6

0

19

6

OH

t

-

OE

t

-

OD

t

From 0.8V to 2.0V, Note 8

From 2.0V to 0.8V, Note 8

-

R

t

-

F

6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)

= 2.0V, (all others) = 1.5V. Output load circuit with C = 40pF. Output transition measured at V ≥ 1.5V and V ≤ 1.5V.

L

OH

OL

7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.

8. Characterized upon initial design and after major changes to design and/or process.

9. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with C = 40pF.

L

Test Load Circuit

S

DUT

1

^C†

L

†INCLUDES STRAY AND JIG CAPACITANCE

±

IOH

1.5V

IOL

SWITCH S1 OPEN FOR I

AND I

EQUIVALENT CIRCUIT

CCSB

CCOP

11

HSP48410

i

Waveforms

t

LL

t

CP

t

CH

CL

LD

CLK

t

FS

t

FH

t

DH

DS

FCT0-2

CLK

DIN0-23

PIN0-9

t

PH

PS

t

LS

START

t

DO

DIO0-23

SYNCHRONOUS OUTPUT TIMING

t

SS

RD

t

SH

t

OD

OE

START

t

SH

DIO0-23

t

SS

FIGURE 16. SYNCHRONOUS DATA AND CONTROL TIMING

FIGURE 17. FUNCTION LOAD TIMING

WR

RD

t

WL

WH

t

RH

RL

WR

RD

t

AH

AS

t

IOADD0-9

AH

t

AS

t

IOADD0-9

RD

t

OD

t

WDH

WDS

DIO0-23

FIGURE 18. WRITE CYCLE TIMING

FIGURE 19. READ CYCLE TIMING

t

FL

t

F

R

2.0 V

0.8 V

FC

FIGURE 20. FLASH CLEAR TIMING

FIGURE 21. OUTPUT RISE AND FALL TIMES

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

12


型号：	HSP48410GC-33
厂家：	Intersil
描述：	Histogrammer/Accumulating Buffer Histogrammer /累积缓冲区
文件：	总12页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSP48410GC-33 [INTERSIL]

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