HSP48410GM-25/883_技术文档

HSP48410/883

TM

Data Sheet

May 1999

FN3542.2

Histogrammer/Accumulating Buffer

Features

The Intersil HSP48410/883 is an 84 lead Histogrammer IC

int.ended for use in image and signal analysis. The on board

memory is configured as 1024 x 24 array. This translates to

a pixel resolution of 10 bits and an image size of 4k x 4k with

no possibility of overflow.

• This Circuit is Processed in Accordance to MIL-STD-883

and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

• 10-Bit Pixel Data

• 4k x 4k Frame Sizes

In addition to 4-Histogramming, the HSP48410 can generate

and store the Cumulative Distribution Function for use in

Histogram Equalization Applications. Other capabilities of

the HSP48410 include: Bin Accumulation, Look Up Table,

24-bit Delay Memory, and Delay and Subtract Mode.

• Asynchronous Flash Clear Pin

• Fully Asynchronous 16-Bit or 24-Bit Host Interface

• DC to 33MHz Clock Rate

A flash clear pin is available in all modes of operation and

performs a single cycle reset on all locations of the internal

memory array and all internal data paths.

Applications

• Histogramming

• Histogram Equalization

• Image and Signal Analysis

The HSP48410 includes a fully asynchronous interface

which provides a means for communications with a host,

such as a microprocessor. The interface includes dedicated

Read/Write pins and an address port which are

asynchronous to the system clock. This allows random

access of the Histogram Memory Array for analysis or

conditioning of the stored data.

Ordering Information

TEMP.

PKG.

NO.

o

PART NUMBER

HSP48410GM-33/883

HSP48410GM-25/883

RANGE ( C) PACKAGE

-55 to 125 84 Ld PGA G84.A

Block Diagram

HISTOGRAM

MEMORY

ARRAY

DATA

IN

DATA

OUT

DIO0-23

DIO

ADDER

MUX

INTERACE

DIN0-23

ADDRESS

PIN0-9

ADDRESS

GENERATOR

IOADD0-9

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

1

HSP48410/883

Pinouts

84 PIN PGA

TOP VIEW

11

10

9

DIN8

DIN5

DIN4

DIN2

PIN9

DIN10

DIN7

DIN6

DIN3

DIN0

DIN11

DIN9

DIN13

DIN12

DIN16

DIN15

DIN14

DIN17

DIN21

GND

DIN19

DIN20

DIN18

DIN22

DIN23

DIO23

DIO21

DIO22

DIO20

DIO18

DIO15

DIO12

DIO8

DIO19

DIO17

DIO16

DIO14

8

DIO11

DIO13

GND

7

GND

DIO10

V

6

5

DIN1

PIN7

CLK

PIN6

CC

DIO9

DIO6

PIN8

DIO7

4

3

2

PIN5

PIN3

PIN2

PIN4

PIN1

FC

DINO4

DIO1

DINO5

DIO3

FCT0

WR

IOADD9 IOADD8

FCT2

IOADD6 IOADD3 IOADD0

DIO0

DIO2

RD

UWS

1

PIN0

A

START

B

LD

C

FCT1

D

GND

E

IOADD5

F

IOADD4

H

IOADD1

K

V

IOADD7

G

IOADD2

J

CC

PIN “A1” ID

L

84 PIN PGA

BOTTOM VIEW

DIN19

DIO17

DIO16

DIO14

DIO11

DIO13

GND

DIO22

DIO20

DIO18

DIO15

DIO12

DIO23

DIO21

DIN22

DIN23

DIN19

DIN17

DIN21

GND

DIN16

DIN13

DIN12

DIN11

DIN9

DIN10

DIN7

DIN6

DIN3

DIN0

DIN1

PIN7

DIN8

DIN5

DIN4

DIN2

11

10

9

DIN20

DIN18

DIN15

DIN14

8

DIN9

DIO10

7

GND

V

DIO8

DIO7

DIO9

DIO6

6

5

CC

CLK

PIN6

PIN8

DIO5

DIO3

DIO4

PIN4

PIN1

FC

PIN5

PIN3

4

3

2

IOADD8 IOADD9 FCT0

DIO2

IOADD3 IOADD6

WR

FCT2

RD

PIN2

DIO0 IOADD3

UWS

V

IOADD1 IOADD2 IOADD4 IOADD7 IOADD5

FCT1

D

START

B

1

PIN0

A

GND

E

LD

C

CC

L

K

J

H

G

F

2

HSP48410/883

Pin Description

SYMBOL

PIN NUMBER

TYPE

DESCRIPTION

CLK

C6

I

Clock Input. This input has no effect on the chips functionality when the chip is

programmed to an asynchronous mode. All signals denoted as synchronous have

their timing specified with reference to this signal.

PIN0-9

A1-5, A7, B3-5, C5

I

Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on

chip RAM with address values in Histogram, Bin Accumulate and LUT (write) mode.

During Asynchronous modes it is unused.

LD

C1

I

The Load pin is used to load the FCT0-2 bits into the FCT Registers.

(See below).

FCT0-2

D1-2, E3

These three pins are decoded to determine the mode of operation for the chip. The

signals are sampled by the rising edge of LD and take effect after the rising edge of

LD. Since the loading of this function is asynchronous to CLK, it is necessary to

disable the START pin during loading and enable START at least 1 CLK cycle

following the LD pulse.

START

B1

I

This pin informs the on chip circuitry which clock cycle will start and/or stop the

current mode of operation. Thus, the modes are asynchronously selected (via LD)

but are synchronously started and stopped. This input is sampled by the rising edge

of CLK. The actual function of this input depends on the mode that is selected.

START must always be held high (disabled) when changing modes. This will provide

a smooth transition from one mode to the next by allowing the part to reconfigure

itself before new mode begins. When START is high, LUT (read) mode is enabled

except for Delay and Subtract Modes.

FC

B2

I

Flash Clear. This input provides a fully asynchronous signal which effectively resets

all bits in the RAM Array and the input and output data paths to zero.

DIN0-23

A8-11, B6-11,

C10-11, D10-11,

E9-11, F10-11,

G9-11, H10-11

Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT,

Delay and Delay and Subtract Modes. Synchronous to CLK.

DIO0-23

J5-7, J10-11,

K2-11, L2-4, L6-11

I/O

Asynchronous Data Bus. Provides RAM access for a microprocessor in

preconditioning the memory array and reading the results of the previous operation.

Configurable as either a 24-bit or 16-bit bus.

IOADD0-9

UWS

F1, F3, G1-3, H1-2,

J1-2, K1

I

RAM Address in Asynchronous Modes. Sampled on the falling edge of WR or RD.

F2

Upper Word Select. In 16-bit asynchronous mode, a one on this pin denotes the

contents of DIO0-7 as being the upper eight-bits of the data in or out of the

Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes,

this pin has no effect.

WR

RD

E2

C2

I

Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured

in one of the asynchronous modes. Asynchronous to CLK.

Read control for the data on DIO0-23 in asynchronous modes. Output enable for

DIO0-23 in other modes. Asynchronous to CLK.

V

A6, L1

+5V.

CC

GND

C7, E1, F9, L5

Ground.

3

HSP48410/883

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8V

Input, Output Voltage. . . . . . . . . . . . . . . . .GND -0.5V to V +0.5V

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Thermal Resistance (Typical, Note 1)

PGA Package. . . . . . . . . . . . . . . . . . . .

Maximum Package Power Dissipation at 125 C

θ

( C/W)

θ

( C/W)

JA

JC

CC

36

7.0

o

PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.46

o

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .175 C

Operating Conditions

o

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,500

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

TABLE 1. DC ELECTRICAL SPECIFICATIONS

Device Guaranteed and 100% Tested

GROUP A

SUBGROUP

o

PARAMETER

Logical One Input Voltage

Logical Zero Input Voltage

High Level Clock Input

Low Level Clock Input

Output High Voltage

SYMBOL

CONDITIONS

= 5.5V

TEMP ( C)

MIN

2.2

-

MAX

UNITS

V

1, 2, 3

-55 ≤ T ≤ 125

-

0.8

-

V

IH

CC

A

V

= 4.5V

1, 2, 3

-55 ≤ T ≤ 125

A

IL

V

= 5.5V

1, 2, 3

-55 ≤ T ≤ 125

3.0

-

IHC

A

V

= 4.5V

1, 2, 3

-55 ≤ T ≤ 125

0.8

-

ILC

OH

A

V

I

= -400µA,

1, 2, 3

-55 ≤ T ≤ 125

2.6

OH

A

V

= 4.5V (Note 2)

CC

Output Low Voltage

Input Leakage Current

I/O Leakage Current

Standby Supply Current

V

OL

I

V

= +2.0mA,

1, 2, 3

-55 ≤ T ≤ 125

-

0.4

10

V

OL

A

= 4.5V (Note 2)

CC

I

V

= V

or GND,

-55 ≤ T ≤ 125

-10

-

µA

L

IN

CC

= 5.5V

A

CC

I

V

= V

CC

or GND,

-55 ≤ T ≤ 125

10

O

OUT

A

= 5.5V

CC

I

V

= V

or GND,

-55 ≤ T ≤ 125

500

CCSB

IN

CC

A

= 5.5V,

CC

Outputs Open

Operating Power Supply Cur-

rent

I

f = 25.6MHz,

1, 2, 3

7, 8

-55 ≤ T ≤ 125

-

308

-

mA

-

CCOP

FT

A

V

= V

or GND

IN

CC

= 5.5V (Note 3)

CC

Functional Test

NOTES:

(Notes 4, 5)

-55 ≤ T ≤ 125

A

2. Interchanging of force and sense conditions is permitted.

3. Power supply current is proportional to operating frequency. Typical rating for I

considered when operating part at high clock frequencies.

is 12mA/MHz. Maximum junction temperature must be

CCOP

4. Tested as follows: f = 1MHz, V = 2.6V, V = 0.4V, V

IH IL

≥ 1.5V, V ≤ 1.5V, V

OL IHC

= 3.4V and V = 0.4V.

ILC

OH

5. Loading is as specified in the test load circuit with C = 40pF.

L

4

HSP48410/883

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

o

Device Tested at: V

= 5.0V ±10%, T = -55 C to 125 C (Note 1)

A

CC

-33 (33MHz)

-25 (25.6MHz)

GROUP A

o

PARAMETER

Clock Period

SYMBOL

NOTES

SUBGROUPS

9, 10, 11

TEMP ( C)

MIN

30

12

15

1

MAX

MIN

39

15

16

1

MAX

UNITS

ns

t

-55 ≤ T ≤ 125

-

CP

CH

CL

A

Clock Low

-55 ≤ T ≤ 125

A

Clock High

-55 ≤ T ≤ 125

-

A

DIN Setup

-55 ≤ T ≤ 125

-

DS

DH

DO

A

DIN 0-23 Hold

-55 ≤ T ≤ 125

-

A

Clock to DIO 0-23 Valid

FC Pulse Width

FCT 0-2 Setup to LD

FCT 0-2 Hold from LD

START Setup to CLK

START Hold from CLK

PIN 0-9 Setup Time

PIN 0-9 Hold Time

LD Pulse Width

LD Setup to START

WR Low

-55 ≤ T ≤ 125

-

19

-

24

-

A

t

-55 ≤ T ≤ 125

35

12

1

35

15

1

FL

FS

FH

SS

SH

PS

PH

A

-55 ≤ T ≤ 125

-

A

-55 ≤ T ≤ 125

-

A

-55 ≤ T ≤ 125

15

0

-

16

0

-

A

t

-55 ≤ T ≤ 125

-

A

-55 ≤ T ≤ 125

15

1

-

16

1

-

A

-55 ≤ T ≤ 125

-

A

t

-55 ≤ T ≤ 125

12

-

15

-

LL

LS

A

t

Note 7

-55 ≤ T ≤ 125

t

CP

-

A

CP

t

-55 ≤ T ≤ 125

15

16

2

-

20

2

-

WL

A

WR High

t

-55 ≤ T ≤ 125

-

WH

A

Address Setup

Address Hold

t

-55 ≤ T ≤ 125

-

AS

AH

A

-55 ≤ T ≤ 125

-

A

DIO Setup to WR

DIO Hold from WR

RD Low

t

-55 ≤ T ≤ 125

16

2

-

20

2

-

WS

WH

A

-55 ≤ T ≤ 125

-

A

t

-55 ≤ T ≤ 125

43

17

-

55

20

-

RL

RH

RD

OE

CY

A

RD High

t

-55 ≤ T ≤ 125

-

A

RD Low to DIO Valid

Output Enable Time

Read/Write Cycle Time

NOTES:

-55 ≤ T ≤ 125

43

19

-

55

24

-

A

Note 8

-55 ≤ T ≤ 125

-

A

-55 ≤ T ≤ 125

65

80

A

6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)

= 2.0V, (all others) = 1.5V. Output load circuit with C = 40pF. Output transition measured at V ≥ 1.5V and V ≥ 1.5V.

L

OH

OL

7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.

8. Transition is measured at ±200 mV from steady state voltage with loading as specified in test load circuit with C = 40pF.

L

5

HSP48410/883

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

-33 (33MHz)

-25 (25.6MHz)

o

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMP ( C)

MIN

MAX

MIN

MAX

UNITS

Input Capacitance

C

V

= Open, f = 1MHz, all

9

T

= 25

-

12

-

12

pF

IN

CC

A

measurements are refer-

enced to device GND.

Output Capacitance

C

V

= Open, f = 1MHz, all

9

T

= 25

-

12

-

12

-

pF

ns

O

CC

A

measurements are refer-

enced to device GND.

DIO Valid After RD

High

t

9, 10

-55 ≤ T ≤ 125

0

OH

OD

A

Output Disable Time

Output Rise Time

Output Fall Time

NOTES:

9, 10

-55 ≤ T ≤ 125

-

27

9

-

27

9

ns

A

t

From 0.8V to 2.0V

From 2.0V to 0.8V

-55 ≤ T ≤ 125

A

r

f

-55 ≤ T ≤ 125

9

A

9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized

upon initial design and after major process and/or design changes.

10. Loading is as specified in the test load circuit with C = 40pF.

L

TABLE 4. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS

Initial Test

METHOD

100%/5004

100%

SUBGROUPS

-

Interim Test

PDA

-

1

Final Test

Group A

100%

2, 3, 8A, 8B, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 7, 9

-

Groups C and D

Samples/5005

6

HSP48410/883

Waveforms

t

CP

t

CL

CH

CLK

t

DS

PS

DH

PH

DIN0-23

PIN0-9

t

DO

DIO0-23

t

SS

t

SH

SS

START

t

SH

t

FL

FC

FIGURE 1. SYNCHRONOUS DATA AND CONTROL TIMING

t

LL

LD

t

FS

t

FH

FCT0-2

CLK

t

LS

START

FIGURE 2. FUNCTION LOAD TIMING

7

HSP48410/883

Waveforms (Continued)

RD

t

OE

OD

DIO0-23

FIGURE 3. SYNCHRONOUS OUTPUT TIMING

t

WH

WL

WR

RD

t

AH

t

AS

IOADD0-9

DIO0-23

t

WDH

WDS

FIGURE 4. WRITE CYCLE TIMING

WR

RD

t

RH

RL

t

AH

RD

t

AS

IOADD0-9

t

OD

t

OH

DIO0-23

FIGURE 5. READ CYCLE TIMING

t

f

r

2.0V

0.8V

FIGURE 6. OUTPUT RISE AND FALL TIMES

8

HSP48410/883

Burn-In Circuits

84 PIN PGA

TOP VIEW

11

10

9

DIN8

DIN5

DIN4

DIN2

PIN9

DIN10

DIN7

DIN6

DIN3

DIN0

DIN11

DIN9

DIN13

DIN12

DIN16

DIN15

DIN14

DIN17

DIN21

GND

DIN19

DIN20

DIN18

DIN22

DIN23

DIO23

DIO21

DIO22

DIO20

DIO18

DIO15

DIO12

DIO8

DIO19

DIO17

DIO16

DIO14

8

DIO11

DIO13

GND

7

GND

DIO10

DIO9

V

6

5

DIN1

PIN7

CLK

PIN6

CC

PIN8

DIO7

DIO6

4

3

2

PIN5

PIN3

PIN4

PIN1

FC

DINO4

DIO1

DINO5

DIO3

FCT0

WR

IOADD9 IOADD8

PIN2

FCT2

IOADD6 IOADD3 IOADD0

DIO0

DIO2

RD

UWS

1

PIN0

A

START

B

LD

C

FCT1

D

GND

E

IOADD5

F

IOADD4

H

IOADD1

K

V

IOADD7

G

IOADD2

J

CC

PIN “A1” ID

L

9

HSP48410/883

TABLE 5.

PGA

NAME

BURN-IN

SIGNAL

PGA

NAME

BURN-IN

SIGNAL

PGA

NAME

BURN-IN

SIGNAL

PGA

NAME

BURN-IN

SIGNAL

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

B1

B2

B3

B4

B5

B6

B7

B8

PIN0

PIN2

PIN3

PIN5

PIN8

F1

F3

F4

F6

F9

B9

B10

B11

C1

DIN6

DIN7

DIN10

LD

F7

F8

E11

F1

DIN16

IOADD5

UWS

F2

F6

J5

J6

DIO6

DIO9

F7

F10

F11

F7

F11

F1

F2

F11

F10

GND

F7

J7

DIO10

DIO21

DIO23

IOADD1

DIO0

F3

IOADD9

GND

J10

J11

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

L1

C2

RD

F9

V

C5

PIN6

CLK

F7

F10

F11

G1

G2

G3

G9

G10

G11

H1

DIN21

F2

CC

PIN9

DIN2

DIN4

DIN5

DIN8

START

FC

F10

F3

C6

F0

DIN17

F3

F1

C7

GND

DIN9

DIN11

FCT1

FCT2

DIN12

DIN13

GND

WR

GND

F10

F12

F13

F14

F13

F14

GND

F2

IOADD7

IOADD6

IOADD8

DIN18

F8

DIO1

F2

F5

C10

C11

D1

F7

DIO4

F5

F6

F9

DIO7

F8

F9

F4

DIO8

F9

F10

F16

F2

D2

DIN20

F6

DIO12

DIO15

DIO18

DIO20

DIO22

F13

F1

D10

D11

E1

DIN19

F5

PIN1

PIN4

PIN7

DIN1

DIN0

DIN3

IOADD4

IOADD3

DIN23

F5

F4

F5

H2

F4

F6

F8

E2

H10

H11

J1

F9

F8

F2

E3

FCT0

DIN14

DIN15

F12

F15

F1

DIN22

F8

V

CC

F1

E9

IOADD2

IOADD0

F3

L2

DIO2

DIO3

DIO4

F3

F4

F6

F4

E10

J2

F1

L3

L4

NOTES:

11. V /2 (2.7V ±10%) used for outputs only.

CC

12. 47kΩ (±20%) resistor connected to all pins except V

and GND.

CC

13. V

= 5.5 ±0.5V.

CC

14. 0.1µF (min) capacitor between V

and GND per position.

CC

15. F = 100kHz ±10%, F1 = F0/2, F2 = F1/2 . . . F16 = F15/2,

O

40% - 60% duty cycle.

16. Input Voltage Limits: V = 0.8V max. V = 4.5V ±10%.

IL

IH

Die Characteristics

DIE DIMENSIONS:

GLASSIVATION:

330 x 281 x 19 ± 1mils

Type: Nitrox

Thickness: 10kÅ

METALLIZATION:

WORST CASE CURRENT DENSITY:

Type: Si - Al or Si-Al-Cu

Thickness: 8kÅ

5

2

0.47 x 10 A/cm

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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型号：	HSP48410GM-25/883
厂家：	Intersil
描述：	Histogrammer/Accumulating Buffer Histogrammer /累积缓冲区外围集成电路时钟
文件：	总10页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSP48410GM-25/883 [INTERSIL]

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