HSP45116GM-15/883 [INTERSIL]
Numerically Controlled Oscillator/Modulator; 数控振荡器/调制器
| 型号： | HSP45116GM-15/883 |
| 厂家： | 
Intersil |
| 描述： | Numerically Controlled Oscillator/Modulator |
| 文件： | 总6页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP45116/883
TM
Data Sheet
May 1999
FN2813.3
Numerically Controlled
Oscillator/Modulator
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Intersil HSP45116/883 combines a high performance
quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As shown
in the Block Diagram, the HSP45116/883 is divided into three
main sections. The Phase/Frequency Control Section (PFCS)
and the Sine/Cosine Section together form a complex NCO.
The CMAC multiplies the output of the Sine/Cosine Section
with an external complex vector.
• NCO and CMAC on One Chip
• 15MHz and 25.6MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.006Hz Tuning Resolution at 25.6MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.006Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC mul-
tiplies this (cos, sin) vector by an external complex vector and
can accumulate the result. The resulting complex vectors are
available through two 20-bit output ports which maintain the
90dB spectral purity. This result can be accumulated internally
to implement an accumulate and dump filter.
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
TEMP.
RANGE ( C)
PKG.
NO.
o
PART NUMBER
HSP45116GM-15/883
HS45116GM-25/883
PACKAGE
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
-55 to 125 145 Ld PGA
-55 to 125 145 Ld PGA
G145.A
G145.A
Block Diagram
VECTOR INPUT
R
I
SINE/
COSINE
ARGUMENT
MICROPROCESSOR
PHASE/
SIN
INTERFACE
SINE/
COSINE
SECTION
FREQUENCY
CMAC
CONTROL
COS
INDIVIDUAL
SECTION
CONTROL SIGNALS
R
I
VECTOR OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HSP45116/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input or Output Voltage Applied. . . . . . . . .GND -0.5V to V +0.5V
ESD Rating Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
PGA Package . . . . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at 125 C
θ
( C/W)
θ
( C/W)
JA
o
JC
30.0
5.0
CC
PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16W
o
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175 C
Operating Conditions
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
o
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
Number of Transistors or Gates . . . . . . . . . . . . 103,000 Transistors
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
TEST
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE ( C) MIN
o
PARAMETER
SYMBOL
MAX
UNITS
Logical One Input
Voltage
V
V
V
V
V
= 5.5V
= 4.5V
= 5.5V
= 4.5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
55 ≤ T ≤ 125
2.2
-
-
V
IH
CC
CC
CC
CC
A
Logical Zero Input
Voltage
V
55 ≤ T ≤ 125
0.8
-
V
V
IL
A
Logical One Input
Voltage Clock
V
55 ≤ T ≤ 125
3.0
-
IHC
A
Logical Zero Input
Voltage Clock
V
55 ≤ T ≤ 125
0.8
-
V
ILC
A
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
V
I
= -400µA
= 4.5V (Note 2)
55 ≤ T ≤ 125
2.6
-
V
OH
OH
A
V
CC
V
I
= +2.0mA
= 4.5V (Note 2)
55 ≤ T ≤ 125
0.4
+10
+10
500
150
V
OL
OL
A
V
CC
I
V
= V
CC
or GND V
CC
55 ≤ T ≤ 125
-10
-10
-
µA
µA
µA
mA
I
IN
A
= 5.5V
Output or I/O Leakage
Current
I
V
V
= V
CC
or GND
55 ≤ T ≤ 125
A
O
OUT
= 5.5V
CC
Standby Power Supply
Current
I
V
= V
CC
or GND, V
55 ≤ T ≤ 125
A
CCSB
IN
CC
= 5.5V, (Note 5)
Operating Power Supply
Current
I
f = 15MHz,
55 ≤ T ≤ 125
-
CCOP
A
V
V
= V
or GND
IN
CC
CC
= 5.5V
(Notes 3, 5)
Functional Test
NOTES:
FT
(Note 4)
7, 8
55 ≤ T ≤ 125
-
-
A
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz.
4. Tested as follows: f = 1MHz, V (clock inputs) = 3.4V, V (all other inputs) = 2.6V, V = 0.4V, V
≥ 1.5V, and V
OL
≤ 1.5V.
IH IH IL OH
5. Output per test load circuit with switch open and C = 40pF.
L
2
HSP45116/883
TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
-15 (15MHz)
-25 (25.6MHz)
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
CLK Period
SYMBOL
NOTES
( C)
MIN
66
26
26
26
26
20
MAX
MIN
39
MAX
UNITS
ns
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
-
-
-
-
-
-
-
-
-
-
-
-
CP
A
CLK High
CLK Low
WR Low
WR High
t
-55 ≤ T ≤ 125
15
ns
CH
A
t
-55 ≤ T ≤ 125
-15
15
ns
CL
A
t
-55 ≤ T ≤ 125
ns
WL
A
t
-55 ≤ T ≤ 125
15
ns
WH
A
Setup Time; ADO-1,
CS to WR Going High
t
t
t
t
-55 ≤ T ≤ 125
18
ns
AWS
AWH
CWS
CWA
A
Hold Time; AD0, AD1,
CS from WR Going High
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
0
20
0
-
-
-
0
18
0
-
-
-
ns
ns
ns
A
Setup Time CO-15 from WR Go-
ing High
-55 ≤ T ≤ 125
A
Hold Time CO-15 from WR Go-
ing High
-55 ≤ T ≤ 125
A
Setup Time WR to CLK High
t
(Note 7)
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
20
20
-
-
16
18
-
-
ns
ns
WC
A
Setup Time MODO-1 to CLK
Going High
t
-55 ≤ T ≤ 125
A
MCS
Hold Time MODO-1 from CLK
Going High
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
0
-
-
-
-
0
18
0
-
-
-
-
ns
ns
ns
ns
MCH
A
Setup Time PACI to CLK
Going High
t
-55 ≤ T ≤ 125
25
0
PCS
PCH
A
Hold Time PACI from CLK
Going High
t
-55 ≤ T ≤ 125
A
Setup Time ENPHREG,
t
-55 ≤ T ≤ 125
20
15
ECS
A
ENCFRCTL, ENPHAC,
ENTICTL, CLROFR, PMSEL,
LOAD, ENI, ACC, BINFMT,
PEAK, MODPI/2PI, SHO-1,
RBYTILD from CLK Going High
Hold Time ENPHREG,
t
9, 10, 11
-55 ≤ T ≤ 125
0
-
0
-
ns
ECH
A
ENCFRCTL, ENPHAC,
ENTICTL, CLROFR, PMSEL,
LOAD, ENI, ACC, BINFMT,
PEAK, MODPI/2PI, SHO-1,
RBYTILD from CLK Going High
Setup Time RINO-18,
IMINO-18 to CLK Going High
t
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
20
0
-
-
-
15
0
-
-
-
ns
ns
ns
DS
DH
DO
A
Hold Time RINO-18,
IMINO-18, to CLK Going High
t
-55 ≤ T ≤ 125
A
CLK to Output Delay R0O-19,
I0O-19
t
-55 ≤ T ≤ 125
40
25
A
3
HSP45116/883
TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
-15 (15MHz)
-25 (25.6MHz)
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
SYMBOL
NOTES
( C)
MIN
MAX
-
MIN
MAX
-
UNITS
ns
CLK to Output Delay DETO-1
CLK to Output Delay PACO
CLK to Output Delay TICO
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
40
-
27
-
DEO
A
t
-55 ≤ T ≤ 125
30
30
25
20
20
20
ns
PO
A
t
-55 ≤ T ≤ 125
-
-
ns
TO
OE
A
Output Enable Time OER, OEI,
OEREXT, OEIEXT
t
(Note 8)
-55 ≤ T ≤ 125
-
-
ns
A
OUTMUXO-1 to Output Delay
t
9, 10, 11
-55 ≤ T ≤ 125
-
40
-
28
ns
MD
A
NOTES:
6. AC testing is performed as follows: V
= 4.5V and 5.5V. Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing
CC
reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with switch closed and C = 40pF. Output transition is measured
L
at V
≥ 1.5V and V
≤ 1.5V.
OH
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.
OL
8. Transition is measured at ±200mV from steady state voltage, output loading per test load circuit, with switch closed and C = 40pF.
L
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
-15
-25
TEMPERATURE
o
PARAMETER
SYMBOL
TEST CONDITIONS
= Open, f = 1MHz All
measurements are refer-
enced to device GND
NOTES
( C)
MIN
MAX
MIN
MAX
UNITS
Input Capacitance
C
V
9
T
T
- +25
-
15
-
15
pF
IN
CC
A
Output Capacitance
Output Disable Time
Output Rise Time
Output Fall Time
NOTES:
C
9
- +25
-
-
-
-
15
20
8
-
-
-
-
15
15
8
pF
ns
ns
ns
OUT
A
t
9, 10
9, 10
9, 10
-55 ≤ T ≤ 125
A
OD
t
From 0.8V to 2.0V
From 2.0V to 0.8V
-55 ≤ T ≤ 125
A
R
t
-55 ≤ T ≤ 125
8
8
F
A
9. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after
major process and/or design changes.
10. Loading is as specified in the test load circuit with C = 40pF.
L
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Tess
METHOD
100%/5004
100%/5004
100%
SUBGROUPS
-
Interim Test
PDA
-
1
Final Test
Group A
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
-
Groups C & D
Samples
4
HSP45116/883
Burn-In Circuit
145 PIN PGA
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
V
IMIN4 IMIN8 IMIN9 IMIN11 IMIN15 IMIN16 GND
IMIN 1 IMIN5 IMIN7 IMIN10 IMIN13 IMIN14 IO19
V
IO18
IO15
IO12
IO10
GND
V
A
B
CC
CC
CC
GND
IO16
IO14
IO13
IO11
IO9
IO8
IO6
IO7
IO5
IO1
IO2
C
D
E
F
RIN15 RIN18 IMIN2 IMIN3 IMIN6 IMIN12 IMIN17 IMIN18 IO17
RIN13 RIN17 IMIN0 INDEX
IO4
IO3
RO18
C
D
E
F
RO19 RO17
RO16 RO15
RO13 RO11
RO12 RO10
RIN10 RIN14 RIN16
IO0
RIN7
RIN11 RIN12
RO14
RO9
RO8
RO5
RO1
G
H
J
V
RIN9
RIN6
RIN1
RIN0
RIN8
RIN5
RIN4
SH1
G
H
J
CC
GND
RIN3
RIN2
RO7
RO4
RO2
GND
V
CC
K
RO6
RO3
RO0
K
L
M
N
P
SH0
ACC RBYTILD
PACO DET1
L
ENPH
REG
PEAK MOD1
OEREXT
OUT-
OEI
M
N
P
Q
ENCF MODPI
REG /2PI
ENOF
REG
OUT-
MUX1 MUX0
BINFMT MOD0 LOAD
AD0
AD1
C14
C15
C13
C10
C8
C9
C2
C6
OEIEXT DET0
TICO
PACI PMSEL CLROFR ENTIREG CS
C3
C1
OER
GND
Q
V
GND ENPHAC ENI
CLK
5
WR
6
V
GND
8
C12
9
C11
10
C7
11
C5
12
C4
13
C0
14
V
CC
CC
CC
1
2
3
4
7
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
5
HSP45116/883
Burn-in Circuit
PGA
PIN
PIN
NAME
BURN-IN-
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
D3
C2
D2
E3
C1
E2
D1
F3
F2
E1
G2
G3
F1
H2
H3
J3
IMIN(0)
RIN(18)
RIN(17)
RIN(16)
RIN(15)
RIN(14)
RIN(13)
RIN(12)
RIN(11)
RIN(10)
RIN(9)
F4
F9
Q3
P5
ENPHAC
ENTIREG
ENI
F1
F4
K14
L15
J14
J13
K15
H14
H13
G13
G15
F15
G14
F14
F13
E15
E14
D15
C15
D14
E13
C14
B15
D13
C13
B14
C12
B13
RO(2)
RO(3)
RO(4)
RO(5)
RO(6)
RO(7)
RO(8)
RO(9)
RO(10)
RO(11)
RO(12)
RO(13)
RO(14)
RO(15)
RO(16)
RO(17)
RO(18)
RO(19)
IO(0)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
A10
B8
C8
C7
A7
A6
B7
B6
C6
A5
B5
A4
A3
B4
C5
B3
A2
C4
C3
B2
A1
A9
A15
G1
J15
Q1
IO(18)
IO(19)
V
V
/2
/2
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
F9
F8
Q4
F1
IMIN(18)
IMIN(17)
IMIN(16)
IMIN(15)
IMIN(14)
IMIN(13)
IMIN(12
IMIN(11)
IMIN(10)
IMIN(9)
IMIN(8)
IMIN(7)
IMIN(6)
IMIN(5)
IMIN(4)
IMIN(3)
IMIN(2)
IMIN(1)
VC
F7
N6
MODPI/2PI
CS
F16
F2
F8
F7
F6
F5
F4
F6
P6
F5
Q5
CLK
F0
F4
P7
AD(1)
AD(0)
WR
F4
F16
F15
F14
F13
F12
F11
F10
F9
N7
F3
Q6
F1
F16
F15
F14
F13
F12
F11
F10
F9
P8
C(15)
C(14)
C(13)
C(12)
C(11)
C(10)
C(9)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N8
RIN(8)
N9
RIN(7)
Q9
RIN(6)
Q10
P9
RIN(5)
RIN(4)
F8
P10
N10
Q11
P11
Q12
Q13
P12
N11
P13
Q14
N12
J1
RIN(3)
F7
C(8)
F8
K1
J2
RIN(2)
F6
C(7)
F7
RIN(1)
F5
C(6)
F6
K2
K3
L1
RIN(0)
F4
C(5)
IO(1)
F5
SH(1)
F3
C(4)
IO(2)
None
SH(0)
F2
C(3)
IO(3)
V
V
V
V
V
V
CC
None
CC
CC
CC
CC
CC
L2
ACC
F4
C(2)
IO(4)
M1
N1
M2
ENPHREG
ENOFREG
PEAK
F16
F4
C(1)
IO(5)
V
V
CC
C(0)
V
IO(6)
CC
CC
F8
OUT-
F11
IO(7)
None
MUX(1)
L3
RBYTILD
F16
F4
N13
OUT-
MUX(0)
F10
B12
IO(8)
V
/2
Q7
V
V
CC
CC
CC
N2
P1
BINFMT
TICO
P14
M13
N14
M14
L13
OER
OEREXT
OEIEXT
OEI
F0
F0
F0
F0
C11
A13
B11
A12
C10
B10
A11
B9
IO(9)
V
V
V
V
V
V
V
V
V
/2
/2
/2
/2
/2
/2
/2
/2
/2
Q15
A8
V
None
GND
None
None
GND
GND
None
None
GND
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
/2
IO(10)
IO(11)
IO(12)
IO(13)
IO(14)
IO(15)
IO(16)
IO(17)
GND
GND
GND
GND
GND
GND
GND
GND
CC
M3
MOD(1)
MOD(0)
PACI
GND
GND
F4
A14
B1
N3
P2
PACO
DET0
V
/2
H1
CC
CC
CC
CC
CC
N4
LOAD
F15
F1
N15
L14
V
V
V
V
/2
/2
/2
/2
H15
P15
Q2
P3
PMSEL
CLROFR
ENCFREG
DET1
P4
F4
M15
K13
RO(0)
RO(1)
N5
F4
C9
Q8
NOTE:
11. 47kΩ ±20%) resistor connected to all pins except V
and GND.
CC
= 5.5V ±0.5V with 0.1µF (min) capacitor between V
12. V
and GND per position.
CC
CC
13. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2 . . . . . , F11 = F10/2, 40% to 60% duty cycle.
14. Input Voltage limits: V = 0.8V max, V = 4.5V ±10%.
IL
IH
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
350 mils x 353 mils x 19 ± 1mils
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
WORST CASE DENSITY:
Type: Si-Al, or Si-Al-Cu
Thickness: 8kÅ
5
2
1.6 x 10 A/cm
6
相关型号：
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