HSP45240 [INTERSIL]
Address Sequencer; 地址序
Intersil 
HSP45240/883
Address Sequencer
February 1998
Features
Description
• This Circuit is Processed in Accordance to MIL-STD- The Intersil HSP45240/883 is a high speed Address
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Sequencer which provides specialized addressing for func-
tions like FFTs, 1-D and 2-D filtering, matrix operations, and
image manipulation. The sequencer supports block oriented
addressing of large data sets up to 24 bits at clock speeds
up to 40MHz.
• Block Oriented 24-Bit Sequencer
• Configurable as Two Independent 12-Bit Sequencers
• 24 x 24 Crosspoint Switch
Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the
mapping of the 24 address bits at the output of the address
generator to the 24 address outputs of the chip. As a result,
bit reverse addressing, such as that used in FFTs, is made
possible.
• Programmable Delay on 12 Outputs 9-
• Multi-Chip Synchronization Signals
• Standard µP Interface
• 100pF Drive on Outputs
A single chip solution to read/write addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a pro-
grammable delay is provided on 12 of the address outputs.
• DC to 40MHz Clock Rate
Applications
• 1-D, 2-D Filtering
The HSP45240 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configu-
ration of the device is controlled through a standard micro-
processor interface and all inputs/outputs, with the exception
of clock, are TTL compatible.
• Pan/Zoom Addressing
• FFT Processing
• Matrix Math Operations
Ordering Information
TEMP.
RANGE ( C)
PKG.
NO.
o
PART NUMBER
HSP45240GM-25/883
HSP45240GM-33/883
HSP45240GM-40/883
PACKAGE
-55 to 125 68 Ld PGA
-55 to 125 68 Ld PGA
-55 to 125 68 Ld PGA
Block Diagram
STARTOUT
ADDVAL
DONE
BLOCKDONE
12
OUT12-23
REG
STARTIN
24
CROSS-POINT
SWITCH
START
CIRCUITRY
SEQUENCE
GENERATOR
OEH
12
DELAY
1-8
OUT0-11
DLYBLK
OEL
BUSY
PROCESSOR INTERFACE
D0-6, CS, A0, WR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2816.3
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
9-16
HSP45240/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical, Note 1)
Input, Output Voltage Applied. . . . . . . . . . GND -0.5V to V +0.5V PGA Package . . . . . . . . . . . . . . . . . . .
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Package Power Dissipation at 125 C
θ
( C/W)
θ
( C/W)
JA
o
JC
10.1
37.1
CC
PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35W
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Operating Conditions
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8,388
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUB-
GROUPS
LIMITS
o
PARAMETER
SYMBOL
TEST CONDITIONS
TEMPERATURE ( C)
MIN
MAX
UNITS
Logical One Input
Voltage
V
V
V
= 5.5V
1, 2, 3
-55 ≤ T ≤ 125
2.2
-
V
lH
DD
DD
A
Logical Zero Input
Voltage
V
= 4.5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
-
0.8
-
V
V
IL
A
Output HlGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
V
I
= -400µA
= 4.5V (Note 2)
-55 ≤ T ≤ 125
2.6
-
OH
OH
A
V
DD
I
V
OL = +2.0mA
-55 ≤ T ≤ 125
0.4
+10
+10
V
OL
A
V
= 4.5V (Note 2)
CC
I
V
V
= V
or GND
= 5.5V
-55 ≤ T ≤ 125
-10
-10
µA
µA
I
IN
CC
A
CC
I
O
V
= V
CC
or GND
-55 ≤ T ≤ 125
A
OUT
V
V
V
= 5.5V
= 5.5V
= 4.5V
CC
CC
CC
Clock lnput High
Clock Input Low
V
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
3.0
-
V
V
IHC
A
V
-55 ≤ T ≤ 125
-
-
0.8
500
ILC
A
I
I
Standby Power Supply
Current
V
V
= V
or GND
= 5.5V,
-55 ≤ T ≤ 125
µA
IN
CC
A
CCSB
CC
Outputs Open
Operating Power
Supply Current
f = 33MHz
V
1, 2, 3
7, 8
-55 ≤ T ≤ 125
-
-
99
-
mA
A
CCOP
= 5.5V (Note 3)
CC
Functional Test
NOTES:
FT
(Note 4)
-55 ≤ T ≤ 125
A
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 3mA/MHz.
4. Tested as follows: t = 1MHz, V = 2.6, V = 0.4, V
IH IL OH
≥ 1.5V, V < 1.5V, V
= 3.4V, and V = 0.4V.
ILC
OL
IHC
9-17
HSP45240/883
TABLE 2. AC ELECTRICAL SPECIFICATIONS
Device Guaranteed and 100% Tested
-25 (25MHz) -33 (33MHz) -40 (40MHz)
MIN MAX MIN MAX MIN MAX
GROUP A
SUBGROUP
TEMPERATURE
o
PARAMETER
Clock Period
SYMBOL
( C)
UNITS
ns
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
39
15
15
17
-
-
-
-
30
12
12
16
-
-
-
-
25
10
10
14
-
-
-
-
CP
A
Clock Pulse Width High
Clock Pulse Width Low
t
-55 ≤ T ≤ 125
ns
CH
A
t
-55 ≤ T ≤ 125
ns
CL
A
Setup Time D0-6 to WR
High
t
-55 ≤ T ≤ 125
ns
DS
A
Hold Time D0-6 from WR
Low
t
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
0
5
0
-
-
-
0
5
0
-
-
-
0
5
0
-
-
-
ns
ns
ns
DH
A
Setup Time A, CS to WR
Low
t
-55 ≤ T ≤ 125
A
AS
AH
Hold Time A, CS from
WR High
t
-55 ≤ T ≤ 125
A
Pulse Width for WR Low
Pulse Width for WR High
WR Cycle Time
t
9, 10, 11
9, 10, 11
9,10,11
-55 ≤ T ≤ 125
18
18
39
15
-
-
-
-
14
14
30
12
-
-
-
-
12
12
25
10
-
-
-
-
ns
ns
ns
ns
WRL
A
t
-55 ≤ T ≤ 125
A
WRH
t
-55 ≤ T ≤ 125
A
WP
Set-up Time STARTIN,
DLYBLK, to Clock High
t
9, 10, 11
-55 ≤ T ≤ 125
A
IS
Hold Time STARTlN,
DLYBLK, to Clock High
t
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
0
-
-
0
-
-
0
-
-
ns
ns
ns
lH
A
Clock to Output Prop.
Delay on OUT0-23
t
-55 ≤ T ≤ 125
18
18
16
16
14
14
PDO
A
Clock to Prop. Delay, on
STARTOUT, BLKDONE,
DONE, ADVAL, and
BUSY
t
-55 ≤ T ≤ 125
-
-
-
PDS
A
Output Enable Time
(Note 6)
t
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
-
22
-
20
-
15
ns
ns
EN
A
RST Low Time
NOTES:
t
-55 ≤ T ≤ 125
2 Clock Cycles
RST
A
5. AC Testing: V
= 4.5V and 5.5V, inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements
are made at 1.5V for both a logic “1” and “‘0”. CLK is driven at 4.0V and 0V and measured at 2.0V.
CC
6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and C = 40pF.
L
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
-25
-33
(25MHz)
(33MHz)
-40 (40MHz)
TEST
PARAMETERS SYMBOL
CONDITIONS
NOTES
TEMPERATURE
T = 25
MIN MAX MIN MAX MIN MAX UNITS
Input
C
V
= Open,
7
-
-
-
10
10
22
-
-
-
10
10
20
-
-
-
10
10
15
pF
pF
ns
IN
CC
A
Capacitance
f = 1MHz, All mea-
surements are
referenced to de-
vice GND.
Output
C
V
= Open,
7
T = 25
A
OUT
CC
Capacitance
f = 1MHz, All mea-
surements are
referenced to de-
vice GND.
Output Disable
t
7, 8
-55 ≤ T ≤ 125
OEZ
A
9-18
HSP45240/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
-25
(25MHz)
-33
(33MHz)
-40 (40MHz)
TEST
PARAMETERS SYMBOL
CONDITIONS
NOTES
TEMPERATURE
-55 ≤ T ≤ 125
MIN MAX MIN MAX MIN MAX UNITS
Output Rise
Time
t
7, 8
-
5
-
5
-
3
ns
OR
A
Output Fall
Time
t
7, 8
-55 ≤ T ≤ 125
A
-
5
-
5
-
3
ns
OF
NOTES:
7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes.
8. Loading is as specified in the test load circuit with C = 40pF.
L
TABLE 4. ELECTRICAL TEST REQUIREMENTS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%
SUBGROUPS
-
Interim Test
PDA
-
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
-
Groups C and D
Samples/5005
9-19
HSP45240/883
Burn-In Circuit
DLY START
BLOCK
DONE
L
K
J
OEH
NC
V
GND OUT1 OUT2
NC
NC
CC
BLK
OUT
START ADD
IN
NC
OEL
BUSY DONE OUTO
V
OUT3
CC
VAL
RST
CLK
V
GND OUT4
CC
H
GND
OUT5
V
CC
G
F
CS
WR
D6
A0
GND
D5
OUT6 OUT7
GND OUT8
E
OUT9
V
CC
D
C
B
A
D4
D2
D0
D3
D1
OUT10 OUT11
GND OUT12
NC OUT22 OUT21 GND OUT18 OUT17 GND OUT14 NC
NC
OUT13
10
GND OUT23
V
OUT20 OUT19
V
OUT16 OUT15
CC
4
CC
7
1
2
3
5
6
8
9
11
BURN-
IN
SIGNAL
BURN-
IN
SIGNAL
BURN-
IN
SIGNAL
BURN-
IN
SIGNAL
PGA
PIN
PIN
NAME
PGA
PIN
PIN
PGA
PIN
PGA
NAME
OUT14
D2
PIN
F11
G1
NAME
OUT8
CSB
PIN
K6
K7
K8
K9
PIN NAME
BUSYB
A2
A3
GND
GND
B9
V
/2
V
/2
V
V
V
/2
/2
/2
CC
CC
CC
CC
CC
OUT23
V
/2
C1
F10
F9
F5
F6
DONEB
OUT0
CC
A4
V
V
C2
D1
G2
A0
CC
CC
A5
OUT20
OUT19
V
V
/2
/2
C10
C11
D1
GND
OUT12
D4
GND
G10
G11
H1
OUT6
OUT7
CLK
V
V
/2
V
V
CC
CC
CC
CC
A6
V
/2
/2
K11 OUT3
V
/2
CC
CC
CC
CC
A7
V
V
F12
F0
GND
/2
L2
L3
L4
LS
L6
L7
L8
L9
OEHB
F13
F11
CC
CC
A8
OUT16
OUT15
OUT13
D0
V
V
V
/2
/2
/2
D2
D3
F11
H2
GND
OUTS
DLYBLK
CC
CC
CC
A9
D10
D11
E1
OUT10
OUT11
D6
V
/2
H10
H11
J1
V
STARTOUTB
V
/2
CC
CC
CC
CC
A10
B1
V
/2
V
V
V
V
CC
CC
CC
CC
/2
F8
F7
F13
/2
RSTB
F14
BLOCKDONEB
GND
V
CC
B3
OUT22
OUT21
GND
V
V
/2
E2
D5
J2
V
V
GND
CC
CC
CC
B4
/2
E10
E11
F1
OUT9
V
J10
J1 1
K3
GND
OUT4
OELB
GND
OUT1
V
/2
CC
CC
CC
B5
GND
V
V
V
/2
OUT2
V
/2
CC
CC
CC
CC
B6
OUT18
OUT17
GND
V
/2
WRB
GND
GND
F4
F12
CC
B7
V
/2
F2
GND
GND
K4
START1NB
ADVALB
F6
CC
B8
GND
F10
K5
V
/2
CC
NOTES:
9. V /2 (2.7V ±10%) used for outputs only.
CC
10. 47Ω (±20%) resistor connected to all pins except V
and GND.
CC
11. V
= 5.5 ±0.5V.
CC
12. 0.1µF (min) capacitor between V
and GND per position.
CC
13. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2....., F11 = F10/2, 40% -60% Duty Cycle.
14. Input voltage limits: V = 0.8V max., V = 4.5V ±10%.
IL IH
9-20
HSP45240/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
186 mils x 222 mils x 19 ±1mils
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Si - Al or Si-Al-Cu
Thickness: 8kÅ
5
2
1.8 x 10 A/cm
Metallization Mask Layout
HSP45240/883
OUT12
GND
D0
D1
OUT11
D2
D3
D4
D5
OUT10
V
CC
OUT9
OUT8
D6
GND
WR
GND
OUT7
OUT6
A0
CS
V
CC
OUT5
OUT4
GND
CLK
V
GND
CC
OUT3
RST
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9-21
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