HSP45116GC-15 [INTERSIL]
Numerically Controlled Oscillator/Modulator; 数控振荡器/调制器
| 型号： | HSP45116GC-15 |
| 厂家： | 
Intersil |
| 描述： | Numerically Controlled Oscillator/Modulator |
| 文件： | 总18页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP45116
Data Sheet
May 1999
File Number 2485.7
Numerically Controlled
Oscillator/Modulator
Features
• NCO and CMAC on One Chip
The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
• 15MHz, 25.6MHz, 33MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
demodulation. As shown in the Block Diagram, the
HSP45116 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
TEMP.
o
PART NUMBER
HSP45116VC-15
HSP45116VC-25
HSP45116GC-15
HSP45116GC-25
HSP45116GC-33
HSP45116GI-15
HSP45116GI-25
HSP45116GI-33
RANGE ( C) PACKAGE
PKG. NO.
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
160 Ld MQFP Q160.28x28
160 Ld MQFP Q160.28x28
145 Ld CPGA G145.A
145 Ld CPGA G145.A
145 Ld CPGA G145.A
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
-40 to 85 145 Ld CPGA G145.A
-40 to 85 145 Ld CPGA G145.A
-40 to 85 145 Ld CPGA G145.A
HSP45116GM-15/883 -55 to 125 145 Ld CPGA G145.A
HSP45116GM-25/883 -55 to 125 145 Ld CPGA G145.A
HSP45116AVC-52
0 to 70
160 Ld MQFP Q160.28x28
† This part has its own data sheet under HSP45116A, AnswerFAX
document no. 4156.
Block Diagram
VECTOR INPUT
R
I
SINE/
COSINE
ARGUMENT
MICROPROCESSOR
PHASE/
SIN
INTERFACE
SINE/
COSINE
SECTION
FREQUENCY
CMAC
CONTROL
COS
INDIVIDUAL
SECTION
CONTROL SIGNALS
R
I
VECTOR OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HSP45116
Pinouts
145 PIN PGA
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
IMIN
4
IMIN
8
IMIN
9
IMIN
11
IMIN
15
IMIN
16
GND
V
IO
18
IO
15
IO
12
IO
10
GND
V
CC
CC
CC
A
B
C
D
E
F
A
B
C
D
E
F
GND
IMIN
1
IMIN
5
IMIN
7
IMIN
10
IMIN
13
IMIN
14
IO
19
IO
16
IO
14
IO
11
IO
8
IO
7
IO
5
IO
2
RIN
15
RIN
18
IMIN
2
IMIN
3
IMIN
6
IMIN
12
IMIN
17
IMIN
18
IO
17
IO
13
IO
9
IO
6
IO
4
IO
1
RO
18
RIN
13
RIN
17
IMIN
0
INDEX
IO
3
RO
19
RO
17
RIN
10
RIN
14
RIN
16
IO
0
RO
16
RO
15
RIN
7
RIN
11
RIN
12
RO
14
RO
13
RO
11
RO
9
RO
12
RO
10
RIN
9
RIN
8
V
CC
G
H
J
G
H
J
GND
RIN
6
RIN
5
RO
8
RO
7
GND
RIN
3
RIN
1
RIN
4
RO
5
RO
4
V
CC
RIN
2
RIN
0
SH
1
RO
1
RO
2
RO
6
K
L
K
L
PACO
DET
1
RO
3
SH
0
ACC RBYTILD
ENPH
REG
PEAK
MOD
1
OEREXT OEI
RO
0
M
N
P
Q
M
N
P
Q
AD
0
C
14
C
13
C
8
C
2
OUT-
MUX
OUT-
MUX
DET
0
ENOF BINFMT MOD
LOAD
ENCF MODPI
OEIEXT
OER
0
REG
REG
/2PI
1
0
TICO
PACI
PMSEL CLROFR ENTIREG
CS
AD
1
C
C
C
9
C
6
C
3
C
1
GND
15
10
V
GND ENPHAC ENI
CLK
5
WR
6
V
GND
8
C
C
C
7
C
5
C
4
C
0
V
CC
CC
1
CC
12
11
2
3
4
7
9
10
11
12
13
14
15
2
HSP45116
Pinouts (Continued)
145 PIN PGA
BOTTOM VIEW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
GND
IO
10
IO
12
IO
15
IO
18
V
GND
IMIN
16
IMIN
15
IMIN
11
IMIN
9
IMIN
8
IMIN
4
V
CC
CC
CC
A
B
C
D
E
F
A
B
C
D
E
F
IO
2
IO
5
IO
7
IO
8
IO
11
IO
14
IO
16
IO
19
IMIN
14
IMIN
13
IMIN
10
IMIN
7
IMIN
5
IMIN
1
GND
RO
18
IO
1
IO
4
IO
6
IO
9
IO
13
IO
17
IMIN
18
IMIN
17
IMIN
12
IMIN
6
IMIN
3
IMIN
2
RIN
18
RIN
15
INDEX
IMIN
0
RIN
17
RIN
13
RO
17
RO
19
IO
3
RIN
16
RIN
14
RIN
10
RO
15
RO
16
IO
0
RIN
12
RIN
11
RIN
7
RO
11
RO
13
RO
14
RO
10
RO
12
RO
9
RIN
8
RIN
9
V
CC
G
H
J
G
H
J
RIN
5
RIN
6
GND
GND
RO
7
RO
8
RIN
4
RIN
1
RIN
3
V
RO
4
RO
5
CC
SH
1
RIN
0
RIN
2
RO
6
RO
2
RO
1
K
L
K
L
RO
3
DET
1
PACO
RBYTILD ACC
SH
0
RO
0
OEI OEREXT
MOD
1
PEAK
ENPH
REG
M
N
P
Q
M
N
P
Q
DET
0
OUT-
MUX
OUT-
MUX
C
2
C
8
C
13
C
14
AD
0
OEIEXT
OER
MODPI ENCF
LOAD
MOD BINFMT ENOF
0
REG
/2PI
REG
0
1
GND
C
1
C
3
C
6
C
9
C
C
AD
1
CS
ENTIREG CLROFR PMSEL
PACI
TICO
10
15
V
C
0
C
4
C
5
C
7
C
C
GND
8
V
WR
6
CLK
5
ENI
4
ENPHAC GND
V
CC
CC
7
CC
12
11
15
14
13
12
11
10
9
3
2
1
3
HSP45116
Pinouts (Continued)
160LEAD MQFP
TOP VIEW
1
2
3
4
5
6
7
8
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
NC
IMIN0
RIN18
RIN17
RIN16
RIN15
RIN14
GND
RIN13
RIN12
RIN11
RIN10
RIN9
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
GND
RIN1
GND
IO6
IO5
IO4
IO3
GND
IO2
IO1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
CC
IO0
RO19
GND
RO18
RO17
RO16
RO15
RO14
103
102
V
CC
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
RO13
RO12
RO11
GND
RO10
RO9
V
CC
RIN0
SH1
SH0
ACC
V
CC
ENPHREG
ENOFREG
PEAK
RBYTILD
BINFMT
GND
RO8
RO7
GND
RO6
RO5
RO4
RO3
TICO
V
V
CC
CC
MOD1
MOD0
PACI
LOAD
PMSEL
NC
RO2
RO1
RO0
GND
DET1
DET0
4
HSP45116
Pin Description
NAME
NUMBER
TYPE
DESCRIPTION
V
A1, A9, A15, G1,
J15, Q1, Q7, Q15
-
+5V Power supply input.
CC
GND
A8, A14, B1, H1,
H15, P15, Q2, Q8
-
I
Power supply ground input.
C0-15
N8-11, P8-13,
Q9-14
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
AD0-1
CS
N7, P7
P6
I
I
I
Address pins for selecting destination of C0-15 data.
Chip Select (active low).
WR
Q6
Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when
the CS line is low.
CLK
Q5
M1
N1
N5
Q3
P5
I
I
I
I
I
I
Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
ENPHREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
Phase Register Enable (active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPHREG enables the clocking of data into the phase register.
Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,
after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.
ENI
Q4
N6
P4
I
I
I
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
MODPI/2PI
CLROFR
Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo π (180 degrees). This input is registered on chip by clock.
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.
LOAD
N4
I
I
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the phase accumulator register.
MOD0-1
M3, N3
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.
These bits are loaded into the phase register when ENPHREG is low.
PMSEL
RBYTILD
PACI
P3
L3
P2
I
I
I
Phase Modulation Select Line. This line determines the source of the data clocked into the phase
register. When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.
ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one, in addition to the values in the phase accumulator register and frequency
adder.
5
HSP45116
Pin Description (Continued)
NAME
NUMBER
TYPE
DESCRIPTION
PACO
L13
O
Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.
TICO
P1
O
I
Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.
RIN0-18
C1, C2, D1, D2, E1-
3, F1-3, G2, G3,
H2, H3, J1-3, K1,
K2
Real Input Data Bus. This is the external real component into the complex multiplier. The bus is
clocked into the real input data register by CLK when ENI is asserted; two’s complement.
IMIN0-18
A2-7, B2-7, C3-8,
D3
I
Imaginary Input Data Bus. This is the external imaginary component into the complex multiplier.
The bus is clocked into the real input data register by CLK when ENI is asserted; two’s
complement.
SH0-1
ACC
K3, L1
L2
I
I
Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the
complex multiplier. The shift controls are common to the shifters on both of the busses.
Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in the accumulators is zeroed to cause the accumulators to load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.
BINFMT
PEAK
N2
M2
I
I
This input is used to convert the two’s complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.
This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the holding registers at the time that PEAK
is activated.
OUTMUX0-1
RO0-19
N12, N13
I
These inputs select the data to be output on RO0-19 and IO0-19.
C15, D14, D15,
E14, E15, F13-15,
G13-15, H13, H14,
J13, J14, K13-15,
L15, M15
O
Real Output Data Bus. These Three-state outputs are controlled by OER and OEREXT.
OUTMUX0-1 select the data output on the bus.
IO0-19
A10-13, B8-15, C9-
14, D13, E13
O
O
Imaginary Output Data Bus. These Three-state outputs are controlled by OEI and OEIEXT.
OUTMUX0-1 select the data output on the bus.
DET0-1
N15, L14
These output pins indicate the number of bits of growth in the accumulators. While PEAK is low,
these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary
accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers.
The bits indicate the largest growth of the four registers.
OER
OEREXT
OEI
P14
M13
M14
N14
I
I
I
I
Three-state control for bits RO0-15. Outputs are enabled when the line is low.
Three-state control for bits RO16-19. Outputs are enabled when the line is low.
Three-state control for bits IO0-15. Outputs are enabled when the line is low.
Three-state control for bits IO16-19. Outputs are enabled when the line is low.
OEIEXT
6
HSP45116
IMIN(18:0)
RIN(18:0)
IMIN(18:0)
RIN(18:0)
2
PHASE
REGISTER
MOD(1:0)
ENCODE
0
PHASE
INPUT
REGISTER
14
16
R
E
R.ENPHREG
CLK
16
G
16
R
E
>
C(15:0)
16
G
PHEN
R.PMSEL
>
MS INPUT
REGISTER
FREQUENCY
ADDER
CENTER FREQUENCY
REGISTER
R
16
E
G
32
32
SIN/COS
ARGUMENT
MSEN
R
E
G
>
32
PHASE
A
D
D
E
R
LS INPUT
REGISTER
CLK
>
OFFSET
FREQUENCY
REGISTER
16
R
E
R.ENCFREG
32
16
16
16
SIN
20
SINE/COSINE
GENERATOR
R
E
G
G
>
32
R
COS
16
32
E
CLK
>
LSEN
G
CLK
>
AD(1:0)
CS
0
32
DECODER
32
R.ENOFREG
WR
R.CLROFR
PHASE
ACCUMULATOR
R.PMSEL
PMSEL
R.ENPHREG
R.ENCFREG
R.ENOFREG
ENPHREG
ENCFREG
ENOFREG
CLROFR
PACO
R
E
G
R
E
G
R.CLROFR
R.LOAD
CLK
>
PHASE
ADDER
LOAD
ENPHAC
MODPI/2PI
R.ENPHAC
R.MODPI/2PI
R.RBYTILD
R.ENTIREG
PHASE
ACCUMULATOR
ADDER
RBYTILD
ENTIREG
CLK
A
0
D
D
E
R
16
>
32
R
E
PHASE
ACCUMULATOR
REGISTER
G
MSB
A
D
D
E
R
CLK
>
CLK
32
32
0
R
E
G
32
15
16 MSBs
CLK
>
R.ENPHAC
32
R.LOAD
PACI
16 LSBs
PACI
R.MODPI/2PI
R.RBYTILD
R.SH(1:0)
R.SH(1:0)
R.ENI
R.ACC
R.PEAK
SH(1:0)
ENI
ACC
PEAK
BINFMT
CLK
R.ENI
R.ACC
R.PEAK
R
E
G
R.BINFMT
R.BINFMT
gram
>
CARRY OUT
TIME
ACCUMULATOR
REGISTER
TICO
32
R
E
G
kDia
CLK
32
>
TIME
INCREMENT
32
OEI
OEIEXT
OER
32
R
E
G
R
E
G
CLK
CLK
>
>
OEREXT
OUTMUX(1:0)
0
32
R.ENTIREG
TICO
PACO
TIME ACCUMULATOR
FutinaBloc
7
HSP45116
IMIN(18:0)
RIN(18:0)
R
E
G
R
E
G
CLK
>
19
19
CLK
>
R.ENI
IMIN0-18
RIN0-18
R.SH(1:0)
SHIFTER
16
SHIFTER
16
CLK
> REG
> REG
> REG
CLK
CLK
> REG
CLK
PHASE
SIN
R
16
E
G
CLK
COS
ADDER
ADDER
>
>
COMPLEX
MULTIPLIER
SIN
R1.ACC
R
E
G
MUX
MUX
16
CLK
0
0
1
0
0
1
COS
> REG
CLK
33
REG < CLK
33
CLK
COMPLEX
ACCUMULATOR
> REG
CLK
> REG
R.RBYTILD
MUX
MUX
ADDER
ADDER
CLK
1
0
0
1
0
ROUND
0
ROUND
> REG
REG <
CLK
CMAC
ACCUMULATOR
REG <
CLK
CLK
REG <
> REG
> REG
REG <
CLK
CLK
CLK
20
35
35
REG <
CLK
0
20
1
0
R.PEAK
MUX
OUTMUX(1:0)
See Table 4
OUTMUX(1:0)
See Table 4
GROWTH
DETECT
MUX
MUX
OUTMUX(1:0)
3
16
FMT
3
16
R.BINFMT
FMT
R.SH(1:0)
R.ENI
R.ENI
OEI
OEIEXT
OER
R.PEAK
R.BINFMT
gram
OEREXT
> REG
CLK
kDia
4
16
4
16
OUTMUX(1:0)
RO(19-16) RO(15:0)
DET(1:0)
IO(19-16) IO(15:0)
FutinaBloc
8
HSP45116
Functional Description
The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16-bit sine and
cosine vectors at a maximum sample rate of 33MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT twiddle
factor; when data is input to the Vector Inputs (see Block
Diagram), the NCOM calculates an FFT butterfly.
register. The overflow bit is used as an output to indicate the
timing of the accumulation overflows. In the Time
Accumulator, the overflow bit generates TICO, the Time
Accumulator carry out (which is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow is
inverted to generate the Phase Accumulator Carry Out,
PACO.
The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32-bit number forms the argument of the sine and
cosine, which is passed to the Sine/Cosine Generator.
Both accumulators are loaded 16 bits at a time over the
C0-15 bus. Data on C0-15 is loaded into one of the three
input registers when CS and WR are low. The data in the
Most Significant Input Register and Least Significant Input
Register forms a 32-bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signal; for example, to load the Center
Frequency Register, the data is loaded into the LS and MS
Input Registers, and ENCFREG is set to zero; the next rising
edge of CLK will pass the registered version of ENCFREG,
R.ENCFREG, to the clock enable of the Center Frequency
Register; this register then gets loaded on the following
rising edge of CLK. The contents of the Input Registers will
be continuously loaded into the Center Frequency Register
as long as R.ENCFREG is low.
As shown in the Block Diagram, the NCOM consists of three
parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the input vector to form the modulated output.
Phase and Frequency Control Section
The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Block Diagram). The
PFCS generates a 32-bit word that represents the current
phase of the sine and cosine waves being generated; the
Sine/ Cosine Argument. Stepping this phase angle from 0
The Phase Register is loaded in a similar manner. Assuming
PMSEL is high, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG is low. If PMSEL is low, MOD0-1 supply
the two most significant bits into the Phase Register (MOD1
is the MSB) and the least significant 14 bits are loaded with
0. MOD0-1 are used to generate a Quad Phase Shift Keying
(QPSK) signal (Table 2).
32
through full scale (2 - 1) corresponds to the phase angle of
o
a sinusoid starting at 0 and advancing around the unit circle
counterclockwise. The PFCS automatically increments the
phase by a preprogrammed amount on every rising edge of
the external clock. The value of the phase step (which is the
sum of the Center and Offset Frequency Registers) is:
TABLE 1. AD0-1 DECODING
AD1
AD0
CS
WR
FUNCTION
32
Signal Frequency
----------------------------------------------
Clock Frequency
0
0
0
Load least significant bits
of frequency input.
↑
Phase Step =
× 2
0
1
0
Load most significant bits
of frequency input.
↑
The PFCS is divided into two sections: the Phase
Accumulator uses the data on C0-15 to compute the phase
angle that is the input to the Sine/Cosine Section
(Sine/Cosine Argument); the Time Accumulator supplies a
pulse to mark the passage of a preprogrammed period of
time.
1
1
0
1
0
X
1
Load phase register.
Reserved.
↑
X
X
X
X
No Operation.
The Phase Accumulator consists of registers and adders
that compute the value of the current phase at every clock. It
has three inputs: Center Frequency, which corresponds to
the carrier frequency of a signal; Offset Frequency, which is
the deviation from the Center Frequency; and Phase, which
is a 16-bit number that is added to the current phase for PSK
The Phase Accumulator and Time Accumulator work on the
same principle: a 32-bit word is added to the contents of a
32-bit accumulator register every clock cycle; when the sum
causes the adder to overflow, the accumulation continues
with the 32 bits of the adder going into the accumulator
9
HSP45116
modulation schemes. These three values are used by the
Phase Accumulator and Phase Adder to form the phase of
the internally generated sine and cosine.
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of CLK
while ENTIREG is low. The output of the Time Accumulator
is the accumulator carry out, TICO. TICO can be used as a
timer to enable the periodic sampling of the output of the
The sum of the values in Center and Offset Frequency
Registers corresponds to the desired phase increment
NCOM. The number programmed into this register equals
32
32
(modulo 2 ) from one clock to the next. For example,
2
x CLK period/desired time interval. TICO is disabled and
loading both registers with zero will cause the Phase
Accumulator to add zero to its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will be a DC signal. If a hexadecimal 00000001 is
loaded into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location in the Sine/Cosine
Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, i.e., the
its phase is initialized by zeroing the feedback path of the
accumulator with RBYTILD.
Sine/Cosine Section
The Sine/Cosine Section (Figure 1) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16-bit sine and cosine inputs to the CMAC.
32
clock frequency divided by 2 . If the input to the Center
Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.
32
16
SIN
MUX
16
16
16
16
16
REG
CLK
COS
32
20
SINE/COSINE
GENERATOR
The operation of the Offset Frequency Control Register is
identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency Control Register and updating the Offset
Frequency Control Register with the value of the frequency
offset - the difference between the carrier frequency and the
frequency of the output signal. A logic low on CLROFR
disables the output of the Offset Frequency Register without
clearing the contents of the register.
CLK
R.RBYTILD
FIGURE 1. SINE/COSINE SECTION
The 20-bit word maps into 2π radians so that the angular
resolution is 2π/2 . An address of zero corresponds to
20
TABLE 2. MOD0-1 DECODE
0 radians and an address of hex FFFFF corresponds to
2π- (2π/2 ) radians. The outputs of the Generator Section
20
MOD1
MOD0
PHASE SHIFT (DEGREES)
are 2’s complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents negative full scale, to 7FFF, which represents
positive full scale. Note that the normal range for two’s
complement numbers is 8000 to 7FFF; the output range of
the SIN/COS generator is scaled by one so that it is
symmetric about 0.
0
0
1
1
0
1
0
1
0
90
270
180
Initializing the Phase Accumulator Register is done by putting
a low on the LOAD line. This zeroes the feedback path to the
accumulator, so that the register is loaded with the current
value of the phase increment summer on the next clock.
The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the complex vector is less than -90.2dB.
The error in the sine or cosine alone is approximately 2dB
better.
The final phase value going to the Generator can be
adjusted using MODPI/2PI to force the range of the phase to
be 0 to 180 (modulo π) or 0 to 360 (modulo 2π). Modulo
2π is the mode used for modulation, demodulation, direct
digital synthesis, etc. Modulo π is used to calculate FFTs.
This is explained in greater detail in the Applications Section.
o
o
o
o
If RBYTILD is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
through 15 of the NCOM with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the
PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.
The Phase Register adds an offset to the output of the
Phase Accumulator. Since the Phase Register is only 16
bits, it is added to the top 16 bits of the Phase Accumulator.
The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
10
HSP45116
The 33-bit real and imaginary outputs of the Complex
Complex Multiplier/Accumulator
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
The CMAC (Figure 2) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0-1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two’s complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two’s
complement.
ROUT = COS x RIN - SIN x IIN
IOUT = COS x IIN + SIN x RIN
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT OUT
MUX MUX
RIN and IIN are latched into the input registers and passed
through the shift stages. Clocking of the input registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.
1
0
RO16-19
RO0-15
IO16-19
IO0-15
0
0
Real CMAC RealCMAC ImagCMAC ImagCMAC
31-34 15-30 31-34 15-30
0
1
1
1
0
1
Real CMAC 0, Real
31-34
ImagCMAC 0, Imag
CMAC 0-14 31-34 CMAC 0-14
Real ACC
16-19
Real ACC
0-15
Imag ACC Imag ACC
16-19
TABLE 3. INPUT SHIFT SELECTION
0-15
SH1
SH0
SELECTED BITS
RIN0-15, IMIN0-15
RIN1-16, IMIN1-16
RIN2-17, IMIN2-17
RIN3-18, IMIN3-18
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
1
0
1
The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.
11
HSP45116
RIN0-18
19
IMIN0-18
19
R.ENI
REG
REG
R.SH0-1
SHIFTER
16
SHIFTER
16
REG
REG
REG
REG
16
16
R1.ACC
SIN
MUX
ADDER
MUX
ADDER
COMPLEX
MULTIPLIER
COS
0
0
REG
REG
33
33
REG
COMPLEX
ACCUMULATOR
REG
MUX
MUX
ADDER
ADDER
0
0
REG
REG
CMAC
ACCUMULATOR
REG
35
REG
35
REG
20
REG
20
R1.ACC
0
R.PEAK
MUX
MUX
3
GROWTH
DETECT
OUTMUX0-1
MUX
3
OUTMUX0-1
R.BINFMT
OEREXT
16
16
FMT
R.BINFMT
OEIEXT
FMT
16
16
REG
OER
OEI
4
4
DET0-1
RO16-19 RO0-15
IO16-19 IO0-15
ENI
R.ENI
R.SH0-1
SH0-1
R1.ACC
R2.ACC
ACC
REG
REG
REG
PEAK
R.PEAK
BINFMT
R.BINFMT
FIGURE 2. COMPLEX MULTIPLIER/ACCUMULATOR; ALL REGISTERS CLOCKED BY CLK
12
HSP45116
The Growth Detect circuitry outputs a two bit value that
TABLE 5. GROWTH ENCODING
NUMBER OF BITS
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DET0-1, is encoded as
shown in Table 5. If PEAK is low, the highest value of
DET0-1 is latched in the Growth Detect Output Register.
o
DET 1
DET 0
OF GROWTH ABOVE 2
0
0
1
1
0
1
0
1
0
1
2
3
The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in Figure 3. Note that the binary point of
the sine, cosine, RIN and IIN is to the right of the most
significant bit, while the binary point of RO and IO is to the
right of the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOMs for FFT applications.
SIN/COS INPUT
15
14
-1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
-2
2
-3
2
-4
2
-5
2
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-2 . 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN)
SH = 00
15
14
-1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
-2
2
-3
2
-4
2
-5
2
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-2 . 2
2
2
2
2
2
2
2
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 00
19
18
17
16
15
14
-1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
4
3
2
1
0
-2
2
-3
2
-4
2
-5
2
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-2
2
2
2
-2 . 2
2
2
2
2
2
2
2
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 01
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
4
3
2
1
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
COMPLEX ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 10
19
18
17
16
15
14
-1
13
-2
12
11
10
9
8
7
6
5
4
3
2
1
0
4
3
2
1
0
-3
2
-4
2
-5
2
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-2
2
2
2
-2 . 2
2
2
2
2
2
2
2
↑
Radix Point
FIGURE 3. BIT WEIGHTING
13
HSP45116
Applications
The NCOM can be used for Amplitude, Phase and Frequency
modulation, as well as in variations and combinations of these
techniques, such as QAM. It is most effective in applications
requiring multiplication of a rotating complex sinusoid by an
external vector. These include AM and QAM modulators and
digital receivers. The NCOM implements AM and QAM
modulation on a single chip, and is a element in demodulation,
where it performs complex down conversion. It can be
combined with the Intersil HSP43220 Decimating Digital Filter
to form the front end of a digital receiver.
RIN IMIN
16
16
NCOM
32
16
CMAC
PFCS
CLK
16
16
RO
D/A
LO
Modulation/Demodulation
Figure 4 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the center frequency register, and the
modulating input is clocked into the real input of the CMAC,
with the imaginary input set to 0. The modulated output is
obtained at the real output of the CMAC. With a sixteen bit,
two’s complement signal input, the output will be a 16-bit real
number, on ROUT0-15 (with OUTMUX = 00).
FIGURE 5. QUADRATURE AMPLITUDE MODULATION (QAM)
The NCOM also works with the HSP43220 Decimating
Digital Filter to implement down conversion and low pass
filtering in a digital receiver (Figure 6). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220s, one
each on the real and imaginary outputs of the HSP45116,
perform low pass filtering and decimation on the down
converted data, resulting in a complex baseband signal.
SIGNAL INPUT
RIN
16
32
SIN
16
CMAC
PFCS
CLK
HSP45116
NCOM
NCOM
HSP43220
DDF
16
MODULATED OUTPUT
RO
COS (wt)
LO
SAMPLED
INPUT
FIGURE 4. AMPLITUDE MODULATION
DATA
By replacing the real input with a complex vector, a similar
setup can generate QAM signals (Figure 5). In this case, the
carrier frequency is loaded into the center frequency register as
before, but the modulating vector now carries both amplitude
and phase information. Since the input vector and the internally
generated sine and cosine waves are both 16 bits, the number
of states is only limited by the characteristics of the
transmission medium and by the analog electronics in the
transmitter and receiver.
SIN (wt)
NCOM
OUTPUT
DDF
OUTPUT
INPUT
The phase and amplitude resolution for the Sine/Cosine section
(16-bit output), delivers a spectral purity of greater than 90dBc.
This means that the unwanted spectral components due to
phase uncertainty (phase noise) will be greater than 90dB
below the desired output (dBc, decibels below the carrier). With
a 32-bit phase accumulator in the Phase/Frequency Control
Section, the frequency tuning resolution equals the clock
0
10MHz
0
20MHz
0
FIGURE 6. CHANNELIZED RECEIVER CHIP SET
32
frequency divided by 2 . For example, a 25MHz clock gives a
tuning resolution of 0.006Hz.
14
HSP45116
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CC
MQFP Package . . . . . . . . . . . . . . . . . .
PGA Package. . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
22.0
23.1
N/A
3
o
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
Operating Conditions
o
Operating Voltage Range. . . . . . . . . . . . . . . . . . . .+4.75V to +5.25V
o
o
o
o
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
(MQFP - Lead Tips Only)
Die Characteristics
Component Count . . . . . . . . . . . . . . . . . . . . . . . 103,000 Transistors
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
High Level Clock Input
SYMBOL
TEST CONDITIONS
MIN
2.0
-
MAX
-
UNITS
V
V
V
V
V
V
= 5.25V
= 4.75V
= 5.25V
= 4.75V
IH
CC
CC
CC
CC
V
0.8
-
V
IL
V
3.0
-
V
IHC
Low Level Clock Input
V
0.8
-
V
ILC
Output HIGH Voltage
V
I
I
= -400mA, V
= 4.75V
= 4.75V
2.6
-
V
OH
OH
CC
Output LOW Voltage
V
= 2.0mA, V
0.4
10
10
500
182
V
OL
OL
CC
Input Leakage Current
I
V
= V
or GND, V
= 5.25V
-10
-10
-
µA
µA
µA
mA
I
IN
CC
CC
or GND, V
I/O Leakage Current
I
V
= V
= 5.25V
O
OUT
CC
or GND V
CC
Standby Power Supply Current
Operating Power Supply Current
I
V
= V
= 5.25V, Note 4
CCSB
IN
CC
CC
or GND, V
I
f = 15MHz, V = V
IN
= 5.25V,
CC
-
CCOP
CC
Notes 2 and 4
o
Capacitance T = 25 C, Note 3
A
PARAMETER
Input Capacitance
Output Capacitance
NOTES:
SYMBOL
TEST CONDITIONS
FREQ = 1MHz, V = Open, All measurements
MIN
MAX
15
UNITS
pF
C
-
-
IN
CC
are referenced to device ground
C
15
pF
O
2. Power supply current is proportional to operating frequency. Typical rating for I
is 10mA/MHz.
CCOP
3. Not tested, but characterized at initial design and at major process/design changes.
4. Output load per test load circuit with switch open and C = 40pF.
L
15
HSP45116
o
o
AC Electrical Specifications
V
= 5.0V ±5%, T = 0 C to 70 C (Note 5)
CC A
-15 (15MHz)
-25 (25.6MHz)
-33 (33MHz)
PARAMETER
SYMBOL
NOTES
MIN
66
26
26
26
26
18
0
MAX
MIN
39
15
15
15
15
13
0
MAX
MIN
30
12
12
12
12
13
0
MAX
UNITS
ns
CLK Period
CLK High
CLK Low
WR Low
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CP
t
ns
CH
t
ns
CL
t
ns
WL
WR High
t
ns
WH
Setup Time; AD0-1, CS to WR Going High
Hold Time; AD0, AD1, CS from WR Going High
Setup Time C0-15 from WR Going High
Hold Time C0-15 from WR Going High
Setup time WR High to CLK High
t
ns
AWS
AWH
CWS
CWH
t
ns
t
20
0
15
0
15
0
ns
t
ns
t
7
20
20
0
16
15
0
12
15
0
ns
WC
Setup Time MOD0-1 to CLK Going High
Hold Time MOD0-1 from CLK Going High
Setup Time PACI to CLK Going High
Hold Time PACI from CLK Going High
t
ns
MCS
t
ns
MCH
t
25
0
15
0
11
0
ns
PCS
t
ns
PCH
Setup ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
t
18
12
12
ns
ECS
Hold Time ENPHREG, ENCFREG, ENOFREG, EN-
PHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
t
0
-
0
-
0
-
ns
ECH
Setup Time RIN0-18, IMIN0-18 to CLK
Going High
t
18
0
-
-
12
0
-
-
12
0
-
-
ns
ns
DS
DH
DO
Hold Time RIN0-18, IMIN0-18 from CLK
Going High
t
CLK to Output Delay RO0-19, IO0-19
CLK to Output Delay DET0-1
CLK to Output Delay PACO
CLK to Output Delay TICO
Output Enable Time OER, OEI, OEREXT, OEIEXT
OUTMUX0-1 to Output Delay
Output Disable Time
t
-
-
-
-
-
-
-
-
40
40
30
30
25
40
20
8
-
-
-
-
-
-
-
-
24
27
20
20
20
28
15
8
-
-
-
-
-
-
-
-
19
20
12
12
20
26
15
6
ns
ns
ns
ns
ns
ns
ns
ns
t
DEO
t
PO
t
TO
OE
MD
t
t
t
6
6
OD
Output Rise, Fall Time
t
RF
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
2.0V; all others 1.5V. Output load per test load circuit with switch closed and C = 40pF. Output transition is measured at V
≥ 1.5V and V
OL
L
OH
≤ 1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.
16
HSP45116
AC Test Load Circuit
S
1
DUT
C
(NOTE)
L
±
I
1.5V
I
OL
OH
SWITCH S1 OPEN FOR I
AND I
CCOP
CCSB
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
Waveforms
t
CP
t
t
CL
CH
CLK
t
t
MCH
MCS
MOD0-1
t
PCH
t
PCS
PACI
t
t
t
ECH
DH
ECS
CONTROL
INPUTS
t
DS
RIN0-19
IIN0-19
t
DO
ROUT0-19
IOUT0-19
t
t
t
DEO
PO
DET0-1
PACO
TICO
TO
FIGURE 7. INPUT AND OUTPUT TIMING
17
HSP45116
Waveforms (Continued)
t
WC
CLK
WR
t
t
WH
WL
t
t
t
AWS
AWH
CS
AD0-1
C0-15
t
t
AWS
AWH
t
CWS
CWH
FIGURE 8. CONTROL BUS TIMING
OUTMUX0-1
OER
OEI
OEREXT
1.5V
1.5V
OEIEXT
t
t
OD
OE
t
MD
RO0-19
IO0-19
1.7V
1.3V
RO0-19
HIGH
IMPEDANCE
HIGH
IMPEDANCE
IO0-19
FIGURE 9. OUTPUT ENABLE, DISABLE TIMING
FIGURE 10. MULTIPLEXER TIMING
2.0V
0.8V
t
t
RF
RF
FIGURE 11. OUTPUT RISE AND FALL TIMES
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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18
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