HM-6514883 [INTERSIL]
1024 x 4 CMOS RAM; 1024 ×4 CMOS RAM
| 型号： | HM-6514883 |
| 厂家： | 
Intersil |
| 描述： | 1024 x 4 CMOS RAM |
| 文件： | 总9页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
HM-6514/883
March 1997
1024 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-
cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
• Common Data Input/Output
Gated inputs allow lower operating current and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
• On-Chip Address Register
Ordering Information
120ns
200ns
300ns
TEMPERATURE RANGE
PACKAGE
PKG. NO.
o
o
HM1-6514S/883
HM1-6514B/883
HM1-6514/883
-55 C to 125 C
CERDIP
F18.3
Pinout
HM-6514/883
(CERDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A6
A5
VCC
A7
A4
A8
A3
A9
A0
DQ0
DQ1
DQ2
DQ3
W
A1
A2
E
GND
PIN
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
A
E
W
D
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN2996.1
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
151
HM-6514/883
Functional Diagram
A
LSB A9
A8
6
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
A7
A6
A5
64 x 64
MATRIX
64
A
A4
6
L
L
G
16 16 16 16
LSB A2
A1
A
GATED
COLUMN
I/O SELECT
LATCHED
ADDRESS
REGISTER
4
A0
A3
A
4
G
4
1 OF 4
E
W
DQ
152
HM-6514/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θ
o
θ
JC
JA
o
CERDIP Package . . . . . . . . . . . . . . . . 75 C/W
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C
15 C/W
o
o
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
o
o
TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
(NOTE 1)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
Output Low Voltage
VOL
VCC = 4.5V
1, 2, 3
-55 C ≤ T ≤ +125 C
-
0.4
V
A
IOL = 3.2mA
o
o
Output High Voltage
VOH
II
VCC = 4.5V
IOH = -1.0mA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
2.4
-1.0
-1.0
-
-
V
A
o
o
Input Leakage Current
VCC = 5.5V,
VI = GND or VCC
-55 C ≤ T ≤ +125 C
+1.0
+1.0
25
µA
µA
µA
A
o
o
Input/Output Leakage
Current
IIOZ
ICCDR
VCC = 5.5 V,
VIO = GND or VCC
-55 C ≤ T ≤ +125 C
A
o
o
Data Retention Supply
Current
VCC = 2.0V,
E = VCC -0.3V,
IO = 0mA
-55 C ≤ T ≤ +125 C
A
o
o
Operating Supply
Current
ICCOP
ICCSB
VCC = 5.5V, (Note 2)
E = 1MHz
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
7
mA
A
o
o
Standby Supply
Current
VCC = 5.5V,
E = VCC-0.3V,
IO = 0mA
-55 C ≤ T ≤ +125 C
50
µA
A
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
153
HM-6514/883
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
GROUP
A SUB-
GROUPS
HM-6514/883
HM-6514S/883 HM-6514B/883
(NOTES 1, 2)
CONDITIONS
TEMPERA-
TURE
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
o
Chip Enable
Access Time
TELQV
TAVQV
TELEH
VCC = 4.5 and
5.5V
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T
-
120
-
200
-
300
ns
(1)
(2)
(5)
A
o
≤ +125 C
o
Address Access
Time
VCC = 4.5 and
5.5V, Note 3
-55 C ≤ T
-
120
-
-
220
-
-
320
-
ns
ns
A
o
≤ +125 C
o
Chip Enable
Pulse Negative
Width
VCC = 4.5 and
5.5V
-55 C ≤ T
120
200
300
A
o
≤ +125 C
o
Chip Enable
Pulse Positive
Width
TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55 C ≤ T
50
-
90
-
120
-
ns
(6)
A
o
≤ +125 C
o
Address Setup
Time
TAVEL
TELAX
TWLWH
TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T
0
-
-
-
-
20
50
-
-
-
-
20
50
-
-
-
-
ns
ns
ns
ns
(7)
(8)
A
o
≤ +125 C
o
Address Hold
Time
VCC = 4.5 and
5.5V
-55 C ≤ T
40
A
o
≤ +125 C
o
Write Enable
Pulse Width
VCC = 4.5 and
5.5V
-55 C ≤ T
120
120
200
200
300
300
(9)
A
o
≤ +125 C
o
Write Enable
Pulse Setup
Time
VCC = 4.5 and
5.5V
-55 C ≤ T
(10)
A
o
≤ +125 C
o
Write Enable
Pulse Hold Time
TELWH
TDVWH
TWHDX
TWLDV
TWLEL
TEHWH
TELEL
VCC = 4.5 and
5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T
120
50
0
-
-
-
-
-
-
-
200
120
0
-
-
-
-
-
-
-
300
200
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
(11)
(12)
(13)
(14)
(15)
(16)
(17)
A
o
≤ +125 C
o
Data Setup Time
VCC = 4.5 and
5.5V
-55 C ≤ T
A
o
≤ +125 C
o
Data Hold Time
VCC = 4.5 and
5.5V
-55 C ≤ T
A
o
≤ +125 C
o
Write Data Delay
Time
VCC = 4.5 and
5.5V
-55 C ≤ T
70
0
80
0
100
0
A
o
≤ +125 C
o
Early Output
High-Z Time
VCC = 4.5 and
5.5V
-55 C ≤ T
A
o
≤ +125 C
o
Late Output
High-Z Time
VCC = 4.5 and
5.5V
-55 C ≤ T
0
0
0
A
o
≤ +125 C
o
Read or Write
Cycle Time
VCC = 4.5 and
5.5V
-55 C ≤ T
170
290
420
A
o
≤ +125 C
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
154
HM-6514/883
TABLE 3. HM-6514/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
HM-6514/883
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
MIN
MAX
UNITS
o
Input Capacitance
CI
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
= +25 C
-
8
pF
A
o
Input/Output
Capacitance
CIO
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
= +25 C
-
10
pF
A
o
Chip Enable Output
Disable Time
TELQX
TEHQZ
VCC = 4.5 and 5.5V
1
1
1
1
1
-55 C ≤ T
≤
≤
≤
≤
≤
5
-
50
80
100
-
A
o
+125 C
o
Chip Enable Output
Disable Time
VCC = 4.5 and 5.5V
HM-6514S/883
-55 C ≤ T
-
ns
ns
ns
V
A
o
+125 C
o
VCC = 4.5 and 5.5V
HM-6514B/883
-55 C ≤ T
-
A
o
+125 C
o
VCC = 4.5 and 5.5V
HM-6514/883
-55 C ≤ T
-
A
o
+125 C
o
High Level Output
Voltage
VOH2
VCC = 4.5V, IO = -100µA
-55 C ≤ T
VCC -0.4
A
o
+125 C
NOTES:
1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major
process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
Samples/5005
Samples/5005
SUBGROUPS
-
Interim Test
PDA
1, 7, 9
1
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
Groups C & D
155
HM-6514/883
Timing Waveforms
(2) TAVQV
(17) TELEL
(7)
(8)
TAVEL
TELAX
(7) TAVEL
A
E
VALID ADD
NEXT ADD
(2) TAVQY
(6)
TEHEL
(6)
TEHEL
(5) TELEH
(1) TELQV
(3) TELQX
(4) TEHQZ
VALID DATA OUT
HIGH Z
HIGH Z
DQ
W
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
TRUTH TABLE
INPUTS
TIME
DATA I/O
REFERENCE
E
W
X
A
X
V
X
X
X
X
V
DQ
FUNCTION
-1
0
1
2
3
4
5
H
Z
Memory Disabled
H
H
H
H
X
Z
Cycle Begins, Addresses are Latched
Output Enabled
L
L
X
V
Output Valid
V
Read Accomplished
H
Z
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
H
Z
The address information is latched in the on-chip registers enabled but data is not valid until during time (T = 2). W must
on the falling edge of E (T = 0). Minimum address set up and remain high throughout the read cycle. After the output data
hold time requirements must be met. After the required hold has been read, E may return high (T = 3). This will disable
time, the addresses may change state without affecting the output buffer and all inputs, and ready the RAM for the
device operation. During time (T = 1) the output becomes
next memory cycle (T = 4).
156
HM-6514/883
Timing Waveforms (Continued)
TELAX
TAVEL
TEVEL
NEXT ADD
A
E
VALID ADD
TELEL
TEHEL
TELEH
TEHEL
TWLEH
TWLWH
TELWL
TWHEH
W
TWLDV
HIGH Z
HIGH Z
DQ
VALID DATA INPUT
TDVWH
TWHDZ
TELWH
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
E
W
X
X
L
A
X
V
X
X
X
X
V
DQ
Z
FUNCTION
-1
0
1
2
3
4
5
H
Memory Disabled
Z
Cycle Begins, Addresses are Latched
Write Period Begins
L
L
Z
V
Z
Data In is Written
H
X
X
Write Completed
H
Z
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
Z
The write cycle is initiated by the falling edge of E (T = 0), This E and W control timing will guarantee that the data out-
which latches the address information in the on-chip regis- puts will stay disabled throughout the cycle, thus simplifying
ters. There are two basic types of write cycles, which differ in the data input timing. TWLEL and TEHWH must be met, but
the control of the common data-in/data-out bus.
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E
rising edge.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
IF
OBSERVE
IGNORE
Case 1
Case 2
E falls before W
TWLDV
TWLEL
E falls after W and
E rises before W
TWLEL
TEHWH
TWLDV
TWHDX
If a series of consecutive write cycles are to be performed,
W may be held low until all desired locations have been writ-
ten (an extension of Case 2).
Case 2: E falls equal to or after W falls, and E rises before
or equal to W rising
157
HM-6514/883
Test Load Circuit
DUT
(NOTE 1) CL
+
IOH
1.5V
IOL
-
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance.
Burn-In Circuit
HM6514/883 CERDIP
VCC
C1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
F9
F8
A6
A5
A4
A3
A0
A1
A2
E
VCC
A7
F10
F11
F12
A8
F7
F6
A9
F3
DQ0
DQ1
DQ2
DQ3
F4
F5
F0
F2
GND
F1
W
NOTES:
All resistors 47kΩ ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C1 = 0.01µF Min.
158
HM-6514/883
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
5
2
136 x 167 x 19 ±1mils
1.79 x 10 A/cm
METALLIZATION:
Type: Si - Al
LEAD TEMPERATURE (10s soldering):
o
300 C
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ± 1kÅ
Metallization Mask Layout
HM-6514/883
A6
A5
VCC
A7
A4
A3
A8
A9
DQ0
DQ1
A0
A1
A2
DQ2
E
GND W
DQ3
NOTE:
1. Pin numbers correspond to DIP Package only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
159
相关型号：
©2020 ICPDF网 联系我们和版权申明