HM-6516 [INTERSIL]
2K x 8 CMOS RAM; 2K ×8 CMOS RAM
| 型号： | HM-6516 |
| 厂家： | 
Intersil |
| 描述： | 2K x 8 CMOS RAM |
| 文件： | 总6页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM-6516
2K x 8 CMOS RAM
March 1997
Features
Description
• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows
easy memory board layouts, flexible enough to accommo-
date a variety of PROMs, RAMS, EPROMs, and ROMs.
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V V
• TTL Compatible
CC
• Static Memory Cells
The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
eration microprocessors which employ
a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B-9
200ns
HM1-6516-9
TEMP. RANGE
PACKAGE
CERDIP
PKG. NO.
o
o
-40 C to +85 C
F24.6
F24.6
F24.6
J32.A
J32.A
o
o
-
29102BJA
-55 C to +125 C
JAN#
o
o
8403607JA
8403601JA
HM4-6516-9
8403601ZA
-55 C to +125 C
SMD#
o
o
-
-40 C to +85 C
CLCC
SMD#
o
o
8403607ZA
-55 C to +125 C
Pinouts
HM-6516
(CERDIP)
TOP VIEW
HM-6516
(CLCC)
TOP VIEW
PIN
DESCRIPTION
No Connect
1
4
3
2
32 31 30
1
2
24
23
22
21
20
19
18
17
16
15
14
13
A7
A6
V
CC
NC
29
28
27
26
25
24
23
22
A8
A9
NC
A6
A5
5
6
A8
3
A5
A9
A0 - A10 Address Inputs
4
W
A4
A4
A3
7
8
E
Chip Enable/Power Down
5
A3
G
W
6
A2
A10
E
V
/GND Ground
G
A2
9
SS
7
A1
A1
A10
E
10
11
12
13
8
DQ0 - DQ7 Data In/Data Out
A0
DQ7
DQ6
DQ5
DQ4
DQ3
A0
9
DQ0
DQ1
DQ2
GND
V
Power (+5V)
Write Enable
Output Enable
CC
10
11
12
NC
DQ0
DQ7
W
G
21 DQ6
14
15 16 17 18 19 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2998.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19996-1
HM-6516
Functional Diagram
A
A
A10
A9
7
7
GATED
ROW
LATCHED
ADDRESS
REGISTER
A8
A7
A6
A5
A4
128 x 128
MATRIX
128
DECODER
1 OF 8
L
G
16
16
16
16
16 16 16 16
DQ0
G
A
GATED COLUMN
DECODER
THRU
DQ7
8
8
G
W
E
A
4
4
A
A
L
LATCHED ADDRESS
REGISTER
A3
A2
A1
A0
6-2
HM-6516
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance
θ
θ
JC
JA
o
o
Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to
+0.3V
CERDIP Package . . . . . . . . . . . . . . . . 48 C/W
CLCC Package . . . . . . . . . . . . . . . . . . 66 C/W
8 C/W
o
o
V
12 C/W
CC
o
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Die Characteristics
Operating Temperature Ranges:
o
o
HM-6516B-9, HM-6516-9 . . . . . . . . . . . . . . . . . . . -40 C to +85 C
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6516B-9, HM-6516-9)
CC
A
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
ICCSB
Standby Supply Current
-
50
µA
IO = 0mA, VI = V
or GND,
CC
= 5.5V, HM-6516B-9
V
CC
-
-
-
-
100
10
µA
mA
µA
µA
IO = 0mA, VI = V
HM-6516-9
or GND,
CC
ICCOP
ICCDR
Operating Supply Current (Note 1)
Data Retention Supply Current
f = 1MHz, IO = 0mA, G = V , V =
CC CC
5.5V, VI = V
or GND
CC
25
V
= 2.0V, IO = 0mA, VI = V
or
or
CC
GND, E = V , HM-6516B-9
CC
CC
CC
50
V
= 2.0V, IO = 0mA, VI = V
CC
GND, E = V , HM-6516-9
CC
VCCDR
II
Data Retention Supply Voltage
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
2.0
-1.0
-1.0
-0.3
2.4
-
-
V
µA
µA
V
+1.0
+1.0
0.8
VI = V
or GND, V
= 5.5V
CC
CC
IIOZ
VIO = V
or GND, V
= 5.5V
CC
CC
V
V
V
= 4.5V
= 5.5V
IL
CC
CC
V
Input High Voltage
V
+0.3
V
IH
CC
VOL
Output Low Voltage
0.4
V
IO = 3.2mA, V
= 4.5V
= 4.5V
CC
VOH1
VOH2
Output High Voltage
2.4
-
-
V
IO = -1.0mA, V
CC
CC
Output High Voltage (Note 2)
V
-0.4
V
IO = -100µA, V
= 4.5V
CC
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
MAX
8
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
pF
pF
f = 1MHz, All measurements are
referenced to device GND
CIO
Input/Output Capacitance (Note 2)
10
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
6-3
HM-6516
o
o
AC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6516B-9, HM-6516-9)
CC
A
LIMITS
HM-6516B-9
HM-6516-9
MIN MAX
TEST
CONDITIONS
SYMBOL
(1) TELQV
(2) TAVQV
(3) TELQX
(4) TWLQZ
(5) TEHQZ
(6) TGLQV
(7) TGLQX
(8) TGHQZ
(9) TELEH
(10) TEHEL
(11) TAVEL
(12) TELAX
(13) TWLWH
(14) TWLEH
(15) TELWH
(16) TDVWH
(17) TWHDX
(18) TELEL
PARAMETER
MIN
-
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Access Time
120
-
-
200
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
Address Access Time
-
120
200
Chip Enable Output Enable Time
Write Enable Output Disable Time
Chip Enable Output Disable Time
Output Enable Output Valid Time
Output Enable Output Enable Time
Output Enable Output DisableTime
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
10
-
-
50
50
80
-
10
-
-
80
80
80
-
-
-
-
-
10
-
10
-
50
-
80
-
120
50
0
200
80
0
-
-
-
-
Address Hold Time
30
120
120
120
50
10
170
-
50
200
200
200
80
10
280
-
Write Enable Pulse Width
-
-
Write Enable Pulse Setup Time
Write Enable Pulse Hold Time
Data Setup Time
-
-
-
-
-
-
Data Hold Time
-
-
Read or Write Cycle Time
-
-
NOTES:
1. Input pulse levels: 0.8V to V
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
CC
1 TTL gate equivalent, C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.
L
L
2. Tested at initial design and after major design changes.
3. V = 4.5V and 5.5V.
CC
4. TAVQV = TELQV + TAVEL.
6-4
HM-6516
Timing Waveforms
(2)
TAVQV
(12)
TELAX
(11)
TAVEL
(11)
TAVEL
A
VALID ADD
NEXT
ADD
(18)
TELEL
(10)
TEHEL
(9)
TELEH
(10)
TEHEL
E
HIGH
W
(1)
TELQV
(5)
(5)
TEHQZ
TEHQZ
(3)
TELQX
DQ
G
VALID DATA OUT
TGHQZ
(6)
TGLQV
(8)
(7)
TGLQX
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
The address information is latched in the on-chip registers remain high throughout the read cycle. After the data has
on the falling edge of E (T = 0), minimum address setup and been read, E may return high (T = 3). This will force the out-
hold time requirements must be met. After the required hold put buffers into a high impedance mode at time (T = 4). G is
time, the addresses may change state without affecting used to disable the output buffers when in a logical “1” state
device operation. During time (T = 1), the outputs become (T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
enabled but data is not valid until time (T = 2), W must
the next cycle.
Timing Waveforms (Continued)
(12)
TELAX
(11)
(11)
TAVEL
TAVEL
A
NEXT ADD
VALID ADD
(18)
TELEL
(10)
TEHEL
(9)
TELEH
(10)
TEHEL
E
(14)
TWLEH
(13)
TWLWH
W
(15)
TELWH
(16)
TDVWH
(17)
TWHDX
DQ
G
VALID DATA IN
HIGH
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
6-5
HM-6516
The write cycle is initiated on the falling edge of E (T = 0), rises, reference data setup and hold times to the E rising
which latches the address information in the on-chip edge. The write operation is terminated by the first rising edge
registers. If a write cycle is to be performed where the output of W (T = 2) or E (T = 3). After the minimum E high time
is not to become active, G can be held high (inactive). (TEHEL), the next cycle may begin. If a series of consecutive
TDVWH and TWHDX must be met for proper device opera- write cycles are to be performed, the W line may be held low
tion regardless of G. If E and G fall before W falls (read until all desired locations have been written. In this case, data
mode), a possible bus conflict may exist. If E rises before W setup and hold times must be referenced to the rising of E.
Typical Performance Curve
V
= 2.0V
CC
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-55
-35
-15
5
25
45
65
85
105
125
FIGURE 3. TYPICAL ICCDR vs T
A
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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