HIP5500 [INTERSIL]

High Voltage IC Half Bridge Gate Driver; 高电压IC半桥栅极驱动器
HIP5500
型号: HIP5500
厂家: Intersil    Intersil
描述:

High Voltage IC Half Bridge Gate Driver
高电压IC半桥栅极驱动器

驱动器 栅极 栅极驱动
文件: 总12页 (文件大小:910K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HIP5500  
®
July 1998  
File Number 3210.3  
Features  
High Voltage IC Half Bridge Gate Driver  
• 500V Maximum Rating  
The HIP5500, a high voltage integrated circuit (HVIC) half-  
bridge gate driver for standard power MOSFETs, IGBTs,  
and the new Intersil Buffered MOSFET (RFV10N50BE), can  
be employed in a wide variety of switching regulator circuits.  
• 2A Peak Gate Drive  
• Ability to Interface and Drive N-Channel Power  
Devices With Complimentary Outputs For Buffered  
FETs  
The HIP5500 combines the functionality and flexibility of a  
PWM IC with the convenience of a high voltage half-bridge  
driver optimized for power supply inverters. It can be used  
either open-loop or in closed-loop fashion using the SS input  
for controlling the output waveform duty-cycle.  
• Fault Output, Overcurrent Detection and Undervoltage  
Holdoff  
• Over 600kHz Sawtooth Oscillator Frequency  
• Adjustable Deadtime Control  
The HIP5500 incorporates a precision oscillator, adjustable  
using an external resistor and capacitor. The resistor sets  
the capacitor charging current and the capacitor sets the  
integration time of a triangle wave. Another resistor  
connected to the DIS pin adjusts the dead-time and can be  
tailored to the application. The oscillator switches at twice  
the output waveform fundamental frequency. The result is an  
output waveform whose positive and negative half-cycles  
are near perfect balance (volt-second equalization).  
• Soft-Start Capability  
• Low Current Standby State  
• Sleep Mode Reduces Bias Current When Not Enabled  
Applications  
• Switching and Distributed Power Supplies  
• Electronic Lighting Supplies  
Short-Detect (SD) and Soft-Start (SS) inputs provide  
alternative means for limiting and regulating respectively the  
half-bridge output voltage. A capacitor on the SS input will  
begin charging up once the EN input is made high and  
causes the duty cycle of each half-cycle to “ramp” the duty  
cycle of the output waveform.  
Ordering Information  
The SD input can sense a signal proportional to current,  
providing a means of shortening the conduction periods  
below that imposed by the SS input.  
PART  
NUMBER  
TEMPERATURE  
RANGE  
PACKAGE  
o
o
HIP5500IP  
HIP5500IB  
-40 C to +85 C  
20 Lead Plastic DIP  
Other circuits within the HIP5500 “match” upper and lower  
turn-on and turn-off propagation times in order to minimize  
flux imbalances when driving output transformer loads.  
o
o
-40 C to +85 C  
20 Lead Plastic  
SOIC (W)  
Pinout  
HIP5500 (PDIP, SOIC)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
HO  
HO  
NC  
20  
19  
18  
R
T
DIS  
NC  
V
B
17 V  
S
C
T
16 NC  
SD  
FLT  
SS  
15  
14  
13  
12  
NC  
GND  
V
CC  
EN  
LO  
OSC 10  
11 LO  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
HIP5500  
Typical Application Block Diagram  
POWER  
TRANSFORMER  
+
LOAD  
HO  
OSC  
FLT  
SD  
HO  
HO  
HO  
TO  
BUFFERED  
FETs  
BUFFERED  
FETs  
+
V
B
EN  
500VDC  
DIS  
V
S
C
V
R
T
LO  
LO  
LO  
LO  
CC  
T
TO  
BUFFERED  
FETs  
SS  
GND  
+
15VDC  
-
Functional Block Diagram  
V
CC  
FLT  
NOR  
LATCH  
V
B
SD  
V
CC  
V
CC  
V
B
UV  
OSC  
V
CC  
V
S
BUFFER  
HO  
HO  
LEVEL  
SHIFT  
UPPER  
DRIVE  
R
C
T
T
OSCILLATOR  
V
CC  
V
S
DFF  
D
Q
CK QN  
DIS  
LO  
LO  
LOWER  
DRIVE  
V
CC  
CURRENT  
SOURCE  
GND  
EN  
UV  
SS  
V
CC  
2
HIP5500  
Absolute Maximum Ratings  
Thermal Information  
Offset Supply Voltage, V . . . . . . . . . . . . . . . . . . . . .-V  
to +500V  
Floating Supply Voltage (V to V ) . . . . . . . . . . . . . . -0.3V to +18V  
Thermal Resistance  
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 C/W  
Plastic SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . 80 C/W  
θ
JA  
S
BS  
o
B
S
o
High Side Channel Output Voltage, V , V  
. V -0.5 to V +0.5  
HO NHO  
S
B
Fixed Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . -0.5V to +18V  
See Maximum Power Dissipation vs Temperature Curve Figure 21  
CC  
Low Side Channel Output Voltage . . . . . . . . . . . -0.5V to V  
All Other Pin Voltages  
+0.5V  
CC  
(SD, R , C , DIS, SS, EN and FLT). . . . . . . . . -0.5V to V  
Storage Temperature Range . . . . . . . . . . . . . . . . . -40 C to +150 C  
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125 C  
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C  
+0.5V  
o
T
T
CC  
o
o
o
(SOIC - Lead Tips Only)  
Offset Supply Maximum dv/dt, dV /dt . . . . . . . . . . . . . . . . . . 50V/ns  
S
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
o
o
Recommended Operating Conditions (T = -40 C to +125 C Unless Otherwise Noted, All Voltages Referenced to V  
)
J
SS  
Discharge Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Min  
Discharge Resistor Range, R . . . . . . . . . . . . . . . . . 1kto 50kΩ  
Offset Supply Voltage, V . . . . . . . . . . . . . . . . . . . . -2.0V to +500V  
S
Floating Supply Voltage, V  
(V to V ) . . . . . . . . . . +10V to +15V  
BS  
B S  
DIS  
Charging Resistor Range, R . . . . . . . . . . . . . . . . . .6.8kto 400kΩ  
Oscillator Capacitor Range, C . . . . . . . . . . . . . . . . . 100pF to 0.1µF  
Oscillator Frequency Range . . . . . . . . . . . . . . . . . . . . . 300kHz Max  
Oscillator Capacitor Charge Current Range, I  
High Side Channel Output Voltage, V ,V  
. . . . . . . 0V to V  
BS  
HO NHO  
. . . . . . . . . . . . . . . . . . . . +10V to +15V  
T
Fixed Supply Voltage, V  
CC  
Low Side Channel Output Voltage, V ,V  
T
. . . . . . . . . 0V to V  
LO NLO  
All Other Pin Voltages (SD, R , C , DIS, SS, FLT and EN) 0V to V  
CC  
CC  
. . . . .21µA to 5mA  
T
T
R
T
Electrical Specifications  
V
= V = +15V, V = GND = 0V, Unless Otherwise Specified  
CC BS S  
o
T
= -40 C  
J
o
o
T
= +25 C  
TO +125 C  
J
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
-
TYP  
5.5  
300  
0.4  
2.0  
110  
7.8  
2
MAX  
7.0  
400  
3.0  
3.5  
145  
8.5  
-
MIN  
-
MAX  
8.0  
435  
-
UNITS  
mA  
µA  
µA  
mA  
µA  
V
Quiescent V  
CC  
Current  
I
QCC  
Quiescent V Current  
BS  
I
-
-
QBS  
Quiescent Leakage Current  
I
(V - GND) = 5.0V  
-
-
LK  
S
Standby V  
Current  
I
R
1
= 0  
T
-
-
5.0  
160  
8.6  
-
CC  
STBY  
2
SS Current Source  
I
/ V  
< V  
SFT  
<
/ V  
3 CC  
70  
7.5  
-
60  
7.4  
-
SFT/PWM  
3
CC  
Input Threshold  
V
Low to High Transition  
EN  
EN-HYS  
Input Hysteresis  
V
V
Undervoltage Threshold  
Undervoltage Threshold  
Undervoltage Hysteresis  
Short Detect Threshold  
V
High to Low Transition  
Low to High Transition  
7.7  
7.9  
0.08  
3.5  
0.9  
8.6  
8.8  
0.3  
4.0  
1
9.5  
9.7  
0.7  
4.5  
1.1  
7.4  
7.6  
0.05  
3.4  
0.85  
9.6  
9.8  
0.75  
4.6  
1.15  
V
UVHL  
V
V
UVLH  
V
V
UVHYS  
V
V
THSD  
C /R Current Ratio  
I
I
R
V
= 100µA,  
µA  
T
T
CTRAT  
T
2
/3 < V  
<
/ V  
CC  
CC  
CT  
3
HO, LO Peak Output Current  
HO, LO Peak Output Current  
LO, HO Peak Output Current  
LO, HO Peak Output Current  
I
+
Sourcing, LO, HO = GND  
1.5  
1.5  
1.95  
2.0  
-
-
-
-
1.0  
1.0  
-
-
-
-
A
A
OUT  
I
-
Sinking, LO, HO = V  
= V  
BS  
OUT  
CC  
I
+
Sourcing, LO, HO = Vss  
170  
170  
250  
230  
110  
110  
mA  
mA  
BUF  
I
-
Sinking, LO, HO = V  
CC  
= V  
BS  
BUF  
3
HIP5500  
Electrical Specifications  
V
= V = +15V, V = GND = 0V, Unless Otherwise Specified (Continued)  
CC  
BS  
S
o
T
= -40 C  
J
o
o
T
= +25 C  
TO +125 C  
J
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
7.5  
7.2  
9.8  
5.0  
4.5  
TYP  
7.8  
MAX  
8.1  
MIN  
7.4  
7.1  
9.7  
4.9  
4.4  
MAX  
8.2  
UNITS  
Soft-Start V  
Soft-Start V  
, Low to High  
, High to Low  
V SSHL  
C
C
= 7.5V  
V
V
V
V
V
THRESH  
T
T
T
V SSLH  
7.5  
7.8  
7.9  
THRESH  
T
OSC Input Upper Threshold  
OSC Input Upper Threshold  
V CTLH  
10.4  
5.6  
11.0  
6.2  
11.1  
6.3  
T
V CTHL  
T
to DIS  
Oscillator Upper to Lower  
Threshold Difference  
VCTDIF  
V CTLH - V CTHL  
4.8  
5.1  
5.2  
T
T
OSC_OUT R ON, Sinking  
DS  
OSCR  
L
I
I
I
I
= -50mA  
= 50mA  
5
8.5  
19  
12  
30  
2
9
17  
40  
DS  
OSC_OUT  
OSC_OUT R ON, Sourcing  
DS  
OSCR H  
14  
D
OSC_OUT  
DIS Output On Resistance  
FLT Output On Resistance  
R
DIS  
DS  
= 10mA  
75  
115  
165  
150  
230  
-
200  
320  
DIS  
FLT  
R
FLT  
DS  
= 5mA  
100  
40  
Dynamic Electrical Specifications  
V
= V = +15V, GND = 0V, Unless Otherwise Specified  
BS  
CC  
T
J
= -40oC  
TO +125 C  
o
o
T
= +25 C  
J
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= 2000pF  
MIN  
TYP  
-
MAX  
50  
MIN  
MAX  
UNITS  
ns  
Turn-On Rise Time, HO, LO  
Turn-Off Fall Time, HO, LO  
Turn-On Rise Time, HO, LO  
Turn-Off Fall Time, HO, LO  
t
C
C
C
C
C
-
-
-
-
-
-
-
-
-
-
-
DR  
L
t
= 2000pF  
-
50  
-
ns  
DF  
L
t
= 200pF  
= 200pF  
25  
25  
475  
35  
-
-
ns  
DNR  
BUF  
BUF  
t
35  
ns  
DNF  
C
C
Fall to LO/HO Rise  
Rise to LO/HO Fall  
T CTLH  
= V CTHL  
700  
925  
ns  
T
T
P
T
T
LO/HO LOAD = 200pF  
T CTHL  
P
C
= V CTLH  
-
475  
700  
-
925  
ns  
T
T
LO/HO LOAD = 200pF  
LO-HO Prop Delay Mismatch  
Delmatch  
T CTLH and T CTHL  
-
-
-
-
-
-
60  
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
P
P
C
C
Rise to DIS Fall  
Fall to DIS Rise  
T CTDISHL  
C
= V CTHL  
300  
600  
200  
425  
500  
450  
800  
-
475  
825  
-
T
T
P
T
T
T
T CTDISLH  
C
= V CTLH  
P
T
Minimum Dead Time  
t
DTMIN  
Short Detect Propagation Delay  
t
SD = V  
, LO/HO = 200pF  
THSD  
850  
750  
1100  
775  
SDLO/HO  
Soft-Start Propagation Delay  
Time  
t
SS = V SSLH, LO/HO =  
T
200pF  
SSDLY  
4
HIP5500  
o
Typical Performance Curves All Curves are V = +15V, T = +25 C, Unless Otherwise Specified  
CC  
A
100.0  
50  
6.4  
6.2  
6.0  
5.8  
5.6  
5.4  
5.2  
5.0  
4.8  
4.6  
4.4  
4.2  
4.0  
3.8  
3.6  
3.4  
20  
10.0  
5
V
= 15V  
CC  
2
1.0  
0.5  
0.2  
0.1  
0.05  
V
V
= 12V  
= 10V  
CC  
0.02  
0.01  
0.005  
CC  
-40  
-20  
0
+20  
+40  
+60  
+80 +100 +120  
o
-40  
-20  
0
+20  
+40  
+60  
+80 +100 +120  
TEMPERATURE ( C)  
o
TEMPERATURE ( C)  
FIGURE 1. OFFSET SUPPLY LEAKAGE CURRENT vs  
TEMPERATURE AT 300VDC  
FIGURE 2. QUIESCENT V  
CURRENT vs TEMPERATURE  
CC  
SUPPLY VOLTAGE  
AND V  
CC  
3.4  
3.2  
3.0  
2.8  
2.6  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
325  
V
= 15V  
BS  
V
V
= 15V  
= 12V  
CC  
CC  
275  
225  
175  
125  
V
= 12V  
BS  
V
= 10V  
0
BS  
V
= 10V  
+20  
CC  
-40  
-20  
0
+40  
+60  
o
+80  
+100  
+120  
-40  
-20  
+20  
+40  
+60  
o
+80 +100 +120  
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 3. QUIESCENT FLOATING BIAS SUPPLY CURRENT  
vs TEMPERATURE AND V SUPPLY VOLTAGE  
FIGURE 4. QUIESCENT STANDBY CURRENT vs  
TEMPERATURE AND V SUPPLY VOLTAGE  
BS  
CC  
65  
60  
55  
50  
45  
40  
35  
2.0  
1.9  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
V
V
V
= 10V  
= 12V  
= 15V  
CC  
CC  
CC  
V
= 15V  
CC  
V
V
V
= 10V  
= 12V  
= 15V  
CC  
CC  
CC  
V
V
= 12V  
= 10V  
CC  
CC  
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
-40  
-20  
0
+20  
+40  
+60  
o
+80 +100 +120  
o
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 6. ENABLE/DISABLE HYSTERESIS VOLTAGE  
TEMPERATURE AND V SUPPLY VOLTAGE  
FIGURE 5. ENABLE/DISABLE THRESHOLD (PERCENT V  
)
CC  
SUPPLY VOLTAGE  
vs TEMPERATURE AND V  
CC  
CC  
5
HIP5500  
o
Typical Performance Curves All Curves are V = +15V, T = +25 C, Unless Otherwise Specified (Continued)  
CC  
A
120  
110  
100  
90  
1.9  
V
V
V
= 10V  
= 12V  
= 15V  
1.7  
1.5  
1.3  
1.1  
0.9  
0.7  
0.5  
CC  
CC  
CC  
V
V
V
= 15V  
= 12V  
= 10V  
CC  
CC  
CC  
80  
-40  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
TEMPERATURE ( C)  
o
TEMPERATURE ( C)  
FIGURE 7. SOFT-START CURRENT SOURCE CURRENT vs  
TEMPERATURE AND V SUPPLY VOLTAGE  
FIGURE 8. FAULT_NOT LOW LEVEL OUTPUT VOLTAGE vs  
TEMPERATURE AND V  
SINKING 5mA  
SUPPLY VOLTAGE,  
CC  
CC  
100  
80  
60  
40  
20  
0
1.00  
0.98  
0.96  
0.94  
0.92  
0.90  
V
V
V
= 15V  
= 12V  
= 10V  
CC  
CC  
CC  
V
= 15V  
= 12V  
= 10V  
CC  
CC  
CC  
V
V
-40  
-20  
0
+20  
+40  
+60  
+80 +100 +120  
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
o
o
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 9. C RAMP TRIGGER AND DISCHARGE VOLTAGE  
FIGURE 10. C TO R CURRENT SOURCE RATIO vs  
T
T
T
TRIP POINT vs TEMPERATURE AND V  
VOLTAGE  
SUPPLY  
TEMPERATURE  
CC  
27.5  
27.0  
26.5  
26.0  
25.5  
25.0  
V
V
V
= 15V  
= 12V  
= 10V  
CC  
CC  
CC  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
TEMPERATURE ( C)  
FIGURE 11. SHUTDOWN THRESHOLD VOLTAGE (% OF V ) vs TEMPERATURE AND V  
CC  
SUPPLY VOLTAGE  
CC  
6
HIP5500  
o
Typical Performance Curves All Curves are V = +15V, T = +25 C, Unless Otherwise Specified (Continued)  
CC  
A
340  
320  
300  
280  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
340  
320  
300  
280  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
V
= 15V  
CC  
CC  
V
= 15V  
= 12V  
CC  
CC  
V
= 12V  
V
V
= 10V  
CC  
V
= 10V  
CC  
60  
60  
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
o
o
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 12. BUFFER GATE OUTPUT SHORT CIRCUIT SINKING  
FIGURE 13. BUFFER GATE OUTPUT SHORT CIRCUIT  
SOURCING CURRENT vs TEMPERATURE AND  
CURRENT vs TEMPERATURE AND V  
SUPPLY VOLTAGE  
CC  
V
SUPPLY VOLTAGE  
CC  
10.0  
9.5  
9.0  
8.5  
8.0  
7.5  
10.0  
9.5  
9.0  
8.5  
8.0  
7.5  
TRIP  
TRIP  
RESET  
RESET  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
o
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 14. LOW-SIDE UNDERVOLTAGE THRESHOLD  
VOLTAGE (TRIP/RESET) vs TEMPERATURE  
FIGURE 15. HIGH-SIDE UNDERVOLTAGE THRESHOLD  
VOLTAGE(TRIP/RESET) vs TEMPERATURE  
1.0  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.8  
C
-DIS FALL  
-DIS RISE  
T
0.6  
0.4  
0.2  
0.0  
C
T
-40  
-20  
0
+20  
+40  
+60  
+80  
+100 +120  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
o
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 16. PROPAGATION DELAY, C TO GATE OUTPUTS vs  
FIGURE 17. PROPAGATION DELAY, C TO DIS vs  
T
T
TEMPERATURE AT V  
= +15V  
TEMPERATURE AT V  
= +15V  
CC  
CC  
7
HIP5500  
o
Typical Performance Curves All Curves are V = +15V, T = +25 C, Unless Otherwise Specified (Continued)  
CC  
A
1.6  
1.2  
0.8  
0.4  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
SD-LO FALL  
SD-LO RISE  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
-40  
-20  
0
+20  
+40  
+60  
o
+80  
+100 +120  
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 18. PROPAGATION DELAY, SS TO LO GATE RISING vs  
TEMPERATURE AT V = +15V  
FIGURE 19. PROPAGATION DELAYS, SD TO LO GATE  
RISE/FALL vs TEMPERATURE AT V  
= +15V  
CC  
CC  
3
2.75  
2.5  
2.25  
2
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
HIP5500IP  
HIP5500IB  
1.75  
1.5  
1.25  
1
0.75  
0.5  
0.25  
0
-40  
-20  
0
+20  
+40  
+60  
+80 +100 +120  
o
10  
11  
12  
13  
14  
15  
AMBIENT TEMPERATURE ( C)  
SUPPLY VOLTAGE (V  
)
CC  
FIGURE 20. PROPAGATION DELAY, C TO GATE OUT vs  
T
FIGURE 21. MAXIMUM POWER DISSIPATION vs  
TEMPERATURE  
o
SUPPLY VOLTAGE, V  
AT +25 C FOR  
CC  
RISING AND FALLING GATE OUTPUTS  
10  
1.0  
0.1  
V
C
T
= V = 15V  
V
V
T
= V  
= COM  
BS  
L
A
CC  
S
SS  
= V  
= 100pF  
= 15VDC  
BS  
= +25 C  
CC  
V
V
V
= 400V  
= 300V  
= 200V  
o
S
S
S
o
= +25 C  
A
1.0  
0.1  
V
= 100V  
S
2100pF  
907pF  
100pF  
0.01  
0.001  
0.01  
10  
100  
SWITCHING FREQUENCY (kHz)  
1000  
10  
100  
SWITCHING FREQUENCY (kHz)  
1000  
NOTE: All switching losses assumed to be in IC.  
FIGURE 22. HIGH VOLTAGE POWER DISSIPATION vs  
SWITCHING FREQUENCY  
FIGURE 23. LOW VOLTAGE POWER DISSIPATION vs  
FREQUENCY  
8
HIP5500  
R B S  
9
HIP5500  
COM  
VBUS  
U1  
RG1  
1
1
C
R
T
T
RDIS  
CX  
C 1  
T
SD  
SS  
RSD  
CSS  
REN  
R1  
RBS  
RG2  
EN  
LED1  
OSC  
+15VDC  
V
CC  
C
D
TRANSFORMER  
GND  
T1  
A
CTAP  
B
FIGURE 25. HIP5500 EVALUATION BOARD SILKSCREEN  
10  
HIP5500  
Dual-In-Line Plastic Packages (PDIP)  
E20.3 (JEDEC MS-001-AD ISSUE D)  
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
N
E1  
INDEX  
AREA  
INCHES MILLIMETERS  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.210  
-
MIN  
-
MAX  
5.33  
-
NOTES  
-B-  
-C-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.115  
0.014  
0.045  
0.008  
0.980  
0.005  
0.300  
0.240  
0.39  
2.93  
0.356  
1.55  
0.204  
24.89  
0.13  
7.62  
6.10  
4
D
E
BASE  
PLANE  
0.195  
0.022  
0.070  
0.014  
1.060  
-
4.95  
0.558  
1.77  
0.355  
-
A2  
A
-
SEATING  
PLANE  
B1  
C
8
L
C
L
D1  
B1  
-
eA  
A1  
A
D1  
e
D
26.9  
5
C
eC  
B S  
B
D1  
E
-
5
eB  
0.010 (0.25) M  
C
0.325  
0.280  
8.25  
7.11  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between  
English and Metric dimensions, the inch dimensions control.  
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
-
0.430  
0.150  
-
10.92  
3.81  
7
3. Symbols are defined in the “MO Series Symbol List” in Section  
2.2 of Publication No. 95.  
L
0.115  
2.93  
4
9
N
20  
20  
4. Dimensions A, A1 and L are measured with the package seated  
in JEDEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or protru-  
sions. Mold flash or protrusions shall not exceed 0.010 inch  
(0.25mm).  
e
6. E and  
pendicular to datum  
7. e and e are measured at the lead tips with the leads uncon-  
are measured with the leads constrained to be per-  
A
-C-  
.
B
C
strained. e must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions.  
Dambar protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,  
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch  
(0.76 - 1.14mm).  
11  
HIP5500  
Small Outline Plastic Packages (SOIC)  
M20.3 (JEDEC MS-013-AC ISSUE C)  
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE  
N
INDEX  
AREA  
M
M
B
0.25(0.010)  
H
INCHES MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
2.35  
0.10  
0.33  
0.23  
12.60  
7.40  
MAX  
2.65  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0926  
0.0040  
0.013  
0.1043  
0.0118  
0.0200  
0.0125  
0.5118  
0.2992  
-
0.30  
-
1
2
3
L
0.51  
9
SEATING PLANE  
A
0.0091  
0.4961  
0.2914  
0.32  
-
-A-  
o
13.00  
7.60  
3
D
h x 45  
4
-C-  
0.050 BSC  
1.27 BSC  
-
α
µ
H
h
0.394  
0.010  
0.016  
0.419  
0.029  
0.050  
10.00  
0.25  
0.40  
10.65  
0.75  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
6
M
M
S
B
0.25(0.010)  
C
A
N
α
20  
20  
7
o
0
o
8
o
0
o
8
-
NOTES:  
Rev. 0 12/93  
1. Symbols are defined in the “MO Series Symbol List” in Section  
2.2 of Publication Number 95.  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusion and gate burrs shall not exceed  
0.15mm (0.006 inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. In-  
terlead flash and protrusions shall not exceed 0.25mm (0.010  
inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual  
index feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater  
above the seating plane, shall not exceed a maximum value of  
0.61mm (0.024 inch)  
10. Controlling dimension: MILLIMETER. Converted inch dimen-  
sions are not necessarily exact.  
12  

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