HI5662/6IN_技术文档

HI5662

Data Sheet

February 1999

File Number 4317.2

Dual 8-Bit, 60MSPS A/D Converter with

Internal Voltage Reference

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS

The HI5662 is a monolithic, dual 8-Bit, 60MSPS analog-to-

digital converter fabricated in an advanced CMOS process.

It is designed for high speed applications where integration,

bandwidth and accuracy are essential. The HI5662 reaches

a new level of multi-channel integration. The fully pipeline

architecture and an innovative input stage enable the HI5662

to accept a variety of input conﬁgurations, single-ended or

fully differential. Only one external clock is necessary to

drive both converters and an internal band-gap voltage

reference is provided. This allows the system designer to

realize an increased level of system integration resulting in

decreased cost and power dissipation.

• 7.8 Bits at f = 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB

• On-Chip Sample and Hold Ampliﬁers

• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V

• Fully Differential or Single-Ended Analog Inputs

• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

The HI5662 has excellent dynamic performance while

consuming only 650mW power at 60MSPS. The A/D only

requires a single +5V power supply and encode clock. Data

output latches are provided which present valid data to the

output bus with a latency of 6 clock cycles.

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary Digital Data Output Format

• Dual 8-Bit A/D Converters on a Monolithic Chip

Applications

• Wireless Local Loop

For those customers needing dual channel 10-bit resolution,

please refer to the HI5762. For single channel 10-bit

applications, please refer to the HI5767.

• PSK and QAM I and Q Demodulators

• Medical Imaging

Ordering Information

• High Speed Data Acquisition

PART

NUMBER

TEMP.

o

RANGE ( C)

-40 to 85

25

PACKAGE

44 Ld MQFP

PKG. NO.

Pinout

HI5662/6IN

Q44.10x10

HI5662

(MQFP)

TOP VIEW

HI5662EVAL2

Evaluation Platform

44 43 42 41 40 39 38 37 36 35 34

A

1

A

33

32

31

30

29

GND

AV

2

AV

CC2

ID7

CC2

3

4

5

6

7

8

9

QD7

QD6

QD5

QD4

QD3

ID6

ID5

ID4

ID3

28

27

26

25

24

23

DV

CC3

D

GND

ID2

10

11

QD2

QD1

ID1

12 13 14 15 16 17 18 19 20 21 22

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

10

HI5662

Functional Block Diagram

I/Q

-

IN

BIAS

I/QV

DC

I/Q

+

IN

S/H

STAGE 1

2-BIT

FLASH

2-BIT

DAC

+

∑

-

DV

CC3

X2

I/QD7 (MSB)

I/QD6

DIGITAL DELAY

AND

STAGE M-1

I/QD5

DIGITAL ERROR

CORRECTION

I/QD4

I/QD3

2-BIT

FLASH

2-BIT

DAC

I/QD2

I/QD1

+

I/QD0 (LSB)

∑

-

X2

STAGE M

2-BIT

FLASH

I or Q CHANNEL

V

REFOUT

CLK

CLOCK

REFERENCE

V

REFIN

AV

AGND

DV

CC1,2

DGND

CC1,2

11

HI5662

Typical Application Schematic

HI5662

(LSB) ID0 (12)

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

I

+

-

(42) I

IN

+

IN

ID1 (11)

ID2 (10)

(44) IV

DC

-

I

(43) I

IN

ID3 (7)

ID4 (6)

ID5 (5)

ID6 (4)

(MSB) ID7 (3)

(LSB) QD0 (22)

QD1 (23)

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

Q

+

-

(36) Q

IN

+

IN

(34) QV

DC

-

QD2 (24)

Q

(35) Q

IN

QD3 (27)

QD4 (28)

QD5 (29)

QD6 (30)

(MSB) QD7 (31)

(40) V

(38) V

RIN

ROUT

0.1µF

CLK (17)

CLOCK

DV

(8,26)

CC3

+5V or +3V

+

0.1µF

10µF

(13,14,20,21,39) NC

(37) AV

CC1

DV

(18)

(16)

CC2

DV

(2,32) AV

+5V

CC1

+5V

CC2

+

10µF

+

10µF

0.1µF

(1,33,41) AGND

DGND (9,15,19,25)

DGND

10µF AND 0.1µF CAPS

ARE PLACED AS CLOSE

TO PART AS POSSIBLE

AGND

BNC

12

HI5662

Pin Descriptions

PIN NO.

NAME

DESCRIPTION

Analog Ground

PIN NO.

24

NAME

DESCRIPTION

Q-Channel, Data Bit 2 Output

Digital Ground

1

2

3

4

5

6

7

8

A

QD2

GND

AV

Analog Supply (+5.0V)

25

D

CC2

ID7

GND

I-Channel, Data Bit 7 Output (MSB)

I-Channel, Data Bit 6 Output

I-Channel, Data Bit 5 Output

I-Channel Data Bit 4 Output

I-Channel, Data Bit 3 Output

26

DV

Digital Output Supply

(+3.0V or +5.0V)

CC3

ID6

ID5

ID4

ID3

27

28

29

30

31

QD3

Q-Channel, Data Bit 3 Output

Q-Channel, Data Bit 4 Output

Q-Channel, Data Bit 5 Output

Q-Channel, Data Bit 6 Output

QD4

QD5

QD6

QD7

DV

Digital Output Supply

(+3.0V or +5.0V)

CC3

Q-Channel, Data Bit 7 Output

(MSB)

9

D

Digital Ground

GND

32

33

34

35

36

37

38

39

40

41

42

43

44

AV

Analog Supply (+5.0V)

CC2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

ID2

ID1

ID0

NC

I-Channel, Data Bit 2 Output

I-Channel, Data Bit 1 Output

I-Channel, Data Bit 0 Output (LSB)

No Connect

A

Analog Ground

GND

QV

Q-Channel DC Bias Voltage Output

Q-Channel Negative Analog Input

Q-Channel Positive Analog Input

Analog Supply (+5.0V)

DC

IN-

Q

IN+

No Connect

AV

CC1

D

Digital Ground

GND

V

+2.5V Reference Voltage Output

No Connect

ROUT

NC

DV

Digital Supply (+5.0V)

Sample Clock Input

Digital Supply (+5.0V)

Digital Ground

CC1

CLK

V

+2.5V Reference Voltage Input

Analog Ground

RIN

DV

CC2

A

GND

D

GND

I

I-Channel Positive Analog Input

I-Channel Negative Analog Input

I-Channel DC Bias Voltage Output

IN+

NC

No Connect

I

IN-

No Connect

IV

DC

QD0

QD1

Q-Channel, Data Bit 0 Output (LSB)

Q-Channel, Data Bit 1 Output

13

HI5662

o

Absolute Maximum Ratings T = 25 C

Thermal Information

A

o

Supply Voltage, AV

CC

or DV

to AGND or DGND . . . . . . . . . . .6V

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

HI5662/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

o

Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C

o

CC

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

(Lead Tips Only)

Operating Conditions

Temperature Range

o

HI5662/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations AV

= DV

CC1,2

= +5.0V, DV

CC3

= +3.0V; V = 2.50V; f = 60MSPS at 50% Duty Cycle;

RIN S

CC1,2

C = 10pF; T = 25 C; Differential Analog Input; Unless Otherwise Speciﬁed

o

L

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Resolution

8

-

Bits

LSB

Integral Linearity Error, INL

f

= 10MHz

0.5

±0.2

IN

Differential Linearity Error, DNL

(Guaranteed No Missing Codes)

= 10MHz

-

±1.0

IN

Offset Error, V

OS

f

= DC

-10

-

+10

-

LSB

IN

Full Scale Error, FSE

1

IN

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate

Maximum Conversion Rate

Effective Number of Bits, ENOB

No Missing Codes

-

1

-

MSPS

60

f

= 10MHz

7.5

7.0

7.8

7.7

-

Bits

IN

= 10MHz, Single Ended Analog Input

Signal to Noise and Distortion Ratio, SINAD

f

= 10MHz

-

48.7

-

dB

IN

RMS Signal

= -------------------------------------------------------------

RMS Noise + Distortion

Signal to Noise Ratio, SNR

f

= 10MHz

-

48

-

dB

IN

RMS Signal

= -------------------------------

RMS Noise

Total Harmonic Distortion, THD

2nd Harmonic Distortion

f

= 10MHz

-

-66

-71

71

64

-75

2.5

1

-

dBc

IN

-

3rd Harmonic Distortion

-

dBc

Spurious Free Dynamic Range, SFDR

Intermodulation Distortion, IMD

I/Q Channel Crosstalk

-

dBc

= 1MHz, f = 1.02MHz

-

dBc

1

2

-60

dBc

I/Q Channel Offset Match

I/Q Channel Full Scale Error Match

Transient Response

-

LSB

Cycle

(Note 2)

Over-Voltage Recovery

0.2V Overdrive (Note 2)

1

14

HI5662

Electrical Speciﬁcations AV

= DV

CC1,2

= +5.0V, DV

CC3

= +3.0V; V = 2.50V; f = 60MSPS at 50% Duty Cycle;

RIN S

CC1,2

C = 10pF; T = 25 C; Differential Analog Input; Unless Otherwise Speciﬁed (Continued)

o

L

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

Range (V + - V -)

IN IN

-

±0.5

-

V

Maximum Peak-to-Peak Single-Ended

Analog Input Range

1.0

Analog Input Resistance, R

or R

V

, V = VREF,DC

IN+ IN-

-

1

10

-

MΩ

pF

IN+

IN-

Analog Input Capacitance, C

or C

, V = 2.5V,DC

IN+ IN-

IN+

IN-

Analog Input Bias Current, I + or I -

, V = V

IN+ IN-

, V

, DC

-10

10

µA

B

REF- REF+

(Notes 2, 3)

Differential Analog Input Bias Current

= (I + - I -)

(Notes 2, 3)

-0.5

-

+0.5

µA

I

BDIFF

B

Full Power Input Bandwidth, FPBW

(Note 2)

-

250

-

MHz

V

Analog Input Common Mode Voltage Range

Differential Mode (Note 2)

0.25

4.75

(V + + V -) / 2

IN IN

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage, V

(Loaded)

2.35

2.5

2

2.65

V

ROUT

Reference Output Current, I

-

4

-

mA

ROUT

o

Reference Temperature Coefficient

-400

ppm/ C

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

-

2.5

1.25

2

-

V

RIN

Total Reference Resistance, R

with V

= 2.5V

kΩ

mA

RIN

Reference Current, I

RIN

DC BIAS VOLTAGE

DC Bias Voltage Output, V

Maximum Output Current

-

3.0

-

V

DC

0.4

mA

SAMPLING CLOCK INPUT

Input Logic High Voltage, V

CLK

2.0

-

V

IH

Input Logic Low Voltage, V

0.8

V

IL

Input Logic High Current, I

CLK, V = 5V

IH

-10.0

-

+10.0

-

µA

pF

IH

Input Logic Low Current, I

CLK, V = 0V

IL

-

IL

Input Capacitance, C

CLK

7

IN

DIGITAL OUTPUTS

Output Logic High Voltage, V

OH

I

= 100µA; DV

= 5V

= 3V

4.0

-

0.8

-

V

OH

OL

OH

OL

CC3

Output Logic Low Voltage, V

OL

= 100µA; DV

-

2.4

-

CC3

Output Logic High Voltage, V

-

V

OH

OL

CC3

Output Logic Low Voltage, V

Output Capacitance, C

= 100µA; DV

-

0.5

-

V

-

7

pF

OUT

TIMING CHARACTERISTICS

Aperture Delay, t

-

5

-

ns

AP

Aperture Jitter, t

AJ

ps

RMS

Data Output Hold, t

10.7

ns

H

15

HI5662

Electrical Speciﬁcations AV

= DV

CC1,2

= +5.0V, DV

CC3

= +3.0V; V = 2.50V; f = 60MSPS at 50% Duty Cycle;

RIN S

CC1,2

C = 10pF; T = 25 C; Differential Analog Input; Unless Otherwise Speciﬁed (Continued)

o

L

A

PARAMETER

Data Output Delay, t

TEST CONDITIONS

MIN

-

TYP

11.7

6

MAX

UNITS

ns

-

6

OD

Data Latency, t

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

(Note 2)

6

Cycles

ns

LAT

Power-Up Initialization

-

20

-

Sample Clock Pulse Width (Low)

Sample Clock Pulse Width (High)

Sample Clock Duty Cycle Variation

7.5

8.3

±5

(Note 2)

-

ns

%

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV

(Note 2)

4.75

5.0

5.25

3.3

5.25

-

V

CC

Digital Supply Voltage, DV

and DV

(Note 2)

4.75

CC1

CC2

Digital Output Supply Voltage, DV

At 3.0V (Note 2)

At 5.0V (Note 2)

2.7

3.0

V

CC3

4.75

5.0

V

Supply Current, I

CC

f

= 60MSPS

-

130

mA

mW

LSB

S

Power Dissipation

650

670

-

Offset Error Sensitivity, ∆V

AV

or DV

= 5V ±5%

±0.125

±0.15

OS

CC

Gain Error Sensitivity, ∆FSE

-

CC

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

16

HI5662

Timing Waveforms

ANALOG

INPUT

CLOCK

INPUT

S

H

S

H

S

H

S

H

S

H

S

H

S

H

N + 8

N - 1

N

N + 1

N + 2

N + 5

N + 6

N + 7

N + 8

INPUT

S/H

1ST

STAGE

B ,

1 N + 7

1

N - 1

1

N

1

N + 1

1

N + 4

1

N + 5

1

N + 6

2ND

STAGE

B ,

2 N + 6

B ,

2 N

2

N + 4

2

N + 5

2

N - 2

2

N - 1

M-th

STAGE

B ,

9 N + 3

9

N - 5

9

N - 4

9

N

9

N + 1

9

N + 2

DATA

OUTPUT

D

N + 2

N - 6

N - 5

N - 1

N

N + 1

t

LAT

NOTES:

4. S : N-th sampling period.

N

5. H : N-th holding period.

N

6. B

, : M-th stage digital output corresponding to N-th sampled input.

M N

7. D : Final data output corresponding to N-th sampled input.

N

FIGURE 1. HI5662 INTERNAL CIRCUIT TIMING

ANALOG

INPUT

t

AP

t

AJ

CLOCK

INPUT

1.5V

t

OD

t

H

2.4V

0.5V

DATA

OUTPUT

DATA N

DATA N-1

FIGURE 2. HI5662 INPUT-TO-OUTPUT TIMING

17

HI5662

Typical Performance Curves

50

44

38

32

8

50

44

38

32

7

6

f

T

= 60MSPS

= 25 C

S

f

T

= 60MSPS

= 25 C

S

o

A

5

1

10

100

1

10

100

INPUT FREQUENCY (MHz)

FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND

SINAD vs INPUT FREQUENCY

FIGURE 4. SNR vs INPUT FREQUENCY

70

90

85

60

50

40

30

20

10

-2HD

80

75

-THD (dBc)

-3HD

70

65

-THD

SNR (dB) OR SINAD (dB)

60

55

50

f

T

= 60MSPS

= 25 C

S

o

A

1

10

100

-40

-30

-20

-10

0

INPUT FREQUENCY (MHz)

INPUT LEVEL (dBFS)

FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY

8

FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE

150

1MHz < f < 15MHz

IN

140

130

120

110

100

90

o

T

= 25 C

A

I

CC

7

6

AI

80

CC

70

60

50

DI

CC1

40

f

= 60MSPS

S

30

1MHz < f < 15MHz

IN

= 25 C

20

DI

o

CC2

T

DI

A

CC3

10

5

0

40

42

44

46

48

50

52

54

)

56

58

60

10

20

30

40

50

60

70

DUTY CYCLE (%, t /t

f

(MSPS)

HI CLK

S

FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs

SAMPLE CLOCK DUTY CYCLE

FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK

FREQUENCY

18

HI5662

Typical Performance Curves (Continued)

3.10

3.05

3.00

2.95

2.90

2.85

2.50

2.49

2.48

2.47

2.46

2.45

2.44

2.43

2.42

2.41

2.40

IV

DC

QV

DC

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

o

TEMPERATURE ( C)

FIGURE 9. INTERNAL REFERENCE VOLTAGE (V

TEMPERATURE

) vs

FIGURE 10. DC BIAS VOLTAGE (I/QVDC) vs TEMPERATURE

ROUT

13.0

12.5

140

I

CC

120

100

80

60

40

20

0

f

= 60MSPS

S

1MHz < f < 15MHz

IN

t

OD

AI

12.0

11.5

11.0

CC

DI

CC1

CC2

DI

CC3

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

o

TEMPERATURE ( C)

FIGURE 11. DATA OUTPUT DELAY (t ) vs TEMPERATURE

OD

FIGURE 12. SUPPLY CURRENT vs TEMPERATURE

0

f

= 60MSPS

= 10MHz

S

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

IN

o

T

= 25 C

A

0

100 200 300 400 500 600 700 800 900 1023

FREQUENCY (BIN)

FIGURE 13. 2048 POINT FFT PLOT

19

HI5662

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

DIFFERENTIAL INPUT

VOLTAGE

(I/Q + - I/Q -)

MSB

LSB

CODE CENTER

DESCRIPTION

I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

IN IN

7

+Full Scale (+FS) - / LSB

16

0.498291V

0.494385V

2.19727mV

-1.70898mV

-0.493896V

-0.497803V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

7

+FS - 1 / LSB

16

9

+ / LSB

16

7

- / LSB

16

9

-FS + 1 / LSB

16

9

-Full Scale (-FS) +

NOTE:

/

LSB

16

8. The voltages listed above represent the ideal center of each output code shown with V

= +2.5V.

REFIN

As illustrated in the functional block diagram and the timing

diagram in Figure 1, identical pipeline subconverter stages,

each containing a two-bit ﬂash converter and a two-bit

multiplying digital-to-analog converter, follow the S/H circuit

with the last stage being a two bit ﬂash converter. Each

converter stage in the pipeline will be sampling in one phase

and amplifying in the other clock phase. Each individual

subconverter clock signal is offset by 180 degrees from the

previous stage clock signal resulting in alternate stages in

the pipeline performing the same operation.

Detailed Description

Theory of Operation

The HI5662 is a dual 8-bit fully differential sampling pipeline

A/D converter with digital error correction logic. Figure 14

depicts the circuit for the front end differential-in-differential-

out sample-and-hold (S/H) ampliﬁers. The switches are

controlled by an internal sampling clock which is a non-

overlapping two phase signal, φ and φ , derived from the

1

2

master sampling clock. During the sampling phase, φ , the

1

input signal is applied to the sampling capacitors, C . At the

S

The output of each of the identical two-bit subconverter

stages is a two-bit digital word containing a supplementary

bit to be used by the digital error correction logic. The output

of each subconverter stage is input to a digital delay line

which is controlled by the internal sampling clock. The

function of the digital delay line is to time align the digital

outputs of the identical two-bit subconverter stages with the

corresponding output of the last stage ﬂash converter before

applying the results to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the ﬁnal

eight bit digital data output of the converter.

same time the holding capacitors, C , are discharged to

H

analog ground. At the falling edge of φ the input signal is

1

sampled on the bottom plates of the sampling capacitors. In

the next clock phase, φ , the two bottom plates of the

2

sampling capacitors are connected together and the holding

capacitors are switched to the op-amp output nodes. The

charge then redistributes between C and C completing

S

H

one sample-and-hold cycle. The front end sample-and-hold

output is a fully-differential, sampled-data representation of

the analog input. The circuit not only performs the sample-

and-hold function but will also convert a single-ended input

to a fully-differential output for the converter core. During the

sampling phase, the I/Q pins see only the on-resistance of

a switch and C . The relatively small values of these

S

components result in a typical full power input bandwidth of

250MHz for the converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus following the 6th cycle of the clock after the

analog sample is taken (see the timing diagram in Figure 1).

This time delay is speciﬁed as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The digital output data is provided in offset

binary format (see Table 1, A/D Code Table).

IN

Φ

C

1

H

Φ

1

C

S

I/Q

IN+

V

OUT+

+

-

Φ

2

V

+

-

OUT-

Internal Reference Voltage Output, V

REFOUT

IN-

S

Φ

1

The HI5662 is equipped with an internal reference voltage

generator, therefore, no external reference voltage is

Φ

C

Φ

1

H

1

required. V

must be connected to V

when using the

RIN

ROUT

internal reference voltage.

FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD

20

HI5662

An internal band-gap reference voltage followed by an

ampliﬁer/buffer generates the precision +2.5V reference

voltage used by the converter. A band-gap reference circuit

is used to generate a precision +1.25V internal reference

voltage. This voltage is then ampliﬁed by a wide-band

uncompensated operational ampliﬁer connected in a

gain-of-two conﬁguration. An external, user-supplied, 0.1µF

an AC coupled differential input. This low output impedance

voltage source is not designed to be a reference but makes an

excellent DC bias source and stays well within the analog

input common mode voltage range over temperature.

For the AC coupled differential input (Figure 15) and with

V

connected to V

, full scale is achieved when the

, with -V being

RIN

ROUT

and -V input signals are 0.5V

IN

P-P

IN

capacitor connected from the V

output pin to analog

ROUT

180 degrees out of phase with V . The converter will be at

IN

ground is used to set the dominant pole and to maintain the

stability of the operational ampliﬁer.

positive full scale when the I/Q + input is at V

IN DC

+ 0.25V and

the I/Q input is at V

- 0.25V (I/Q

- I/Q = +0.5V).

IN- DC

IN+ IN-

Conversely, the converter will be at negative full scale when

the I/Q input is equal to V - 0.25V and I/Q is at

Reference Voltage Input, V

REFIN

The HI5662 is designed to accept a +2.5V reference voltage

source at the V input pin. Typical operation of the

IN+

+ 0.25V (I/Q

DC

IN-

V

- I/Q = -0.5V).

IN+ IN-

DC

RIN

converter requires V

to be set at +2.5V. The HI5662 is

yielding a fully

RIN

connected to V

The analog input can be DC coupled (Figure 16) as long as

the inputs are within the analog input common mode voltage

range (0.25V ≤ VDC ≤ 4.75V).

tested with V

RIN

ROUT

differential analog input voltage range of ±0.5V.

The user does have the option of supplying an external

+2.5V reference voltage. As a result of the high input

V

IN

I/Q

+

IN

VDC

impedance presented at the V

input pin, 1.25kΩ typically,

RIN

R

HI5662

the external reference voltage being used is only required to

source 2mA of reference input current. In the situation where

an external reference voltage will be used an external 0.1µF

C

I/QV

I/Q

DC

-V

IN

capacitor must be connected from the V

output pin to

ROUT

VDC

-

analog ground in order to maintain the stability of the internal

operational ampliﬁer.

IN

FIGURE 16. DC COUPLED DIFFERENTIAL INPUT

In order to minimize overall converter noise it is

The resistors, R, in Figure 16 are not absolutely necessary

but may be used as load setting resistors. A capacitor, C,

recommended that adequate high frequency decoupling be

provided at the reference voltage input pin, V

.

RIN

connected from I/Q + to I/Q - will help ﬁlter any high

IN IN

Analog Input, Differential Connection

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

The analog input of the HI5662 is a differential input that can

be conﬁgured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 15 and Figure 16) will deliver

the best performance from the converter.

Analog Input, Single-Ended Connection

The conﬁguration shown in Figure 17 may be used with a

single ended AC coupled input.

I/Q

+

V

IN

R

HI5662

I/QV

I/Q

+

V

IN

DC

R

HI5662

VDC

-V

IN

I/Q

-

IN

I/Q

-

IN

FIGURE 15. AC COUPLED DIFFERENTIAL INPUT

FIGURE 17. AC COUPLED SINGLE ENDED INPUT

Since the HI5662 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change signiﬁcantly

with the value of the analog input common mode voltage.

Again, with V

RIN

connected to V

, if V is a 1V

IN P-P

ROUT

sinewave, then I/Q

is a 1.0V sinewave riding on a

IN+

P-P

positive voltage equal to V . The converter will be at positive

DC

full scale when I/Q

is at V

+ 0.5V (I/Q

- I/Q = +0.5V)

IN+

DC

IN+

IN-

and will be at negative full scale when I/Q

IN+

is equal to

V

- 0.5V (I/Q

- I/Q = -0.5V). Sufficient headroom must

IN-

DC

be provided such that the input voltage never goes above +5V

IN+

A DC voltage source, I/QV , equal to 3.0V (typical), is made

DC

available to the user to help simplify circuit design when using

21

HI5662

or below AGND. In this case, VDC could range between 0.5V

and 4.5V without a significant change in ADC performance.

The simplest way to produce VDC is to use the DC bias source,

regulated supplies. The board should also have good high

frequency decoupling capacitors mounted as close as

possible to the converter. If the part is powered off a single

supply then the analog supply can be isolated by a ferrite

bead from the digital supply.

I/QV , of the HI5662.

DC

The single ended analog input can be DC coupled

(Figure 18) as long as the input is within the analog input

common mode voltage range.

Refer to the application note “Using Intersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed converters.

V

IN

I/Q

+

V

IN

DC

Static Performance Deﬁnitions

R

Offset Error (V

)

OS

HI5662

C

1

The midscale code transition should occur at a level / LSB

4

above half-scale. Offset is deﬁned as the deviation of the

actual code transition from this point.

V

I/Q

-

IN

DC

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

3

FIGURE 18. DC COUPLED SINGLE ENDED INPUT

is / LSB below Positive Full Scale (+FS) with the offset

4

The resistor, R, in Figure 18 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

error removed. Full scale error is deﬁned as the deviation of

the actual code transition from this point.

connected from I/Q + to I/Q - will help ﬁlter any high

IN IN

Differential Linearity Error (DNL)

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

DNL is the worst case deviation of a code width from the

ideal value of 1LSB.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

ﬁt straight line calculated from the measured data.

A single ended source may give better overall system

performance if it is ﬁrst converted to differential before

driving the HI5662.

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5% and

the shift in the offset and full scale error (in LSBs) is noted.

Sampling Clock Requirements

The HI5662 sampling clock input provides a standard high-

speed interface to external TTL/CMOS logic families.

Dynamic Performance Deﬁnitions

Fast Fourier Transform (FFT) techniques are used to evaluate

the dynamic performance of the HI5662. A low distortion sine

wave is applied to the input, it is coherently sampled, and the

output is stored in RAM. The data is then transformed into the

frequency domain with an FFT and analyzed to evaluate the

dynamic performance of the A/D. The sine wave input to the

part is typically -0.5dB down from full scale for all these tests.

In order to ensure rated performance of the HI5662, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL/CMOS levels.

Performance of the HI5662 will only be guaranteed at

conversion rates above 1MSPS (Typ). This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is ﬁrst applied to the converter, a maximum of 20

cycles at a sample rate above 1MSPS must to be performed

before valid data is available.

SNR and SINAD are quoted in dB. The distortion numbers are

quoted in dBc (decibels with respect to carrier) and DO NOT

include any correction factors for normalizing to full scale.

Supply and Ground Considerations

The Effective Number of Bits (ENOB) is calculated from the

SINAD data by:

The HI5662 has separate analog and digital supply and ground

pins to keep digital noise out of the analog signal path. The

digital data outputs also have a separate supply pin, DV

,

ENOB = (SINAD - 1.76 + V

) / 6.02,

CORR

CC3

which can be powered from a 3.0V or 5.0V supply. This allows

the outputs to interface with 3.0V logic if so desired.

where: V

= 0.5 dB (Typical).

adjusts the SINAD, and hence the ENOB, for the

CORR

V

CORR

amount the analog input signal is backed off from full scale.

The part should be mounted on a board that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the HI5662 should be driven by clean, linear

22

HI5662

Signal To Noise and Distortion Ratio (SINAD)

I/Q Channel Crosstalk

SINAD is the ratio of the measured RMS signal to RMS sum

of all the other spectral components below the Nyquist

frequency, f /2, excluding DC.

S

I/Q Channel Crosstalk is a measure of the amount of

channel separation or isolation between the two A/D

converter cores contained within the dual converter

package. The measurement consists of stimulating one

channel of the converter with a fullscale input signal and

then measuring the amount that signal is below, in dBc, a

fullscale signal on the opposite channel.

Signal To Noise Ratio (SNR)

SNR is the ratio of the measured RMS signal to RMS noise at

a speciﬁed input and sampling frequency. The noise is the

RMS sum of all of the spectral components below f /2

S

excluding the fundamental, the ﬁrst ﬁve harmonics and DC.

Timing Deﬁnitions

Refer to Figure 1 and Figure 2 for these deﬁnitions.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input signal.

Aperture Delay (t

)

AP

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable harmonic

component to the RMS value of the fundamental input signal.

Aperture Jitter (t

)

AJ

Spurious Free Dynamic Range (SFDR)

Aperture jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spectral component in the

spectrum below f /2.

S

Data Hold Time (t )

H

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate

intermodulation products when two tones, f and f , are

present at the inputs. The ratio of the measured signal to the

distortion terms is calculated. The terms included in the

1

2

Data Output Delay Time (t

)

OD

Data output delay time is the time to where the new data (N)

is valid.

calculation are (f +f ), (f -f ), (2f ), (2f ), (2f +f ), (2f -f ),

1

2

1 2 1 2

1

2

1 2

Data Latency (t )

LAT

After the analog sample is taken, the digital data

(f +2f ), (f -2f ). The ADC is tested with each tone 6dB

below full scale.

1

2

1

2

representing an analog input sample is output to the digital

data bus following the 6th cycle of the clock after the analog

sample is taken. This is due to the pipeline nature of the

converter where the analog sample has to ripple through the

internal subconverter stages. This delay is speciﬁed as the

data latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital data lags the

analog input sample by 6 sample clock cycles.

Transient Response

Transient response is measured by providing a full-scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

10-bit accuracy.

Over-Voltage Recovery

Over-Voltage Recovery is measured by providing a full-scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 10-bit accuracy.

Power-Up Initialization

This time is deﬁned as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the

speciﬁed sampling frequency.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

23


型号：	HI5662/6IN
厂家：	Intersil
描述：	Dual 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference 双8位，60Msps A / D转换器，内置电压基准转换器
文件：	总14页 (文件大小：133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI5662/6IN [INTERSIL]

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