HI5667/6CB_技术文档

HI5667

®

Data Sheet

March 2003

FN4584.2

8-Bit, 60MSPS A/D Converter with Internal

Voltage Reference

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60MSPS

• 7.7Bits at f = 10MHz, f = 60MSPS

The HI5667 is a monolithic, 8-bit, analog-to-digital converter

fabricated in a CMOS process. It is designed for high speed

applications where wide bandwidth and low power

consumption are essential. Its high sample clock rate is

made possible by a fully differential pipelined architecture

with both an internal sample and hold and internal band-gap

voltage reference.

IN

S

• Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 350mW

• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz

• On-Chip Sample and Hold

• Internal 2.5V Band-Gap Voltage Reference

The 250MHz Full Power Input Bandwidth and superior high

frequency performance of the HI5667 converter make it an

excellent choice for implementing Digital IF architectures in

communications applications.

• Fully Differential or Single-Ended Analog Input

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

• CMOS Compatible Digital Outputs. . . . . . . . . . 3.0V/5.0V

• Offset Binary or Two’s Complement Output Format

The HI5667 has excellent dynamic performance while

consuming only 350mW power at 60MSPS. Data output

latches are provided which present valid data to the output

bus with a latency of 7 clock cycles.

Applications

.

• Digital Communication Systems

• QAM Demodulators

Part Number Information

TEMP.

SAMPLING

RATE

(MSPS)

• Professional Video Digitizing

• Medical Imaging

PART

NUMBER

RANGE

PKG.

NO.

o

( C)

PACKAGE

• High Speed Data Acquisition

HI5667/6CB

HI5667/6CA

HI5667EVAL2

0 to 70 28 Ld SOIC

0 to 70 28 Ld SSOP

M28.3

60

M28.15

Pinout

25

Evaluation Board

HI5667 (SOIC, SSOP)

TOP VIEW

DV

1

2

28 NC

CC1

27

26

25

24

23

22

21

20

19

18

17

16

NC

D0

D1

DGND

DV

3

CC1

4

DGND

AV

CC

5

D2

DV

6

AGND

CC2

CLK

DGND

D3

7

V

REFIN

8

V

REFOUT

V

+

9

IN

V

-

10

11

12

13

D4

IN

V

D5

DC

AGND

D6

AV

CC

D7

OE 14

15 DFS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

HI5667

Functional Block Diagram

CLK

CLOCK

V

BIAS

DC

V

-

IN

V

REFOUT

V

+

IN

REFERENCE

V

REFIN

S/H

STAGE 1

DFS

OE

2-BIT

FLASH

2-BIT

DAC

+

∑

-

DV

CC2

X2

D7 (MSB)

D6

D5

D4

DIGITAL DELAY

AND

STAGE M-1

D3

DIGITAL ERROR

CORRECTION

D2

D1

2-BIT

FLASH

2-BIT

DAC

D0 (LSB)

+

∑

-

X2

DGND2

STAGE M

2-BIT

FLASH

AV

AGND DV

DGND1

CC

CC1

2

HI5667

Typical Application Schematic

HI5667

(28) NC

(27) NC

NC

V

(7)

REFIN

REFOUT

(8)

0.1µF

(LSB) (26) D0

D0

D1

D2

D3

D4

D5

D6

D7

(25) D1

(24) D2

(20) D3

(19) D4

(18) D5

(17) D6

AGND (12)

AGND (6)

DGND

AGND

BNC

DGND1 (2)

DGND1 (4)

DGND2 (21)

(MSB) (16) D7

10µF AND 0.1µF CAPS

ARE PLACED AS CLOSE

TO PART AS POSSIBLE

V

+

-

(1) DV

CC1

V

+ (9)

(11)

IN

(3) DV

CC1

DC

IN

V

- (10) (23) DV

IN

CC2

+5V

+

0.1µF

10µF

CLOCK

CLK (22)

DFS (15)

OE (14)

(13) AV

CC

(5) AV

+5V

CC

+

0.1µF

10µF

Pin Descriptions

PIN NO.

NAME

DESCRIPTION

PIN NO.

17

NAME

DESCRIPTION

Data Bit 6 Output

1

2

DV

CC1

Digital Supply (+5.0V)

Digital Ground

D6

D5

DGND1

18

Data Bit 5 Output

Data Bit 4 Output

Data Bit 3 Output

Digital Ground

3

DV

CC1

Digital Supply (+5.0V)

Digital Ground

19

D4

4

DGND1

20

D3

5

AV

CC

Analog Supply (+5.0V)

Analog Ground

21

DGND2

CLK

6

AGND

22

Sample Clock Input

7

V

+2.5V Reference Voltage Input

+2.5V Reference Voltage Output

Positive Analog Input

Negative Analog Input

DC Bias Voltage Output

Analog Ground

23

DV

Digital Output Supply

(+3.0V or +5.0V)

REFIN

CC2

8

V

REFOUT

24

25

26

27

28

D2

Data Bit 2 Output

Data Bit 1 Output

Data Bit 0 Output

No Connection

9

V +

IN

D1

D0

NC

10

11

12

13

14

15

16

V

-

IN

DC

V

AGND

AV

CC

Analog Supply (+5.0V)

Digital Output Enable Control Input

Data Format Select Input

Data Bit 7 Output (MSB)

OE

DFS

D7

3

HI5667

o

Absolute Maximum Ratings T = 25 C

Thermal Information

A

o

Supply Voltage, AV

or DV

to AGND or DGND . . . . . . . . . . 6V

CC

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

100

o

Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C

o

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . 300 C

o

Operating Conditions

(SOIC - Lead Tips Only)

Temperature Range

o

HI5667/xCx (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Specifications AV = DV

= 5.0V, DV

= 3.0V; V

= V

; f = 60MSPS at 50% Duty Cycle;

REFOUT S

CC

CC1

CC2

REFIN

o

C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,

L

A

Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Resolution

8

-

Bits

LSB

Integral Linearity Error, INL

f

= 10MHz

±0.3

±1.75

±1.0

IN

Differential Linearity Error, DNL

(Guaranteed No Missing Codes)

= 10MHz

-

IN

Offset Error, V

f

= 10MHz

-10

-

10

-

LSB

OS

IN

Full Scale Error, FSE

1

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate

Maximum Conversion Rate

Effective Number of Bits, ENOB

No Missing Codes

-

60

7.3

-

0.5

1

MSPS

Bits

f

= 10MHz

7.7

48

-

IN

Signal to Noise and Distortion Ratio, SINAD

dB

RMS Signal

= -------------------------------------------------------------

RMS Noise + Distortion

Signal to Noise Ratio, SNR

f

= 10MHz

-

48.2

-

dB

IN

RMS Signal

= -------------------------------

RMS Noise

Total Harmonic Distortion, THD

f

= 10MHz

-

-62

-69

-63

63

1

-

dBc

IN

2nd Harmonic Distortion

3rd Harmonic Distortion

dBc

Spurious Free Dynamic Range, SFDR

Transient Response

dBc

(Note 2)

Cycle

Over-Voltage Recovery

0.2V Overdrive (Note 2)

1

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input Range

-

±0.5

-

V

(V + - V -)

IN IN

Maximum Peak-to-Peak Single-Ended

Analog Input Range

1.0

Analog Input Resistance, R

(Note 3)

-

1

10

-

MΩ

pF

IN

Analog Input Capacitance, C

-

+10

-

IN

Analog Input Bias Current, I + or I -

(Note 3)

-10

-

µA

B

Differential Analog Input Bias Current

= (I + - I -)

±0.5

I

BDIFF

Full Power Input Bandwidth, FPBW

Analog Input Common Mode Voltage Range (V + + V -) / 2 Differential Mode (Note 2)

B

-

250

-

MHz

V

0.25

4.75

IN IN

INTERNAL REFERENCE VOLTAGE

Reference Voltage Output, V

(Loaded)

-

2.5

1

-

V

REFOUT

Reference Output Current, I

2

mA

REFOUT

4

HI5667

Electrical Specifications AV = DV

= 5.0V, DV

= 3.0V; V

= V

; f = 60MSPS at 50% Duty Cycle;

REFOUT S

CC

CC1

CC2

REFIN

o

C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,

L

A

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

MIN

TYP

MAX

UNITS

o

Reference Temperature Coefficient

-

120

-

ppm/ C

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

-

2.5

1

-

V

REFIN

Total Reference Resistance, R

kΩ

mA

REFIN

Reference Input Current, I

DC BIAS VOLTAGE

DC Bias Voltage Output, V

Maximum Output Current

DIGITAL INPUTS

-

3.0

-

V

DC

0.2

mA

Input Logic High Voltage, V

CLK, DFS, OE

CLK, DFS, OE, V = 5V

2.0

-

V

IH

Input Logic Low Voltage, V

0.8

V

IL

Input Logic High Current, I

-10.0

-

+10.0

-

µA

pF

IH

CLK, DFS, OE, V = 0V

Input Logic Low Current, I

-

IL

Input Capacitance, C

7

IN

DIGITAL OUTPUTS

Output Logic High Voltage, V

I

= 100µA; DV

= 5V

4.0

-

0.8

10

-

V

OH

OL

CC2

Output Logic Low Voltage, V

= 100µA; DV

= 0/5V; DV

OL

Output Three-State Leakage Current, I

CC2

V

= 5V

-10

2.4

-

±1

-

µA

V

OZ

O

CC2

Output Logic High Voltage, V

I

= 100µA; DV

= 3V

OH

OL

CC2

Output Logic Low Voltage, V

= 100µA; DV

= 0/5V; DV

-

0.5

10

-

V

OL

CC2

Output Three-State Leakage Current, I

Output Capacitance, C

V

= 3V

CC2

-10

-

±1

10

µA

pF

O

OUT

TIMING CHARACTERISTICS

Aperture Delay, t

-

5

-

ns

AP

Aperture Jitter, t

-

ps

AJ

Data Output Hold, t

RMS

ns

-

5

-

H

Data Output Delay, t

-

6

-

ns

OD

Data Output Enable Time, t

-

5

-

EN

-

5

-

DIS

Data Latency, t

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

-

7

20

-

Cycles

ns

LAT

Power-Up Initialization

-

Sample Clock Pulse Width (Low)

Sample Clock Pulse Width (High)

Sample Clock Duty Cycle Variation

f

= 60MSPS

7.5

-

8.33

±5

S

-

ns

-

%

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV

4.75

5.0

5.25

3.3

5.25

92

63

25

4

V

CC

Digital Supply Voltage, DV

4.75

CC1

Digital Output Supply Voltage, DV

At 3.0V

At 5.0V

2.7

3.0

V

CC2

4.75

5.0

V

Total Supply Current, I

f

= 10MHz and DFS = “0”

-

70

mA

mW

LSB

CC

IN

Analog Supply Current, AI

47

CC

Digital Supply Current, DI

21

CC

Output Supply Current, DI

Power Dissipation

2

CC2

346

±0.175

±0.025

452

-

Offset Error Sensitivity, ∆V

AV

or DV

= 5V ±5%

OS

CC

Gain Error Sensitivity, ∆FSE

-

CC

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

5

HI5667

Timing Waveforms

ANALOG

INPUT

CLOCK

INPUT

S

H

S

H

S

H

S

H

S

H

S

H

S

H

N + 8

N - 1

N

N + 1

N + 2

N + 5

N + 6

N + 7

N + 8

INPUT

S/H

1ST

STAGE

B ,

1

B ,

1 N + 7

1

N - 1

1

N

1

N + 1

1

N + 4

N + 5

1

N + 6

2ND

STAGE

B ,

2 N + 6

B ,

2

B ,

2 N

2

N + 4

2

N + 5

N - 2

2

N - 1

MTH

STAGE

B

,

B

,

B

,

B

,

B

,

B ,

M N + 3

M N - 5

M N - 4

M N

M N + 1

M N + 2

DATA

OUTPUT

D

N + 1

N - 7

N - 6

N - 2

N - 1

N

t

LAT

NOTES:

4. S : N-th sampling period.

N

5. H : N-th holding period.

N

6. B

, : M-th stage digital output corresponding to N-th sampled input.

N

M

7. D : Final data output corresponding to N-th sampled input.

N

FIGURE 1. HI5667 INTERNAL CIRCUIT TIMING

ANALOG

INPUT

t

AP

t

AJ

CLOCK

INPUT

1.5V

t

OD

t

H

2.4V

0.5V

DATA

OUTPUT

DATA N

DATA N-1

FIGURE 2. INPUT-TO OUTPUT TIMING

6

HI5667

outputs of the identical two-bit subconverter stages with the

corresponding output of the last stage flash converter before

applying the results to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final

ten bit digital data output of the converter.

Detailed Description

Theory of Operation

The HI5667 is an 8-Bit fully differential sampling pipeline A/D

converter with digital error correction logic. Figure 3 depicts

the circuit for the front end differential-in-differential-out

sample-and-hold (S/H). The switches are controlled by an

internal sampling clock which is a non-overlapping two

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus on the 7th cycle of the clock after the analog

sample is taken. This time delay is specified as the data

latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital output data is

synchronized to the external sampling clock by a double

buffered latching technique. The digital output data is

available in two’s complement or offset binary format

depending on the state of the Data Format Select (DFS)

control input (see Table 1, A/D Code Table).

phase signal, Φ and Φ , derived from the master sampling

1

2

clock. During the sampling phase, Φ , the input signal is

applied to the sampling capacitors, C . At the same time the

holding capacitors, CH, are discharged to analog ground. At

1

S

the falling edge of Φ the input signal is sampled on the

1

bottom plates of the sampling capacitors. In the next clock

phase, F2, the two bottom plates of the sampling capacitors

are connected together and the holding capacitors are

switched to the op amp output nodes. The charge then

redistributes between C and C completing one sample-

S

H

and-hold cycle. The front end sample-and-hold output is a

fully-differential, sampled-data representation of the analog

input. The circuit not only performs the sample-and-hold

function but will also convert a single-ended input to a fully-

differential output for the converter core. During the sampling

phase, the VIN pins see only the on-resistance of a switch

Internal Reference Voltage Output, V

REFOUT

The HI5667 is equipped with an internal reference voltage

generator, therefore, no external reference voltage is

required. V

REFOUT

must be connected to V when

REFIN

using the internal reference voltage.

and C . The relatively small values of these components

S

An internal band-gap reference voltage followed by an

amplifier/buffer generates the precision +2.5V reference

voltage used by the converter. A 4:1 array of substrate

result in a typical full power input bandwidth of 250MHz for

the converter.

PNPs generates the “delta-V ” and a two-stage op amp

BE

Φ

C

1

H

closes the loop to create an internal +1.25V band-gap

reference voltage. This voltage is then amplified by a wide-

band uncompensated operational amplifier connected in a

gain-of-two configuration. An external, user-supplied,

Φ

1

C

S

V

IN+

V

OUT+

+

-

Φ

2

V

+

-

OUT-

IN-

0.1µF capacitor connected from the V

output pin to

REFOUT

S

Φ

1

analog ground is used to set the dominant pole and to

maintain the stability of the operational amplifier.

Φ

C

Φ

1

H

1

Reference Voltage Input, V

REFIN

The HI5667 is designed to accept a +2.5V reference voltage

source at the V input pin. Typical operation of the

FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD

REFIN

converter requires V

As illustrated in the functional block diagram and the timing

diagram in Figure 1, identical pipeline subconverter stages,

each containing a two-bit flash converter and a two-bit

multiplying digital-to-analog converter, follow the S/H circuit

with the last stage being a two bit flash converter. Each

converter stage in the pipeline will be sampling in one phase

and amplifying in the other clock phase. Each individual

subconverter clock signal is offset by 180 degrees from the

previous stage clock signal resulting in alternate stages in

the pipeline performing the same operation.

to be set at +2.5V. The HI5667 is

yielding a fully

REFIN

connected to V

tested with V

REFIN

REFOUT

differential analog input voltage range of ±0.5V.

The user does have the option of supplying an external

+2.5V reference voltage. As a result of the high input

impedance presented at the VREFIN input pin, 2.5kΩ

typically, the external reference voltage being used is only

required to source 1mA of reference input current. In the

situation where an external reference voltage will be used an

external 0.1mF capacitor must be connected from the

The output of each of the identical two-bit subconverter

stages is a two-bit digital word containing a supplementary

bit to be used by the digital error correction logic. The output

of each subconverter stage is input to a digital delay line

which is controlled by the internal sampling clock. The

function of the digital delay line is to time align the digital

V

output pin to analog ground in order to maintain

REFOUT

the stability of the internal operational amplifier.

In order to minimize overall converter noise it is

recommended that adequate high frequency decoupling be

provided at the reference voltage input pin, V

.

REFIN

7

HI5667

connected from V + to V - will help filter any high

IN IN

Analog Input, Differential Connection

frequency noise on the inputs, also improving performance.

Values around 20pF are sufficient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

The analog input to the HI5667 is a differential input that can

be configured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 4 and Figure 5) will deliver the

best performance from the converter.

Analog Input, Single-Ended Connection

The configuration shown in Figure 6 may be used with a

single ended AC coupled input.

Since the HI5667 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change significantly

with the value of the analog input common mode voltage.

V

+

V

IN

R

HI5667

-

V

DC

V

+

V

IN

V

IN

R

HI5667

FIGURE 6. AC COUPLED SINGLE ENDED INPUT

V

DC

Again, with V

REFIN

connected to V

, if V is a 1V

IN P-P

REFOUT

sinewave, then V + is a 1.0V

sinewave riding on a positive

IN P-P

-V

IN

-

voltage equal to VDC. The converter will be at positive full scale

IN

when V + is at VDC + 0.5V (V + - V - = +0.5V) and will be at

IN IN IN

FIGURE 4. AC COUPLED DIFFERENTIAL INPUT

negative full scale when V + is equal to VDC - 0.5V (V + - V -

IN IN IN

= -0.5V). Sufficient headroom must be provided such that the

input voltage never goes above +5V or below AGND. In this

case, VDC could range between 0.5V and 4.5V without a

significant change in ADC performance. The simplest way to

A DC voltage source, V , equal to 3.2V (typical), is made

DC

available to the user to help simplify circuit design when using

an AC coupled differential input. This low output impedance

voltage source is not designed to be a reference but makes

an excellent DC bias source and stays well within the analog

input common mode voltage range over temperature.

produce VDC is to use the DC bias source, V , output of the

DC

HI5667.

The single ended analog input can be DC coupled (Figure 7)

as long as the input is within the analog input common mode

voltage range.

For the AC coupled differential input (Figure 4) and with

V

connected to V

, full scale is achieved when

, with -V being

REFIN

REFOUT

the V and -V input signals are 0.5V

IN IN P-P

IN

V

IN

180 degrees out of phase with V . The converter will be at

IN

V

IN

+

V

DC

positive full scale when the V + input is at V

IN DC

+ 0.25V and

the V - input is at V

- 0.25V (V + - V - = +0.5V).

R

IN DC

IN IN

Conversely, the converter will be at negative full scale when

the V + input is equal to V - 0.25V and V - is at

HI5667

-

C

IN DC IN

V

+ 0.25V (V + - V - = -0.5V).

IN IN

DC

V

IN

DC

The analog input can be DC coupled (Figure 5) as long as

the inputs are within the analog input common mode voltage

range (0.25V ≤ VDC ≤ 4.75V).

FIGURE 7. DC COUPLED SINGLE ENDED INPUT

V

IN

The resistor, R, in Figure 7 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from V + to V - will help filter any high

frequency noise on the inputs, also improving performance.

Values around 20pF are sufficient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

V

+

IN

V

DC

R

IN

HI5667

C

V

DC

-V

IN

-

DC

IN

FIGURE 5. DC COUPLED DIFFERENTIAL INPUT

A single ended source may give better overall system

performance if it is first converted to differential before

driving the HI5667.

The resistors, R, in Figure 5 are not absolutely necessary

but may be used as load setting resistors. A capacitor, C,

8

HI5667

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

(DFS LOW)

TWO’S COMPLEMENT OUTPUT CODE

(DFS HIGH)

M

S

B

L

S

B

M

S

B

L

S

B

DIFFERENTIAL

INPUT

VOLTAGE

CODE CENTER

DESCRIPTION

7

(V + - V -)

IN IN

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

+Full Scale (+FS) - / LSB

16

0.498291V

0.494385V

2.19727mV

-1.70898V

-0.493896V

-0.497803V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

7

+FS - 1 / LSB

16

9

+ / LSB

16

7

- / LSB

16

9

-FS + 1 / LSB

16

9

-Full Scale (-FS) + / LSB

16

NOTE:

8. The voltages listed above represent the ideal center of each output code shown with V

= +2.5V.

REFIN

frequency decoupling capacitors mounted as close as

Digital Output Control and Clock Requirements

The HI5667 provides a standard high-speed interface to

external TTL logic families.

possible to the converter. If the part is powered off a single

supply then the analog supply should be isolated with a

ferrite bead from the digital supply.

In order to ensure rated performance of the HI5667, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL levels.

Refer to the application note “Using Intersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed converters.

Performance of the HI5667 will only be guaranteed at

conversion rates above 1MSPS. This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is first applied to the converter, a maximum of 20

cycles at a sample rate above 1MSPS will have to be

performed before valid data is available.

Static Performance Definitions

Offset Error (V

)

OS

1

The midscale code transition should occur at a level / LSB

above half-scale. Offset is defined as the deviation of the

actual code transition from this point.

4

A Data Format Select (DFS) pin is provided which will

determine the format of the digital data outputs. When at

logic low, the data will be output in offset binary format.

When at logic high, the data will be output in two’s

complement format. Refer to Table 1 for further information.

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

3

is / LSB below Positive Full Scale (+FS) with the offset

4

error removed. Full scale error is defined as the deviation of

the actual code transition from this point.

The output enable pin, OE, when pulled high will three-state

the digital outputs to a high impedance state. Set the OE

input to logic low for normal operation.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the

ideal value of 1 LSB.

OE INPUT

DIGITAL DATA OUTPUTS

Active

0

1

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

fit straight line calculated from the measured data.

High Impedance

Supply and Ground Considerations

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5% and

the shift in the offset and full scale error (in LSBs) is noted.

The HI5667 has separate analog and digital supply and ground

pins to keep digital noise out of the analog signal path. The

digital data outputs also have a separate supply pin, DV

,

CC2

which can be powered from a 3.0V or 5.0V supply. This allows

the outputs to interface with 3.0V logic if so desired.

Dynamic Performance Definitions

Fast Fourier Transform (FFT) techniques are used to evaluate

the dynamic performance of the HI5667. A low distortion sine

wave is applied to the input, it is coherently sampled, and the

output is stored in RAM. The data is then transformed into the

frequency domain with an FFT and analyzed to evaluate the

The part should be mounted on a board that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the HI5667 should be driven by clean, linear

regulated supplies. The board should also have good high

9

HI5667

dynamic performance of the A/D. The sine wave input to the

part is typically -0.5dB down from full scale for all these tests.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the

specified sampling frequency.

SNR and SINAD are quoted in dB. The distortion numbers are

quoted in dBc (decibels with respect to carrier) and DO NOT

include any correction factors for normalizing to full scale.

The Effective Number of Bits (ENOB) is calculated from the

SINAD data by:

Video Definitions

ENOB = (SINAD - 1.76 + V

) / 6.02,

CORR

Differential Gain and Differential Phase are two commonly

found video specifications for characterizing the distortion of a

chrominance signal as it is offset through the input voltage

range of an ADC.

where:

V

= 0.5 dB (Typical).

CORR

V

adjusts the SINAD, and hence the ENOB, for the

CORR

amount the analog input signal is backed off from full scale.

Signal To Noise and Distortion Ratio (SINAD)

SINAD is the ratio of the measured RMS signal to RMS sum

of all the other spectral components below the Nyquist

Differential Gain (DG)

Differential Gain is the peak difference in chrominance

amplitude (in percent) relative to the reference burst.

frequency, f /2, excluding DC.

S

Differential Phase (DP)

Signal To Noise Ratio (SNR)

SNR is the ratio of the measured RMS signal to RMS noise at

a specified input and sampling frequency. The noise is the

Differential Phase is the peak difference in chrominance

phase (in degrees) relative to the reference burst.

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

RMS sum of all of the spectral components below f /2

excluding the fundamental, the first five harmonics and DC.

S

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input

signal.

Aperture Delay (t

)

AP

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

2nd and 3rd Harmonic Distortion

Aperture Jitter (t

Aperture jitter is the RMS variation in the aperture delay due

)

This is the ratio of the RMS value of the applicable harmonic

component to the RMS value of the fundamental input signal.

AJ

to variation of internal clock path delays.

Spurious Free Dynamic Range (SFDR)

Data Hold Time (t )

H

Data hold time is the time to where the previous data (N - 1)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spectral component in the

is no longer valid.

spectrum below f /2.

S

Data Output Delay Time (t

)

Intermodulation Distortion (IMD)

OD

Data output delay time is the time from the rising edge of the

Nonlinearities in the signal path will tend to generate

external sample clock to where the new data (N) is valid.

intermodulation products when two tones, f and f , are

1

2

present at the inputs. The ratio of the measured signal to

the distortion terms is calculated. The terms included in the

Data Latency (t

After the analog sample is taken, the digital data

)

LAT

calculation are (f +f ), (f -f ), (2f ), (2f ), (2f +f ), (2f -f ),

1 2 1 2

1

2

1

2

1 2

representing an analog input sample is output to the digital

data bus on the 7th cycle of the clock after the analog

sample is taken. This is due to the pipeline nature of the

converter where the analog sample has to ripple through the

internal subconverter stages. This delay is specified as the

data latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital data lags the

analog input sample by 7 sample clock cycles.

(f +2f ), (f -2f ). The ADC is tested with each tone 6dB

below full scale.

1

2

1

2

Transient Response

Transient response is measured by providing a full-scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

8-Bit accuracy.

Over-Voltage Recovery

Power-Up Initialization

Over-Voltage Recovery is measured by providing a full-scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 8-Bit accuracy.

This time is defined as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

10


型号：	HI5667/6CB
厂家：	Intersil
描述：	8-Bit, 60MSPS A/D Converter with Internal Voltage Reference 8位，60Msps A / D转换器，内置电压基准转换器
文件：	总10页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI5667/6CB [INTERSIL]

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