HI4P0201-5 [INTERSIL]
Dual/Quad SPST, CMOS Analog Switches; 双/四路SPST ， CMOS模拟开关
| 型号： | HI4P0201-5 |
| 厂家： | 
Intersil |
| 描述： | Dual/Quad SPST, CMOS Analog Switches |
| 文件： | 总10页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-200, HI-201
Data Sheet
October 1999
File Number 3121.4
Dual/Quad SPST, CMOS Analog Switches
Features
HI-200/HI-201 (dual/quad) are monolithic devices comprising
independently selectable SPST switches which feature fast
switching speeds (HI-200 240ns, and HI-201 185ns)
• Analog Voltage Range . . . . . . . . . . . . . . . . . . . . . . . 15V
• Analog Current Range . . . . . . . . . . . . . . . . . . . . . . . 80mA
• Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240ns
o
combined with low power dissipation (15mW at 25 C). Each
switch provides low “ON” resistance operation for input signal
voltage up to the supply rails and for signal current up to
80mA. Rugged DI construction eliminates latch-up and
substrate SCR failure modes.
• Low r
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Ω
• Low Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .15mW
• TTL/CMOS Compatible
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. HI-200/HI-201 are ideal components for use in
high frequency analog switching. Typical applications include
signal path switching, sample and hold circuit, digital filters,
and operational amplifier gain switching networks.
Applications
• High Frequency Analog Switching
• Sample and Hold Circuits
• Digital Filters
• Operational Amplifier Gain Switching Networks
Ordering Information
Functional Diagram
PART
NUMBER
TEMPERATURE
RANGE ( C)
o
PACKAGE
14 Ld CERDIP
10 Pin Metal Can
14 Ld PDIP
PKG. NO.
F14.3
V+
V
REF
HI1-0200-5
HI2-0200-5
HI3-0200-5
HI1-0201-2
HI1-0201-4
HI1-0201-5
HI3-0201-5
HI4P0201-5
HI9P0201-5
HI9P0201-9
0 to 75
0 to 75
INPUT
T10.B
SOURCE
GATE
GATE
0 to 75
E14.3
LOGIC
INPUT
SWITCH
CELL
REFERENCE,
LEVEL SHIFTER,
AND DRIVER
-55 to 125
-25 to 85
0 to 75
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
F16.3
DRAIN
OUTPUT
F16.3
V-
F16.3
0 to 75
E16.3
TRUTH TABLE
HI-200
0 to 75
20 Ld PLCC
N20.35
M16.15
M16.15
LOGIC
HI-201
0 to 75
16 Ld SOIC
0
1
ON
ON
-40 to 85
16 Ld SOIC
OFF
OFF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HI-200, HI-201
Pinouts (Switches Shown For Logic “1” Input)
HI-200 (CERDIP, PDIP)
HI-201 (CERDIP, PDIP, SOIC)
HI-201 (PLCC)
TOP VIEW
TOP VIEW
TOP VIEW
A
1
2
3
4
5
6
7
14 A
1
A
1
2
3
4
5
6
7
8
16 A
2
2
1
OUT1
IN1
15 OUT2
14 IN2
13 V+
NC
GND
NC
13 NC
12 V+
11 NC
10 IN1
3
2
1
20 19
IN2
V+
18
17
IN1
V-
4
5
6
7
8
V-
GND
IN4
12 V
REF
IN2
11 IN3
16 NC
NC
OUT2
V-
9
8
OUT1
10 OUT3
OUT4
15
14
V
GND
IN4
REF
V
REF
9
A
3
A
4
IN3
HI-200 (METAL CAN)
9
10 11 12 13
TOP VIEW
V+
10
IN1
8
A
1
4
9
6
1
A
2
OUT1
2
3
7
V
GND
REF
IN2
V-
5
OUT2
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT V
CELL
TTL/CMOS REFERENCE CIRCUIT V CELL
REF
REF
HI-200
HI-201
V+
V+
6
R
6
R
300
600
R
R
2
2
5K
5K
Q
Q
P2
P2
Q
Q
P1
P1
Q
Q
P3
P5
P3
V
V
REF
REF
Q
Q
N4
N4
Q
P4
Q
Q
P4
Q
P5
M
M
P13
P13
TO P
TO P
2
2
Q
Q
N1
R
N1
R
D
3
D
3
3
3
M
N14
M
N14
24.2K
24.2K
R
4
5.4K
R
4
5.4K
M
P14
Q
Q
N2
N2
V
V
LL
Q
M
LL
N3
R
7.9K
R
5
7.9K
5
Q
P6
GND
V-
GND
V-
R
7
100K
R
7
100K
M
N15
M
N15
M
N16
M
N16
M
N17
N17
GND
GND
2
HI-200, HI-201
Schematic Diagrams (Continued)
SWITCH CELL
A’
Q
N11
V+
Q
N12
INPUT
OUTPUT
Q
P11
Q
N13
V-
Q
P12
A’
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
Q
P3
Q
P5
Q
P1
Q
P4
A’
V+
Q
N1
Q
Q
Q
P10
P7
Q
P8
Q
Q
P9
P6
D
D
1
TO V
TO V
LL
Q
REF
Q
N10
Q
N9
N8
200Ω
2
N7
Q
N6
Q
P2
A
V-
A’
Q
Q
N5
N2
Q
N4
Q
N3
V-
3
HI-200, HI-201
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . 44V ( 22)
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V, -5V
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
V
REF
14 Ld CERDIP Package . . . . . . . . . . . .
16 Ld CERDIP Package . . . . . . . . . . . .
PLCC Package. . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
16 Ld SOIC Package . . . . . . . . . . . . . .
10 Pin Metal Can Package . . . . . . . . . .
80
75
80
95
110
160
24
20
N/A
N/A
N/A
Analog Input Voltage (One Switch) . . . . . . . . . . (V+) +2V to (V-) -2V
Operating Conditions
75
Temperature Ranges
HI-201-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-201-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C
HI-200-5, HI-201-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C
Maximum Junction Temperature (Hermetic Packages) . . . . . 175 C
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150 C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . 300 C
o
o
o
o
o
o
o
o
o
o
o
HI-201-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
(PLCC and SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
Supplies = +15V, -15V; V
= Open; V (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V
AH
REF
-2
-4, -5, -9
TYP
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switch ON Time, t
HI-200
ON
25
25
-
-
-
240
185
500
500
-
-
-
-
240
185
-
-
-
ns
ns
ns
HI-201
Full
1000
1000
Switch OFF Time, t
HI-200
OFF
25
25
-
-
-
330
220
500
500
-
-
-
-
500
220
-
-
-
ns
ns
ns
HI-201
Full
1000
1000
Off Isolation
HI-200
(Note 4)
25
25
25
25
25
25
25
-
-
-
-
-
-
-
70
80
5.5
5.5
11
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70
80
5.5
5.5
11
5
-
-
-
-
-
-
-
dB
dB
pF
pF
pF
pF
pF
HI-201
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
D(OFF)
D(ON)
Output Switch Capacitance, C
Digital Input Capacitance, C
A
Drain-to-Source Capacitance, C
0.5
0.5
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
Full
Full
Full
-
2.4
-
-
-
-
0.8
-
-
2.4
-
-
-
-
0.8
-
V
V
AL
Input High Threshold, V
AH
Input Leakage Current (High or Low), I
(Note 3)
(Note 2)
1.0
1.0
µA
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
-15
-
+15
70
-15
-
+15
80
V
Ω
Ω
S
ON Resistance, r
ON
-
-
55
80
-
-
55
72
Full
100
100
4
HI-200, HI-201
Electrical Specifications
Supplies = +15V, -15V; V
= Open; V (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V (Continued)
REF
AH
-2
TYP
1
-4, -5, -9
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
MAX
5
MIN
TYP
1
MAX
50
UNITS
nA
OFF Input Leakage Current, I
(Note 6)
(Note 6)
(Note 6)
25
Full
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S(OFF)
HI-200
HI-201
100
2
500
5
10
2
500
50
nA
nA
Full
25
-
500
5
-
250
50
nA
OFF Output Leakage Current, I
1
1
nA
D(OFF)
HI-200
HI-201
Full
25
100
2
500
5
10
2
500
50
nA
nA
Full
25
35
1
500
5
35
1
250
50
nA
ON Leakage Current, I
HI-200
nA
D(ON)
Full
25
100
2
500
5
10
2
500
50
nA
HI-201
nA
Full
-
500
-
250
nA
POWER SUPPLY CHARACTERISTICS (Note 5)
Power Dissipation, P
25
Full
25
-
-
-
-
-
-
15
-
-
60
-
-
-
-
-
-
-
15
-
-
60
-
mW
mW
mA
mA
mA
mA
D
Current, I+
0.5
-
0.5
-
Full
25
2.0
-
2.0
-
Current, I-
0.5
-
0.5
-
Full
2.0
2.0
NOTES:
2. V
OUT
=
10V, I
= 1mA.
OUT
3. Digital Inputs are MOS gates: typical leakage is < 1nA.
4. V = 5V, R = 1kΩ, C = 10pF, V = 3V , f = 100kHz.
A
L
L
S
RMS
5. V = +3V or V = 0V for Both Switches.
A
A
6. Refer to Leakage Current Measurements (Figure 2).
o
Test Circuits and Waveforms T = 25 C, V
=
15V, V = 2.4V, V = 0.8V and V
AH AL
= Open
REF
A
SUPPLY
1mA
V
2
1mA
V
2
r
= ------------
ON
IN
OUT
V
IN
FIGURE 1A. ON RESISTANCE TEST CIRCUIT
5
HI-200, HI-201
o
Test Circuits and Waveforms T = 25 C, V
=
15V, V = 2.4V, V = 0.8V and V
AH AL
= Open (Continued)
REF
A
SUPPLY
80
100
50
0
70
V+ = +10V
V- = -10V
V
= 0V
IN
60
50
40
30
V+ = +12.5V
V- = -12.5V
V+ = +15V
V- = -15V
20
10
0
-50
-25
0
25
50
o
75
100
125
-15
-10
-5
0
5
10
15
TEMPERATURE ( C)
ANALOG SIGNAL LEVEL (V)
FIGURE 1B. ON RESISTANCE vs TEMPERATURE
FIGURE 1C. HI-200 ON RESISTANCE vs ANALOG SIGNAL
LEVEL
FIGURE 1. ON RESISTANCE
I
I
S(OFF)
D(OFF)
IN
OUT
100
10
A
A
14V
14V
+
I
/ I
S(OFF) D(OFF)
FIGURE 2B. OFF LEAKAGE CURRENT TEST CIRCUIT
I
D(ON)
IN
OUT
1.0
0.1
A
I
D(ON)
14V
25
50
75
100
o
125
TEMPERATURE ( C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2. LEAKAGE CURRENTS
FIGURE 2C. ON LEAKAGE CURRENT TEST CIRCUIT
90
80
70
60
50
40
30
20
IN
OUT
I
10
0
HI-201
V
IN
0
1
2
3
4
5
6
7
VOLTAGE ACROSS SWITCH ( V)
FIGURE 3A. SWITCH CURRENT vs VOLTAGE
FIGURE 3B. TEST CIRCUIT
FIGURE 3. SWITCH CURRENT
6
HI-200, HI-201
o
Test Circuits and Waveforms T = 25 C, V
=
15V, V = 2.4V, V = 0.8V and V
= Open (Continued)
REF
A
SUPPLY
AH
AL
V
= 4V
AH
DIGITAL
INPUT
50%
50%
V
= 0V
AL
t
t
ON
OFF
80%
80%
0V
SWITCH
OUTPUT
FIGURE 4A. MEASUREMENT POINTS
V
A
V
A
OUTPUT
OUTPUT
V
= 0 to 4V
V = 0 to 15V
A
A
Vertical: 2V/Div.
Horizontal: 100ns/Div.
Vertical: 5V/Div.
Horizontal: 100ns/Div.
FIGURE 4B. WAVEFORMS WITH TTL COMPATIBLE LOGIC
INPUT
FIGURE 4C. WAVEFORMS WITH CMOS COMPATIBLE LOGIC
INPUT
FIGURE 4. SWITCH t
AND t
OFF
ON
140
120
100
80
R
= 1kΩ
L
60
40
20
0
100Hz
1kHz
10kHz
100kHz
1MHz
FREQUENCY (Hz)
FIGURE 5. HI-201 OFF ISOLATION vs FREQUENCY
For more information see Application Notes AN520, AN521, AN531, AN532 and AN557.
7
HI-200, HI-201
Application Information
Single Supply Operation
The switch operation of the HI-200/201 is dependent upon
an internally generated switching threshold voltage
optimized for 15V power supplies. The HI-200/201 does not
provide the necessary internal switching threshold in a
single supply system. Therefore, if single supply operation is
required, the HI-300 series of switches is recommended.
The HI-300 series will remain operational to a minimum +5V
single supply.
Switch performance will degrade as power supply voltage is
reduced from optimum levels ( 15V). So it is recommended
that a single supply design be thoroughly evaluated to
ensure that the switch will meet the requirements of the
application.
For further information see Application Notes AN520,
AN521, AN531, AN532, AN543 and AN557.
8
HI-200
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
54 mils x 79 mils
Type: Nitride over Silox
Nitride Thickness: 3.5kÅ 1kÅ
Silox Thickness: 12kÅ 2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ 2kÅ
WORST CASE CURRENT DENSITY:
5
2
2 x 10 A/cm at 25mA
Metallization Mask Layout
HI-200
GND
2
V+
9
A
A
1
2
1
10
IN 1
8
IN 2
3
OUT 1
4
5
6
7
OUT 2
V-
V
REF
9
HI-201
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
81 mils x 85 mils
Type: Nitride over Silox
Nitride Thickness: 3.5kÅ 1kÅ
Silox Thickness: 12kÅ 2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ 2kÅ
WORST CASE CURRENT DENSITY:
5
2
2 x 10 A/cm at 25mA
Metallization Mask Layout
HI-201
A
A
2
1
2
1
16
15
OUT 2
OUT 1
14
13
IN 2
V+
3
IN 1
V-
4
5
GND
12
11
V
REF
IN 4
6
7
IN 3
OUT 4
OUT 3
8
9
10
A
A
3
4
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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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10
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