HI4P0201HS-5 [INTERSIL]

High Speed, Quad SPST, CMOS Analog Switch; 高速,四通道SPST , CMOS模拟开关
HI4P0201HS-5
型号: HI4P0201HS-5
厂家: Intersil    Intersil
描述:

High Speed, Quad SPST, CMOS Analog Switch
高速,四通道SPST , CMOS模拟开关

开关
文件: 总11页 (文件大小:256K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HI-201HS  
Data Sheet  
July 1999  
File Number 3123.2  
High Speed, Quad SPST, CMOS Analog  
Switch  
Features  
• Fast Switching Times  
The HI-201HS is a monolithic CMOS Analog Switch  
featuring very fast switching speeds and low ON resistance.  
The integrated circuit consists of four independently  
selectable SPST switches and is pin compatible with the  
industry standard HI-201 switch.  
- t  
- t  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns  
ON  
OFF  
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . 30Ω  
• Pin Compatible with Standard HI-201  
• Wide Analog Voltage Range (±15V Supplies) . . . . . . . ±15V  
• Low Charge Injection (±15V Supplies) . . . . . . . . . . 10pC  
• TTL Compatible  
Fabricated using silicon-gate technology and the Intersil  
Dielectric Isolation process, this TTL compatible device offers  
improved performance over previously available CMOS analog  
switches. Featuring maximum switching times of 50ns, low ON  
resistance of 50maximum, and a wide analog signal range, the  
HI-201HS is designed for any application where improved  
switching performance, particularly switching speed, is required.  
(A more detailed discussion on the design and application of the  
HI-201HS can be found in Application Note AN543.)  
• Symmetrical Switching Analog Current Range . . . . . 80mA  
Applications  
• High Speed Multiplexing  
• High Frequency Analog Switching  
• Sample and Hold Circuits  
• Digital Filters  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
HI1-0201HS-2  
HI1-0201HS-4  
HI1-0201HS-5  
HI3-0201HS-5  
HI4P0201HS-5  
HI9P0201HS-5  
HI9P0201HS-9  
-55 to 125 16 Ld CERDIP  
F16.3  
• Operational Amplifier Gain Switching Networks  
• Integrator Reset Circuits  
-25 to 85  
0 to 75  
0 to 75  
0 to 75  
0 to 75  
-40 to 85  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
20 Ld PLCC  
16 Ld SOIC  
16 Ld SOIC  
F16.3  
F16.3  
E16.3  
N20.35  
M16.3  
M16.3  
Pinouts (Switches Shown For Logic “1” Input)  
HI-201HS (CERDIP, PDIP, SOIC)  
HI201HS (PLCC)  
TOP VIEW  
TOP VIEW  
A
1
2
3
4
5
6
7
8
16  
A
2
1
2
19  
3
1
20  
OUT1  
IN1  
15 OUT2  
14 IN2  
13 V+  
4
5
6
7
8
18  
17  
16  
15  
14  
IN 2  
V+  
IN 1  
V-  
V-  
GND  
IN4  
12 NC  
11 IN3  
10 OUT3  
GND  
IN 4  
OUT4  
IN 3  
9
A
3
A
4
12  
9
10 11  
13  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
HI-201HS  
TRUTH TABLE  
Functional Diagram  
V+  
LOGIC  
SWITCH  
0
1
ON  
OFF  
SOURCE  
GATE  
INPUT  
LEVEL  
SHIFTER  
AND  
SWITCH  
CELL  
TTL  
LOGIC  
INPUT  
GATE  
DRIVER  
DRAIN  
OUTPUT  
V-  
Schematic Diagrams  
TTL/CMOS REFERENCE CIRCUIT  
SWITCH CELL  
V+  
MP42  
V+  
Q
MP43  
QN43  
MP44  
MP45  
P41  
MN31  
QN41  
C48  
C49  
ANALOG  
IN  
ANALOG  
OUT  
QN45  
MP33  
QN42  
R42  
R41  
QP44  
MP32  
MN32  
QN44  
V
R1  
D41  
5V  
MN33  
D42  
5.6V  
MP31  
QP41  
Q
QP42  
V-  
MN42  
MN44  
MN45  
V-  
2
HI-201HS  
Schematic Diagrams (Continued)  
DIGITAL INPUT BUFFER AND LEVEL SHIFTER  
M
M
P51  
N46  
M
P52  
M
M
P4  
P8  
Q
Q
N6  
N8  
Q
M
M
Q
N9  
P3  
P7  
N7  
I
I
I
X4  
X3  
Q
I
V
I
X1  
X2  
M
M
P10  
R1  
P6  
M
M
P5  
P9  
M
M
P12  
P11  
Q
N1  
I
Q
M
M
N12  
N11  
Q
Q
C
R
1
1
V
EE  
Q
N4  
Q
N5  
VA  
Q
N2  
Q
Q
P1  
P4  
V
CC  
V
R1  
R
3
Q
C
P5  
M
P13  
R
2
2
M
P14  
Q
P2  
I
X3  
M
M
M
N10  
M
N9  
N5  
C
FF  
M
N6  
M
M
N14  
N13  
Q
I
X1  
P7  
I
X2  
M
N3  
M
N7  
M
Q
N4  
N8  
P9  
Q
P6  
Q
P8  
M
N52  
M
N51  
REPEAT FOR EACH  
LEVEL SHIFTER  
3
HI-201HS  
Absolute Maximum Ratings  
Thermal Information  
o
o
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V  
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V  
Analog Input Voltage (One Switch) . . . . . . . (V+) +2.0V to (V-) -2.0V  
Peak Current, S or D (Pulse 1ms, 10% Duty Cycle Max) . . . . 50mA  
Continuous Current Any Terminal (Except S or D) . . . . . . . . . 25mA  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
CERDIP Package. . . . . . . . . . . . . . . . .  
PDIP Package . . . . . . . . . . . . . . . . . . .  
PLCC Package. . . . . . . . . . . . . . . . . . .  
SOIC Package . . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature  
80  
90  
80  
30  
N/A  
N/A  
N/A  
100  
o
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C  
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C  
Operating Conditions  
o
Temperature Ranges  
HI-201HS-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
HI-201HS-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C  
HI-201HS-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C  
o
o
o
o
o
o
o
(SOIC, PLCC - Lead Tips Only)  
o
o
o
o
HI-201HS-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = +0.8V, GND = 0V,  
AH  
AL  
Unless Otherwise Specified  
-2  
-4, -5, -9  
TYP  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MIN  
TYP  
MAX  
MIN  
MAX UNITS  
DYNAMIC CHARACTERISTICS  
Switch ON Time, t  
ON  
(Note 3)  
(Note 3)  
(Note 3)  
To 0.1%  
(Note 6)  
(Note 4)  
(Note 5)  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
-
-
-
-
-
-
-
-
-
-
-
-
30  
40  
50  
50  
-
-
-
-
-
-
-
-
-
-
-
-
-
30  
40  
50  
50  
-
ns  
ns  
ns  
ns  
pC  
dB  
dB  
pF  
pF  
pF  
pF  
pF  
Switch OFF Time, t  
OFF1  
OFF2  
Switch OFF Time, t  
150  
180  
10  
150  
180  
10  
Output Settling Time  
Charge Injection, Q  
OFF Isolation  
-
-
-
-
72  
-
72  
-
Crosstalk  
86  
-
86  
-
Input Switch Capacitance, C  
Output Switch Capacitance  
10  
-
10  
-
S(OFF)  
C
C
10  
-
10  
-
D(OFF)  
30  
-
30  
-
D(ON)  
Digital Input Capacitance, C  
18  
-
18  
-
A
Drain-To-Source Capacitance, C  
DS(OFF)  
0.5  
-
0.5  
-
DIGITAL INPUT CHARACTERISTICS  
Input Low Threshold, V  
Full  
25  
-
-
0.8  
-
-
0.8  
V
V
AL  
Input High Threshold, V  
2.0  
-
-
-
-
2.0  
-
-
-
-
AH  
Full  
25  
2.4  
2.4  
V
Input Leakage Current (Low), I  
AL  
-
-
-
-
200  
-
-
-
-
-
-
200  
-
-
µA  
µA  
µA  
µA  
Full  
25  
500  
-
500  
-
Input Leakage Current (High), I  
AH  
V
= 4.0V  
20  
-
20  
-
AH  
Full  
40  
40  
ANALOG SWITCH CHARACTERISTICS  
Analog Signal Range, V  
Full  
25  
-15  
-
30  
-
+15  
50  
-15  
-
30  
-
+15  
50  
V
S
ON Resistance, r  
ON  
(Note 2)  
-
-
-
-
Full  
75  
75  
4
HI-201HS  
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = +0.8V, GND = 0V,  
AH  
AL  
Unless Otherwise Specified (Continued)  
-2  
TYP  
3
-4, -5, -9  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MIN  
MAX  
-
MIN  
TYP  
3
MAX UNITS  
r
Match  
25  
25  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
%
ON  
OFF Input Leakage Current, I  
0.3  
-
10  
0.3  
-
10  
50  
10  
50  
10  
50  
nA  
nA  
nA  
nA  
nA  
nA  
S(OFF)  
Full  
25  
100  
10  
OFF Output Leakage Current, I  
0.3  
-
0.3  
-
D(OFF)  
Full  
25  
100  
10  
ON Leakage Current, I  
0.1  
-
0.1  
-
D(ON)  
Full  
100  
POWER SUPPLY CHARACTERISTICS (Note 7)  
Power Dissipation, P  
Current, I+ (Pin 13)  
Current, I- (Pin 4)  
NOTES:  
25  
Full  
25  
-
-
-
-
-
-
120  
-
-
240  
-
-
-
-
-
-
-
120  
-
-
240  
-
mW  
mW  
mA  
mA  
mA  
mA  
D
4.5  
-
4.5  
-
Full  
25  
10.0  
-
10.0  
-
3.5  
-
3.5  
-
Full  
6
6
2. V  
OUT  
= ±10V, I  
= 1mA.  
OUT  
3. R = 1k, C = 35pF, V = +10V, V = +3V. (See Figure 1).  
IN  
L
L
A
4. V = 3V, R = 1k, C = 10pF, V = 3V  
IN  
, f = 100kHz.  
A
L
L
RMS  
5. V = 3V, R = 1k, V = 3V , f = 100kHz.  
IN RMS  
A
L
6. C = 1nF, V = 0V, Q = C x V .  
IN  
L
L
O
7. V = 3V or V = 0 for all switches.  
A
A
Test Circuits and Waveforms  
V
= 3.0V  
AH  
DIGITAL  
INPUT  
50%  
50%  
V
= 0V  
AL  
t
OFF1  
t
ON  
90%  
90%  
0V  
10%  
SWITCH  
OUTPUT  
t
OFF2  
TOP: Logic Input (2V/Div.) BOTTOM: Output (5V/Div.)  
HORIZONTAL: 100ns/Div.  
FIGURE 1A. MEASUREMENT POINTS  
FIGURE 1B. WAVEFORMS  
5
HI-201HS  
Test Circuits and Waveforms (Continued)  
V+ = +15V  
13  
SWITCH  
INPUT  
SWITCH  
OUTPUT  
3
1
2
V
O
V
= +10V  
IN  
R
1kΩ  
C
L
L
V
A
35pF  
LOGIC  
INPUT  
5
4
R
L
V
= V  
IN  
O
R
+ r  
L
ON  
V- = -15V  
C
INCLUDES C + C  
FIXTURE  
GND  
L
PROBE  
FIGURE 1C. TEST CIRCUIT  
FIGURE 1. SWITCH t AND t  
ON OFF  
3
2
1
0
+10  
+5  
0
t
O
t
O
FIGURE 2A. LOGIC INPUT WAVEFORM  
FIGURE 2B. V = +10V  
IN  
+5  
0
+5  
0
+5  
t
O
t
O
FIGURE 2C. V = +5V  
IN  
FIGURE 2D. V = 0V  
IN  
6
HI-201HS  
Test Circuits and Waveforms (Continued)  
0
-5  
0
-5  
-10  
t
t
O
O
FIGURE 2E. V = -5V  
IN  
FIGURE 2F. V = -10V  
IN  
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES  
Power Supply Considerations  
Application Information  
The electrical characteristics specified in this data sheet are  
Logic Compatibility  
guaranteed for power supplies V = ±15V. Power supply  
S
The HI-201HS is TTL compatible. Its logic inputs (pins 1, 8,  
9, and 16) are designed to react to digital inputs which  
exceed a fixed, internally generated TTL switching threshold.  
The HI-201HS can also be driven with CMOS logic (0V-  
15V), although the switch performance with CMOS logic will  
be inferior to that with TTL logic (0V-5V).  
voltages less than ±15V will result in reduced switch  
performance. The following information is intended as a  
design aid only.  
POWER SUPPLY  
VOLTAGES  
SWITCH PERFORMANCE  
Minimal Variation  
±12 V ≤ ±15V  
The logic input design of the HI-201HS is largely responsible  
for its fast switching speed. It is a design which features a  
unique input stage consisting of complementary vertical  
PNP and NPN bipolar transistors. This design differs from  
that of the standard HI-201 product where the logic inputs  
are MOS transistors.  
S
V
< ±12V  
Parametric variation becomes  
increasingly large (increased ON  
resistance, longer switching times).  
S
V
V
< ±10V  
> ±16V  
Not Recommended.  
Not Recommended.  
S
S
Although the new logic design enhances the switching  
speed performance, it also increases the logic input leakage  
currents. Therefore, the HI-201HS will exhibit larger digital  
input leakage currents in comparison to the standard HI-201  
product.  
Single Supply  
The switch operation of the HI-201HS is dependent upon an  
internally generated switching threshold voltage optimized  
for ±15V power supplies. The HI-201HS does not provide  
the necessary internal switching threshold in a single supply  
system. Therefore, if single supply operation is required, the  
HI-300 series of switches is recommended. The HI-300  
series will remain operational to a minimum +5V single  
supply.  
Charge Injection  
Charge injection is the charge transferred, through the  
internal gate-to-channel capacitances, from the digital logic  
input to the analog output. To optimize charge injection  
performance for the HI-201HS, it is advisable to provide a  
TTL logic input with fast rise and fall times.  
Switch performance will degrade as power supply voltage is  
reduced from optimum levels (±15V). So it is recommended  
that a single supply design be thoroughly evaluated to  
ensure that the switch will meet the requirements of the  
application.  
If the power supplies are reduced from ±15V, charge  
injection will become increasingly dependent upon the digital  
input frequency. Increased logic input frequency will result in  
larger output error due to charge injection.  
For further information see Application Notes AN520,  
AN521, AN531, AN532, AN543 and AN557.  
7
HI-201HS  
Typical Performance Curves  
80  
80  
70  
60  
50  
40  
30  
20  
10  
0
o
V+ = +15V, V- = -15V  
T
= 25 C  
A
70  
60  
50  
V+ = +8V, V- = -8V  
V+ = +10V, V- = -10V  
o
125 C  
40  
o
25 C  
30  
o
-55 C  
V+ = +12V, V- = -12V  
V+ = +15V, V- = -15V  
20  
10  
0
-15  
-10  
-5  
0
5
10  
15  
-15  
-10  
-5  
0
5
10  
15  
ANALOG INPUT (V)  
ANALOG INPUT (V)  
FIGURE 3. ON RESISTANCE vs ANALOG SIGNAL LEVEL  
100.0  
FIGURE 4. ON RESISTANCE vs ANALOG SIGNAL LEVEL  
100.0  
10.0  
1.0  
10.0  
1.0  
0.10  
0.01  
0.10  
0.01  
25  
75  
TEMPERATURE ( C)  
125  
25  
75  
125  
o
o
TEMPERATURE ( C)  
FIGURE 5. I  
OR I  
D(OFF)  
vs TEMPERATURE   
FIGURE 6. I  
D(ON)  
vs TEMPERATURE †  
S(OFF)  
o
Theoretically, leakage current will continue to decrease below 25 C. But due to environmental conditions, leakage measurements below this  
temperature are not representative of actual switch performance.  
7
100  
V+ = +15V, V- = -15V  
V+ = +15V, V- = -15V  
80  
60  
40  
I
I
V = 0V  
6
5
4
3
2
1
0
S(OFF)  
D(OFF)  
D
V = 0V  
S
20  
0
I
DON  
I+  
I-  
-20  
-40  
-60  
-80  
-100  
-120  
-140  
-160  
-180  
-200  
I
/I  
S(OFF) D(OFF)  
-55  
-35  
-15  
5
25  
45  
65  
85  
105 125  
-14 -12 -10 -8 -6 -4 -2  
0
2
4
6
8
10 12 14  
o
TEMPERATURE ( C)  
ANALOG INPUT (V)  
FIGURE 7. SUPPLY CURRENT vs TEMPERATURE  
FIGURE 8. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE  
8
HI-201HS  
Typical Performance Curves (Continued)  
60  
40  
20  
0
-20  
-40  
-60  
-80  
10  
9
o
V
= 0V, V  
AH2  
= 3V, V = 5V  
AH1  
V+ = +15V, V- = -15V, T = 25 C  
AL  
A
I
AH1  
8
I
I
V = 0V  
S(OFF)  
D(OFF)  
D
7
V = 0V  
S
6
5
4
3
2
1
-100  
-120  
-140  
-160  
-180  
-200  
-220  
-240  
-260  
-280  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
I
AH2  
I
AL  
25  
35  
45  
55  
65  
75  
85  
95 105 115 125  
-16.0 -15.5 -15.0 -14.5 -14.0 14.0 14.5 15.0 15.5 16.0  
o
TEMPERATURE ( C)  
ANALOG INPUT (V)  
FIGURE 9. DIGITAL INPUT LEAKAGE CURRENT vs  
FIGURE 10. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE  
TEMPERATURE †  
o
Theoretically, leakage current will continue to decrease below 25 C. But due to environmental conditions, leakage measurements below this  
temperature are not representative of actual switch performance.  
180  
160  
350  
300  
250  
200  
150  
100  
o
R
= 1k, C = 35pF, T = 25 C  
L A  
L
t
OFF2  
140  
120  
100  
V+ = +15V  
V- = -15V  
t
OFF2  
R
C
= 1kΩ  
= 35pF  
L
L
80  
60  
40  
t
OFF1  
t
OFF1  
t
ON  
50  
0
20  
0
t
ON  
-55  
-35  
-15  
5
25  
45  
65  
85  
105 125  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
o
SUPPLY VOLTAGE (±V)  
TEMPERATURE ( C)  
FIGURE 11. SWITCHING TIME vs TEMPERATURE  
FIGURE 12. SWITCHING TIME vs SUPPLY VOLTAGE  
350  
350  
V+ = +15V, R = 1kΩ  
V- = -15V, R = 1kΩ  
L
L
o
o
C
= 35pF, T = 25 C  
C
= 35pF, T = 25 C  
L
A
L
A
300  
250  
200  
150  
100  
50  
300  
250  
200  
150  
100  
t
OFF2  
t
t
OFF2  
OFF1  
t
OFF1  
t
50  
0
ON  
t
ON  
0
5
6
7
8
9
10  
11  
12  
13  
14  
15  
-5  
-6  
-7  
-8  
-9  
-10 -11 -12 -13 -14 -15  
POSITIVE SUPPLY (V)  
NEGATIVE SUPPLY (V)  
FIGURE 13. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE  
FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE  
9
HI-201HS  
Typical Performance Curves (Continued)  
350  
3.0  
2.5  
V + = +15V, V- = -15V, R = 1kΩ  
L
o
C
= 35pF, V = 0V, T = 25 C  
300  
250  
200  
150  
100  
L
AL  
A
2.0  
1.8  
1.5  
1.0  
0.5  
0
t
t
OFF2  
OFF1  
50  
0
t
ON  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
2
3
4
5
SUPPLY VOLTAGE (±V)  
DIGITAL INPUT VOLTAGE (V)  
FIGURE 15. SWITCHING TIME vs INPUT LOGIC VOLTAGE  
FIGURE 16. INPUT SWITCHING THRESHOLD vs SUPPLY  
VOLTAGE  
40  
50  
OUT  
IN  
V  
O
C
35  
30  
25  
20  
15  
10  
5
D(ON)  
40  
30  
C
L
20  
V
A
10  
Q
0
Q = C x V  
L
O
-10  
-20  
-30  
-40  
-50  
C
OR C  
S(OFF)  
D(OFF)  
V+ = +15V, V- = -15V  
C
DS(OFF)  
C
= 1nF  
L
0
-15  
-10  
-5  
0
5
10  
-10  
-5  
0
5
10  
15  
ANALOG INPUT (V)  
ANALOG INPUT (V)  
FIGURE 17. CHARGE INJECTION vs ANALOG VOLTAGE  
FIGURE 18. CAPACITANCE vs ANALOG VOLTAGE  
140  
140  
V+ = +15V, V- = -15V  
V+ = +15V, V- = -15V  
= 3V , V = 3V  
V
= 3V  
RMS  
, V = 3V  
A
V
IN  
IN  
RMS  
A
120  
100  
80  
120  
100  
80  
IN  
OUT  
V
O1  
R
= 100Ω  
L
V
R
= 1kΩ  
IN  
L
L
60  
IN  
OUT  
60  
V
O
V
O2  
V
R
IN  
40  
L
R
= 1kΩ  
40  
L
R
= 1kΩ  
V
IN  
20  
0
20  
0
OFF ISOLATION = 20 Log  
V
O2  
V
O
CROSSTALK = 20 Log  
100K  
V
O1  
10K  
100K  
1M  
10M  
10K  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 19. OFF ISOLATION vs FREQUENCY  
FIGURE 20. CROSSTALK vs FREQUENCY  
10  
HI-201HS  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
2440µm x 2860µm x 485µm  
Type: Nitride Over Silox  
Nitride Thickness: 3.5kÅ ±1kÅ  
Silox Thickness: 12kÅ ±2kÅ  
METALLIZATION:  
Type: CuAl  
Thickness: 16kÅ ±2kÅ  
WORST CASE CURRENT DENSITY:  
4
2
9.5 x 10 A/cm  
Metallization Mask Layout  
HI-201HS  
A1  
A2  
OUT2  
OUT1  
IN2  
V+  
IN1  
V-  
GND  
IN4  
IN3  
OUT4  
OUT3  
A4  
A3  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
11  

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