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HI3-0506A-5 [INTERSIL]

16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection; 16通道， 8通道，差分8通道和差分4通道， CMOS模拟的MUX与Active过压保护
HI3-0506A-5
型号： HI3-0506A-5
厂家： Intersil    Intersil
描述：

16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection
16通道， 8通道，差分8通道和差分4通道， CMOS模拟的MUX与Active过压保护

光电二极管
文件： 总15页 (文件大小：236K)
中文：  中文翻译
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HI-506A, HI-507A, HI-508A, HI-509A  
Data Sheet  
June 1999  
File Number 3143.2  
16-Channel, 8-Channel, Differential  
8-Channel and Differential 4-Channel,  
CMOS Analog MUXs with Active  
Overvoltage Protection  
Features  
• Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70V  
P-P  
• No Channel Interaction During Overvoltage  
• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V  
• Fail Safe with Power Loss (No Latch-Up)  
The HI-506A, HI-507A, HI-508A and HI-509A are analog  
multiplexers with active overvoltage protection. Analog input  
levels may greatly exceed either power supply without  
damaging the device or disturbing the signal path of other  
channels. Active protection circuitry assures that signal  
fidelity is maintained even under fault conditions that would  
destroy other multiplexers. Analog inputs can withstand  
• Break-Before-Make Switching  
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V  
• Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns  
• Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW  
constant 70V  
levels with ±15V supplies. Digital inputs will  
P-P  
also sustain continuous faults up to 4V greater than either  
supply. In addition, signal sources are protected from short  
circuiting should multiplexer supply loss occur. Each input  
presents 1kΩ of resistance under this condition. These  
features make the HI-506A, HI-507A, HI-508A and HI-509A  
ideal for use in systems where the analog inputs originate  
from external equipment, or separately powered circuitry. All  
devices are fabricated with 44V dielectrically isolated CMOS  
technology. The HI-506A is a single 16-Channel multiplexer,  
the HI-507A is an 8-Channel differential multiplexer, the  
HI-508A is a single 8-Channel multiplexer and the HI-509A is  
a differential 4-Channel multiplexer. If input overvoltage  
protection is not needed the HI-506/507/508/509  
Applications  
• Data Acquisition Systems  
• Industrial Controls  
• Telemetry  
Ordering Information  
PART  
NUMBER  
TEMP. RANGE  
PKG.  
NO.  
o
( C)  
PACKAGE  
28 Ld CERDIP  
28 Ld CERDIP  
28 Ld CERDIP  
HI1-0506A-2  
HI1-0506A-5  
HI1-0506A-8  
-55 to 125  
0 to 75  
F28.6  
F28.6  
F28.6  
multiplexers are recommended. For further information see  
Application Notes AN520 and AN521.  
-55 to 125  
+ 160 Hour Burn-In  
HI3-0506A-5  
HI1-0507A-8  
0 to 75  
28 Ld PDIP  
E28.6  
F28.6  
-55 to 125  
28 Ld CERDIP  
+ 160 Hour Burn-In  
HI3-0507A-5  
HI1-0508A-7  
0 to 75  
28 Ld PDIP  
E28.6  
F16.3  
0 to 75  
16 Ld CERDIP  
+ 96 Hour Burn-In  
HI1-0508A-8  
-55 to 125  
16 Ld CERDIP  
F16.3  
+ 160 Hour Burn-In  
HI3-0508A-5  
HI1-0509A-2  
HI1-0509A-5  
HI1-0509A-8  
+0 to 75  
-55 to 125  
0 to 75  
16 Ld PDIP  
E16.3  
F16.3  
F16.3  
F16.3  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
-55 to 125  
+ 160 Hour Burn-In  
HI3-0509A-5  
0 to 75  
16 Ld PDIP  
E16.3  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
HI-506A, HI-507A, HI-508A, HI-509A  
Pinouts  
HI-506A (CERDIP, PDIP)  
TOP VIEW  
HI-507A (CERDIP, PDIP)  
TOP VIEW  
+V  
1
2
3
4
5
6
7
8
9
28 OUT  
27 -V  
+V  
1
2
3
4
5
6
7
8
9
28 OUT A  
27 -V  
SUPPLY  
NC  
SUPPLY  
OUT B  
SUPPLY  
SUPPLY  
26 IN 8  
25 IN 7  
24 IN 6  
23 IN 5  
22 IN 4  
21 IN 3  
26 IN 8A  
25 IN 7A  
24 IN 6A  
23 IN 5A  
22 IN 4A  
21 IN 3A  
NC  
IN 16  
IN 15  
IN 14  
IN 13  
IN 12  
IN 11  
NC  
IN 8B  
IN 7B  
IN 6B  
IN 5B  
IN 4B  
IN 3B  
20  
20  
IN 2A  
IN 2  
IN 10 10  
IN 9 11  
GND 12  
19 IN 1  
IN 2B 10  
IN 1B 11  
GND 12  
19 IN 1A  
18 ENABLE  
18 ENABLE  
17 ADDRESS A  
16 ADDRESS A  
15 ADDRESS A  
17 ADDRESS A  
16 ADDRESS A  
15 ADDRESS A  
0
1
2
0
1
2
V
13  
V
13  
REF  
REF  
ADDRESS A 14  
NC 14  
3
HI-508A (CERDIP, PDIP)  
HI-509A (CERDIP, PDIP)  
TOP VIEW  
TOP VIEW  
A
1
2
3
4
5
6
7
8
16 A  
15 A  
A
1
2
3
4
5
6
7
8
16 A  
1
0
1
2
0
ENABLE  
ENABLE  
15 GND  
14 +V  
SUPPLY  
-V  
14 GND  
13 +V  
-V  
SUPPLY  
IN 1  
SUPPLY  
IN 1A  
13 IN 1B  
12 IN 2B  
11 IN 3B  
10 IN 4B  
SUPPLY  
IN 2  
IN 3  
IN 4  
OUT  
12 IN 5  
11 IN 6  
10 IN 7  
IN 2A  
IN 3A  
IN 4A  
9
IN 8  
9 OUT B  
OUT A  
2
HI-506A, HI-507A, HI-508A, HI-509A  
Truth Tables  
HI-506A  
EN  
HI-508A  
A
A
A
A
“ON” CHANNEL  
3
2
1
0
A
A
A
0
EN  
L
“ON” CHANNEL  
2
1
X
X
X
X
L
None  
1
X
X
X
None  
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
2
L
L
H
H
L
3
L
H
H
L
L
L
H
L
4
L
H
L
L
H
H
H
H
L
5
H
H
H
H
L
L
H
L
6
L
H
L
L
H
H
L
7
H
H
L
H
L
8
H
H
H
H
H
H
H
H
H
9
HI-509A  
L
L
H
L
10  
11  
12  
13  
14  
15  
16  
A
A
EN  
L
“ON” CHANNEL PAIR  
L
H
H
L
1
0
X
X
None  
L
H
L
L
L
L
H
L
H
1
2
3
4
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
HI-507A  
A
A
A
0
EN  
L
“ON” CHANNEL PAIR  
2
1
X
X
X
None  
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
3
HI-506A, HI-507A, HI-508A, HI-509A  
Functional Diagrams  
HI-506A  
HI-507A  
OUT  
A
1K  
OUT  
1K  
1K  
IN 1A  
IN 1  
IN 2  
1K  
IN 8A  
OUT  
B
1K  
DECODER/  
DRIVER  
IN 1B  
1K  
IN 16  
1K  
DECODER/  
DRIVER  
IN 8B  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
ISOLATION  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
† † † † †  
ISOLATION  
† DIGITAL INPUT  
†
†
†
†
PROTECTION  
V
A
A
A
A EN  
3
REF  
0
1
2
† DIGITAL INPUT  
V
A
A
A
2
EN  
PROTECTION  
REF  
0
1
HI-508A  
HI-509A  
OUT  
A
1K  
OUT  
1K  
1K  
IN 1A  
IN 1  
IN 2  
1K  
1K  
IN 4A  
IN 1B  
OUT  
B
DECODER/  
DRIVER  
1K  
IN 8  
1K  
DECODER/  
DRIVER  
IN 4B  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
ISOLATION  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
†
†
†
†
ISOLATION  
† DIGITAL INPUT  
†
†
†
PROTECTION  
A
A
A
2
EN  
0
1
† DIGITAL INPUT  
A
A
EN  
PROTECTION  
0
1
4
HI-506A, HI-507A, HI-508A, HI-509A  
Schematic Diagrams  
ADDRESS INPUT BUFFER AND LEVEL SHIFTER  
TTL REFERENCE  
CIRCUIT  
V+  
R10  
R9  
Q1  
V
REF  
Q4  
D3  
GND  
LEVEL SHIFTER  
V+  
P
N
P
P
P
P
P
P
P
P
OVERVOLTAGE  
P
R2  
R3  
LEVEL  
PROTECTION  
R5  
R7  
R8  
SHIFTED  
ADDRESS  
TO  
V+  
D2  
R4  
DECODE  
R6  
N
N
N
N
N
N
N
N
R1  
200  
Ω
D1  
N
V-  
V-  
GND  
ADD  
IN  
ADDRESS DECODER  
V+  
P
P
P
P
P
P
P
TO P-CHANNEL  
DEVICE OF  
THE SWITCH  
N
N
N
A
OR A  
0
0
N
N
N
N
A
OR A  
1
1
TO N-CHANNEL  
DEVICE OF  
THE SWITCH  
A
OR A  
2
2
A
OR A  
3
3
ENABLE  
DELETE A OR A INPUT  
3
3
V-  
FOR HI-507A, HI-508A, HI-509A  
DELETE A OR A INPUT FOR HI-509A  
2
2
5
HI-506A, HI-507A, HI-508A, HI-509A  
Schematic Diagrams (Continued)  
MULTIPLEX SWITCH  
FROM DECODE  
OVERVOLTAGE PROTECTION  
N
V+  
Q5  
P
D7 D4  
D5  
D6  
N
R11  
1K  
IN  
OUT  
N
Q6  
V-  
P
FROM DECODE  
6
HI-506A, HI-507A, HI-508A, HI-509A  
Absolute Maximum Ratings  
Thermal Information  
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V  
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V  
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
28 Ld CERDIP Package. . . . . . . . . . . .  
16 Ld CERDIP Package. . . . . . . . . . . .  
28 Ld PDIP Package . . . . . . . . . . . . . .  
16 Ld PDIP Package . . . . . . . . . . . . . .  
Maximum Junction Temperature  
55  
85  
60  
90  
18  
32  
N/A  
N/A  
Digital Input Voltage (V , V ) . . . . . . . . . . . . . (V-) -4V to (V+) +4V  
EN  
A
or 20mA, Whichever Occurs First  
Analog Signal (V , V  
IN OUT  
). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V  
o
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA  
Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max). . 40mA  
CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C  
PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C  
o
o
o
o
Operating Conditions  
Temperature Ranges  
HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55 C to 125 C  
HI-506A/507A/508A/509A-5, -7 . . . . . . . . . . . . . . . . . 0 C to 75 C  
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications Supplies = +15V, -15V; V  
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V,  
AH AL  
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section  
REF  
-2, -8  
-5, -7  
TYP  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MIN  
TYP  
MAX  
MIN  
MAX  
UNITS  
DYNAMIC CHARACTERISTICS  
Access Time, t  
Note 2  
25  
Full  
25  
-
-
0.5  
-
-
-
-
0.5  
-
-
µs  
µs  
ns  
ns  
ns  
ns  
ns  
A
1.0  
1.0  
Break-Before-Make Delay, t  
Note 2  
Note 2  
25  
-
80  
300  
-
-
25  
-
80  
300  
-
-
OPEN  
Enable Delay (ON), t  
25  
500  
1000  
500  
1000  
-
ON(EN)  
Full  
25  
-
-
1000  
-
Enable Delay (OFF), t  
Note 2  
-
300  
-
-
300  
-
OFF(EN)  
Full  
-
-
1000  
Settling Time, t  
S
HI-506A and HI-507A  
To 0.1%  
To 0.01%  
To 0.1%  
To 0.01%  
Note 7  
25  
25  
25  
25  
25  
25  
-
-
1.2  
3.5  
1.2  
3.5  
68  
-
-
-
-
-
-
-
-
1.2  
3.5  
1.2  
3.5  
68  
-
-
-
-
-
-
µs  
µs  
µs  
µs  
dB  
pF  
HI-508A and HI-509A  
-
-
-
-
Off Isolation  
Channel Input Capacitance, C  
50  
-
50  
-
10  
10  
S(OFF)  
Channel Output Capacitance, C  
HI-506A  
D(OFF)  
25  
25  
25  
25  
25  
25  
-
-
-
-
-
-
52  
30  
25  
12  
10  
0.1  
-
-
-
-
-
-
-
-
-
-
-
-
52  
30  
25  
12  
10  
0.1  
-
-
-
-
-
-
pF  
pF  
pF  
pF  
pF  
pF  
HI-507A  
HI-508A  
HI-509A  
Digital Input Capacitance, C  
A
Input to Output Capacitance, C  
DS(OFF)  
DIGITAL INPUT CHARACTERISTICS  
Input Low Threshold, TTL Drive, V  
Note 2  
Full  
Full  
Full  
-
4.0  
-
-
-
-
0.8  
-
-
4.0  
-
-
-
-
0.8  
-
V
V
AL  
Input High Threshold, V (Note 9)  
AH  
Note 2  
Input Leakage Current (High or Low), I  
Notes 2, 6  
1.0  
1.0  
µA  
A
7
HI-506A, HI-507A, HI-508A, HI-509A  
Electrical Specifications Supplies = +15V, -15V; V  
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V,  
AH AL  
REF  
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)  
-2, -8  
-5, -7  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MOS Drive, V , HI-506A/HI-507A  
MIN  
-
TYP  
MAX  
0.8  
-
MIN  
-
TYP  
MAX  
0.8  
-
UNITS  
V
V
= +10V  
= +10V  
25  
25  
-
-
-
-
V
V
AL  
REF  
REF  
MOS Drive, V , HI-506A/HI-507A  
AH  
6.0  
6.0  
ANALOG CHANNEL CHARACTERISTICS  
Analog Signal Range, V  
Note 2  
Full  
25  
-15  
-
-
+15  
1.5  
1.8  
-
-15  
-
-
+15  
1.8  
2.0  
-
V
IN  
On Resistance, r  
Notes 2, 3  
1.2  
1.5  
kΩ  
kΩ  
nA  
nA  
nA  
nA  
nA  
nA  
nA  
nA  
µA  
nA  
nA  
nA  
nA  
nA  
nA  
ON  
Full  
25  
-
1.5  
-
1.8  
Off Input Leakage Current, I  
Notes 2, 4  
Notes 2, 4  
-
0.03  
-
0.03  
S(OFF)  
Full  
25  
-
-
50  
-
-
50  
-
Off Output Leakage Current, I  
-
0.1  
-
-
0.1  
D(OFF)  
HI-506A  
HI-507A  
HI-508A  
HI-509A  
Full  
Full  
Full  
Full  
25  
-
-
300  
200  
200  
100  
-
-
-
300  
200  
200  
100  
-
-
-
-
-
-
-
-
-
-
-
-
-
I
With Input Overvoltage Applied  
Note 5  
-
4.0  
-
4.0  
D(OFF)  
Full  
25  
-
-
2.0  
-
-
-
-
On Channel Leakage Current, I  
Notes 2, 4  
-
0.1  
-
0.1  
-
D(ON)  
HI-506A  
HI-507A  
HI-508A  
HI-509A  
Full  
Full  
Full  
Full  
Full  
-
-
-
-
-
-
300  
200  
200  
100  
50  
-
-
-
-
-
-
300  
200  
200  
100  
50  
-
-
-
-
-
-
Differential Off Output Leakage Current, I  
(HI-507A, HI-509A Only)  
,
-
-
DIFF  
POWER SUPPLY CHARACTERISTICS  
Current, I+  
Current, I-  
Notes 2, 8  
Notes 2, 8  
Full  
Full  
Full  
-
-
-
0.5  
0.02  
7.5  
2.0  
1.0  
-
-
-
-
0.5  
0.02  
7.5  
2.0  
1.0  
-
mA  
mA  
mW  
Power Dissipation, P  
D
NOTES:  
o
2. 100% tested for Dash 8. Leakage currents not tested at -55 C.  
3. V = ±10V, I = +100µA.  
OUT  
OUT  
4. 10nA is the practical lower limit for high speed measurement in the production test environment.  
5. Analog Overvoltage = ±33V.  
o
6. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25 C.  
7. V = 0.8V, R = 1K, C = 15pF, V = 7V , f = 100kHz.  
EN  
L
L
S
RMS  
8. V , V = 0V or 4V.  
EN  
A
9. To drive from DTL/TTL Circuits, 1kΩ pull-up resistors to +5V supply are recommended.  
8
HI-506A, HI-507A, HI-508A, HI-509A  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
SUPPLY AH AL REF  
= Open,  
A
Unless Otherwise Specified  
100µA  
V
2
IN  
OUT  
V
2
V
r
=
IN  
ON  
100µA  
FIGURE 1A. TEST CIRCUIT  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
o
o
o
-55 C TO 125 C  
= +5V  
125 C  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
V
IN  
o
25 C  
o
-55 C  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
-10  
-8  
-6  
-4  
-2  
0
2
4
6
8
10  
ANALOG INPUT (V)  
SUPPLY VOLTAGE (±V)  
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE  
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY  
VOLTAGE  
FIGURE 1. ON RESISTANCE  
100nA  
10nA  
1nA  
OFF OUTPUT  
CURRENT  
+0.8V  
EN  
ON LEAKAGE  
CURRENT  
I
D(OFF)  
OUT  
I
D(ON)  
I
D(OFF)  
A
±
±10V  
10V  
OFF INPUT  
LEAKAGE CURRENT  
S(OFF)  
100pA  
10pA  
I
25  
50  
75  
100  
125  
o
TEMPERATURE ( C)  
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE  
FIGURE 2B. I  
TEST CIRCUIT (NOTE 10)  
D(OFF)  
9
HI-506A, HI-507A, HI-508A, HI-509A  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V = Open,  
AH AL REF  
A
SUPPLY  
Unless Otherwise Specified (Continued)  
OUT  
OUT  
I
A
A
S(OFF)  
I
D(ON)  
+0.8V  
EN  
EN  
A
A
1
0
±
±10V  
10V  
±
±10V  
10V  
4V  
FIGURE 2C. I  
S(OFF)  
TEST CIRCUIT (NOTE 10)  
FIGURE 2D. I  
TEST CIRCUIT (NOTE 10)  
D(On)  
NOTE:  
10. Two measurements per channel: ±10V and +10V. (Two measurements per device for I  
±10V and +10V.)  
D(OFF)  
FIGURE 2. LEAKAGE CURRENTS  
7
18  
15  
12  
9
6
5
ANALOG INPUT  
CURRENT (I  
)
IN  
4
3
2
1
0
I
I
D(OFF)  
A
A
IN  
6
±V  
IN  
OUTPUT OFF LEAKAGE  
CURRENT ID  
3
(OFF)  
0
15  
18  
21  
24  
27  
30  
33  
36  
ANALOG INPUT OVERVOLTAGE (±V)  
FIGURE 3A. ANALOG INPUT OVERVOLTAGE  
CHARACTERISTICS  
FIGURE 3B. TEST CIRCUIT  
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS  
±14  
±12  
±10  
±8  
o
-55 C  
o
25 C  
o
125 C  
±6  
A
±V  
IN  
±4  
±2  
0
0
2
4
6
8
10  
12  
14  
VOLTAGE ACROSS SWITCH (±V)  
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE  
FIGURE 4. ON CHANNEL CURRENT  
FIGURE 4B. TEST CIRCUIT  
10  
HI-506A, HI-507A, HI-508A, HI-509A  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
= Open,  
REF  
A
SUPPLY  
AH AL  
Unless Otherwise Specified (Continued)  
+15V/+10V  
+I  
8
6
4
2
0
SUPPLY  
A
V+  
±10V/±5V  
A
A
A
A
IN 1  
3
HI-506A†  
2
1
0
IN 2  
V
= ±15V  
SUPPLY  
THRU  
V
50Ω  
A
IN 7/IN 15  
V
= ±10V  
SUPPLY  
±
±
IN 8/IN 16  
10V/ 5V  
EN  
OUT  
V-  
+4V  
GND  
14  
10  
pF  
MΩ  
-I  
A
SUPPLY  
1K  
10K  
100K  
1M  
10M  
-15V/-10V  
TOGGLE FREQUENCY (Hz)  
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY  
†Similar connection for HI-507A/HI-508A/HI-509A  
FIGURE 5B. TEST CIRCUIT  
FIGURE 5. DYNAMIC SUPPLY CURRENT  
+15V  
900  
V
V
= OPEN FOR LOGIC HIGH LEVEL ≤ 6V  
= LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V  
REF  
REF  
V
V+  
IN 1  
800  
700  
600  
500  
400  
300  
REF  
±10V  
A
A
A
A
3
2
1
0
IN 2 THRU  
IN 7/IN 15  
V
50Ω  
A
HI-506A†  
±
10V  
IN 16  
EN  
OUT  
V-  
+4V  
GND  
50  
pF  
10  
kΩ  
3
4
5
6
7
8
9
10 11 12 13 14 15  
-15V  
LOGIC LEVEL (HIGH) (V)  
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)  
†Similar connection for HI-507A/HI-580A/HI-509A  
FIGURE 6B. TEST CIRCUIT  
V
INPUT  
A
2V/DIV.  
V
= 4.0V  
AH  
ADDRESS  
DRIVE (V )  
A
S
ON  
1
1
/
V
AH  
2
0V  
+10V  
OUTPUT  
5V/DIV.  
OUTPUT  
-10V  
10%  
S
ON  
16  
t
A
200ns/DIV.  
FIGURE 6C. MEASUREMENT POINTS  
FIGURE 6D. WAVEFORMS  
FIGURE 6. ACCESS TIME  
11  
HI-506A, HI-507A, HI-508A, HI-509A  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V = Open,  
AH AL REF  
A
SUPPLY  
Unless Otherwise Specified (Continued)  
A
A
3
2
HI-506A†  
IN 1  
+5V  
V
= 4.0V  
AH  
IN 2 THRU  
IN 7/IN 15  
IN 8/IN 16  
OUT  
V
50Ω  
A
A
A
1
0
ADDRESS  
DRIVE (V )  
A
0V  
V
OUT  
+4.0V  
EN  
OUTPUT  
GND  
50pF  
1kΩ  
50%  
50%  
t
OPEN  
†Similar connection for HI-507A/HI-508A/HI-509A  
FIGURE 7A. TEST CIRCUIT  
FIGURE 7B. MEASUREMENT POINTS  
V
INPUT  
A
2V/DIV.  
S
ON  
S
ON  
16  
1
OUTPUT  
0.5V/DIV.  
100ns/DIV.  
FIGURE 7C. WAVEFORMS  
FIGURE 7. BREAK-BEFORE-MAKE DELAY  
12  
HI-506A, HI-507A, HI-508A, HI-509A  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V = Open,  
AH AL REF  
A
SUPPLY  
Unless Otherwise Specified (Continued)  
A
A
3
2
HI-506A†  
+10V  
IN 1  
V
= 4.0V  
AH  
IN 2 THRU  
IN 7/IN 15  
ENABLE DRIVE  
(V )  
50%  
50%  
A
A
A
1
0
IN 8 /IN 16  
0V  
V
EN  
OUT  
OUT  
90%  
GND  
OUTPUT  
V
50pF  
50Ω  
1kΩ  
A
10%  
0V  
t
ON(EN)  
t
OFF(EN)  
†Similar connection for HI-507A//HI-508A/HI-509A  
FIGURE 8A. TEST CIRCUIT  
FIGURE 8B. MEASUREMENT POINTS  
ENABLE DRIVE  
2V/DIV.  
OUTPUT  
2V/DIV.  
ENABLED  
(S ON)  
DISABLED  
1
100ns/DIV.  
FIGURE 8C. WAVEFORMS  
FIGURE 8. ENABLE DELAYS  
13  
HI-506A, HI-507A, HI-508A, HI-509A  
Die Characteristics  
DIE DIMENSIONS:  
WORST CASE CURRENT DENSITY:  
5
2
159 mils x 83.9 mils  
1.4 x 10 A/cm  
METALLIZATION:  
TRANSISTOR COUNT:  
Type: CuAl  
485  
Thickness: 16kÅ ±2kÅ  
PROCESS:  
SUBSTRATE POTENTIAL (NOTE):  
CMOS-DI  
-V  
SUPPLY  
PASSIVATION:  
Silox: 12kÅ ±2kÅ  
Nitride: 3.5kÅ ±1kÅ  
NOTE: The substrate appears resistive to the -V  
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a  
SUPPLY  
conductor at -V  
potential.  
SUPPLY  
Metallization Mask Layouts  
HI-506A  
HI-507A  
NC  
V
A
A
V
A
(17)  
A
A
A
(17)  
A
1
EN  
(18)  
GND  
(12)  
EN  
(18)  
GND  
(12)  
2
3
REF  
0
1
2
REF  
(13)  
0
(14)  
(16) (15)  
(14) (13)  
(16) (15)  
IN 1  
(19)  
IN 9  
(11)  
IN 1B  
(11)  
IN 1A  
(19)  
IN 2B  
(10)  
IN 2A  
(20)  
IN 2  
(20)  
IN 10  
(10)  
IN 3  
(21)  
IN 11  
(9)  
IN 3A  
(21)  
IN 3B  
(9)  
IN 4A  
(22)  
IN 4B  
(8)  
IN 4  
(22)  
IN 12  
(8)  
IN 5  
(23)  
IN 13  
(7)  
IN 5A  
(23)  
IN 5B  
(7)  
IN 6  
(24)  
IN 14  
(6)  
IN 6A  
(24)  
IN 6B  
(6)  
IN 7  
(25)  
IN 15  
(5)  
IN 7A  
(25)  
IN 7B  
(5)  
IN 8  
(26)  
IN 16  
(4)  
IN 8A  
(26)  
IN 8B  
(4)  
V- (27)  
OUT (28)  
+V (1)  
NC (2)  
V- (27)  
OUT A (28)  
+V (1)  
OUT B(2)  
14  
HI-506A, HI-507A, HI-508A, HI-509A  
Die Characteristics  
DIE DIMENSIONS:  
WORST CASE CURRENT DENSITY:  
5
2
108 mils x 83 mils  
1.4 x 10 A/cm  
METALLIZATION:  
TRANSISTOR COUNT:  
Type: CuAl  
253  
Thickness: 16kÅ ±2kÅ  
PROCESS:  
SUBSTRATE POTENTIAL (NOTE):  
CMOS-DI  
-V  
SUPPLY  
PASSIVATION:  
Silox: 12kÅ ±2kÅ  
Nitride: 3.5kÅ ±1kÅ  
NOTE: The substrate appears resistive to the -V  
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a  
SUPPLY  
conductor at -V  
potential.  
SUPPLY  
Metallization Mask Layouts  
HI-508A  
HI-509A  
IN 6 IN 7 IN 8  
(11) (10) (9)  
OUT  
(8)  
IN 4 IN 3  
IN 3B IN 4B OUT B  
OUT A IN 4A IN 3A  
(8) (7) (6)  
(7)  
(6)  
(11) (10)  
(9)  
IN 5  
(12)  
IN 2  
(5)  
IN 2B  
(12)  
IN 2A  
(5)  
+V  
(13)  
IN 1  
(4)  
IN 1B  
(13)  
IN 1A  
(4)  
GND  
(14)  
-V  
(3)  
+V  
(14)  
-V  
(3)  
A
2
(15)  
A
A
GND  
(15)  
A
A
0
EN  
(2)  
EN  
(2)  
1
0
1
(16) (1)  
(16) (1)  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
15  

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