HI3-0507-5 [INTERSIL]
Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers; 单16和8 /差分8通道和4通道CMOS模拟多路复用器
| 型号： | HI3-0507-5 |
| 厂家： | 
Intersil |
| 描述： | Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers |
| 文件： | 总23页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-506, HI-507, HI-508, HI-509
Data Sheet
June 1999
File Number 3142.2
Single 16 and 8/Differential 8-Channel and
4-Channel CMOS Analog Multiplexers
Features
• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 180Ω
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V
• TTL/CMOS Compatible
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS
multiplexers each include an array of sixteen and eight
analog switches respectively, a digital decoder circuit for
channel selection, voltage reference for logic thresholds, and
an enable input for device selection when several
multiplexers are present. The Dielectric Isolation (DI)
process used in fabrication of these devices eliminates the
problem of latchup. DI also offers much lower substrate
leakage and parasitic capacitance than conventional
junction isolated CMOS (see Application Notes AN520 and
AN521).
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switching
• No Latch-Up
• Replaces DG506A/DG506AA and DG507A/DG507AA
• Replaces DG508A/DG508AA and DG509A/DG509AA
The switching threshold for each digital input is established by
an internal +5V reference, providing a guaranteed minimum
2.4V for logic “1” and maximum 0.8V for logic “0”. This allows
direct interface without pullup resistors to signals from most
logic families: CMOS, TTL, DTL and some PMOS. For
protection against transient overvoltage, the digital inputs
include a series 200Ω resistor and diode clamp to each
supply.
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Ordering Information
The HI-506 is a single 16-Channel, the HI-507 is an
8-Channel differential, the HI-508 is a single 8-Channel and
the HI-509 is a 4-Channel differential multiplexer.
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
28 Ld SOIC
HI9P0506-9
HI3-0506-5
HI4P0506-5
HI1-0506-5
HI1-0506-4
HI1-0506-2
HI4P0507-5
HI3-0507-5
HI1-0507-2
HI1-0508-5
HI3-0508-5
HI1-0508-4
HI1-0508-2
HI4P0508-5
HI9P0508-9
HI9P0508-5
HI9P0509-5
HI1-0509-4
HI1-0509-5
HI3-0509-5
HI4P0509-5
HI1-0509-2
-40 to 85
0 to 75
M28.3
If input overvoltages are present, the HI-546/HI-547/HI-548/
HI-549 multiplexers are recommended.
28 Ld PDIP
E28.6
N28.45
F28.6
F28.6
F28.6
N28.45
E28.6
F28.6
F16.3
E16.3
F16.3
F16.3
N20.35
M16.15
M16.15
M16.15
F16.3
F16.3
E16.3
N20.35
F16.3
0 to 75
28 Ld PLCC
28 Ld CERDIP
28 Ld CERDIP
0 to 75
-25 to 85
-55 to 125 28 Ld CERDIP
0 to 75
0 to 75
28 Ld PLCC
28 Ld PDIP
-55 to 125 28 Ld CERDIP
0 to 75
0 to 75
16 Ld CERDIP
16 Ld PDIP
-25 to 85
16 Ld CERDIP
-55 to 125 16 Ld CERDIP
0 to 75
-40 to 85
0 to 75
0 to 75
-25 to 85
0 to 75
0 to 75
0 to 75
20 Ld PLCC
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
20 Ld PLCC
-55 to 125 16 Ld CERDIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HI-506, HI-507, HI-508, HI-509
Pinouts
HI-506
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-507
(PDIP, CERDIP)
TOP VIEW
+V
1
2
3
4
5
6
7
8
9
28 OUT
27 -V
+V
1
2
3
4
5
6
7
8
9
28 OUT A
27 -V
SUPPLY
SUPPLY
NC
OUT B
SUPPLY
SUPPLY
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
26 IN 8A
25 IN 7A
24 IN 6A
23 IN 5A
22 IN 4A
21 IN 3A
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
20
20
IN 2A
IN 2
IN 10 10
IN 9 11
GND 12
NC 13
19 IN 1
IN 2B 10
IN 1B 11
GND 12
NC 13
19 IN 1A
18 ENABLE
18 ENABLE
17 ADDRESS A
16 ADDRESS A
15 ADDRESS A
17 ADDRESS A
16 ADDRESS A
15 ADDRESS A
0
1
2
0
1
2
ADDRESS A 14
NC 14
3
HI-506
(PLCC)
HI-507
(PLCC)
TOP VIEW
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
25
24
23
22
21
20
19
25
24
23
22
21
20
19
IN 15
IN 14
IN 13
IN 12
IN 11
5
6
7
8
9
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
5
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
6
7
8
9
IN 10 10
IN 9 11
IN 2B 10
IN 1B 11
12 13 14 15 16 17 18
12 13 14 15 16 17 18
2
HI-506, HI-507, HI-508, HI-509
Pinouts (Continued)
HI-508
HI-509
(PDIP, CERDIP, SOIC)
TOP VIEW
(PDIP, CERDIP, SOIC)
TOP VIEW
A
1
2
3
4
5
6
7
8
16 A
15 A
A
1
2
3
4
5
6
7
8
16 A
1
0
1
2
0
ENABLE
ENABLE
15 GND
14 +V
SUPPLY
-V
14 GND
13 +V
-V
SUPPLY
IN 1
SUPPLY
IN 1A
13 IN 1B
12 IN 2B
11 IN 3B
10 IN 4B
SUPPLY
IN 2
IN 3
IN 4
OUT
12 IN 5
11 IN 6
10 IN 7
IN 2A
IN 3A
IN 4A
9
IN 8
9
OUT B
OUT A
HI-508
(PLCC)
HI-509
(PLCC)
TOP VIEW
TOP VIEW
3
2
1
20 19
3
2
1
20 19
GND
+V
+V
18
17
18
17
-V
4
-V
4
SUPPLY
SUPPLY
SUPPLY
IN 1B
IN 1
NC
5
6
7
8
IN 1A
NC
5
6
7
8
SUPPLY
16 NC
16 NC
15 IN 2B
IN 3B
15 IN 5
IN 2
IN 3
IN 2A
IN 3A
IN 6
14
14
9
10 11 12 13
9
10 11 12 13
3
HI-506, HI-507, HI-508, HI-509
Truth Tables
HI-508
HI-506
A EN
0
A
A
A
0
EN
L
“ON” CHANNEL
A
A
A
“ON” CHANNEL
2
1
3
2
1
X
X
X
None
X
X
X
X
L
None
1
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
L
H
H
L
L
L
H
H
L
3
L
H
L
L
L
H
L
4
H
H
H
H
L
H
H
H
H
L
5
L
H
L
L
L
H
L
6
H
H
L
H
H
L
7
H
L
H
L
8
H
H
H
H
H
H
H
H
9
HI-509
L
L
H
L
10
11
12
13
14
15
16
A
A
EN
L
“ON” CHANNEL PAIR
1
0
L
H
H
L
X
X
None
L
H
L
L
L
L
H
L
H
1
2
3
4
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
HI-507
A
A
A
0
EN
L
“ON” CHANNEL
2
1
X
X
X
None
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
4
HI-506, HI-507, HI-508, HI-509
Functional Diagrams
HI-506
HI-507
IN 1
IN 2
IN 1A
OUT A
OUT B
OUT
IN 8A
IN 1B
DECODER/
DRIVER
IN 16
DECODER/
DRIVER
IN 8B
5V
REF
LEVEL
SHIFT
DIGITAL
INPUT
PROTECTION
5V
REF
LEVEL
SHIFT
†
† † † †
†
DIGITAL
INPUT
†
†
†
†
†
A
A
A
A
3
EN
PROTECTION
0
1
2
A
A
A
2
EN
0
1
HI-508
HI-509
IN 1
IN 2
IN 1A
OUT A
OUT B
OUT
IN 4A
IN 1B
DECODER/
DRIVER
IN 8
DECODER/
DRIVER
IN 4B
5V
REF
LEVEL
SHIFT
DIGITAL
INPUT
PROTECTION
5V
REF
LEVEL
SHIFT
†
†
†
†
†
DIGITAL
INPUT
†
†
†
†
A
A
A
2
EN
PROTECTION
0
1
A
A
EN
0
1
5
HI-506, HI-507, HI-508, HI-509
Schematic Diagrams
ADDRESS DECODER
V+
P
P
P
P
P
P
P
N
TO P-CHANNEL
DEVICE OF
THE SWITCH
N
N
A
OR A
0
0
N
N
N
N
A
OR A
1
1
TO N-CHANNEL
DEVICE OF
THE SWITCH
A
OR A
2
2
A
OR A
3
3
ENABLE
DELETE A OR A INPUT FOR HI-507, HI-508, HI-509
3
3
DELETE A OR A INPUT FOR HI-509
2
2
V-
ADDRESS INPUT BUFFER LEVEL SHIFTER
V+
P3
P1
N1
P5
A
A
P4
V+
D1
P7
N7
P6
N6
P8
N8
P9
P10
N10
V
V
L
R
N9
D2
P2
N4
200Ω
N5
N2
V-
N3
A
IN
ALL N-CHANNEL BODIES TO V-
ALL P-CHANNEL BODIES TO V+
UNLESS OTHERWISE INDICATED
V-
TTL REFERENCE CIRCUIT
MULTIPLEX SWITCH
N18
V+
FROM DECODE
P15
Q2P Q3P Q4P
Q1P
Q5N
Q6N
V+
N17
N19
Q8N
IN
OUT
R2
16.8K
P17
V
L
N12
Q7P
V
Q11P
V-
D3
Q10N
R3
6.8K
R
Q9P
P18
N13
N14 N15
P16
Q12N
FROM DECODE
V-
GND
6
HI-506, HI-507, HI-508, HI-509
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
16 Ld CERDIP Package. . . . . . . . . . . .
16 Ld SOIC Package . . . . . . . . . . . . . .
16 Ld PDIP Package . . . . . . . . . . . . . .
20 Ld PLCC Package. . . . . . . . . . . . . .
28 Ld CERDIP Package. . . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . .
28 Ld PLCC Package. . . . . . . . . . . . . .
Maximum Junction Temperature
85
115
100
80
55
60
32
N/A
N/A
N/A
18
N/A
N/A
N/A
Digital Input Voltage (V , V ) . . . . . (V-) -4V to (V+) +4V or 20mA,
EN
A
Whichever Occurs First
Analog Signal (V , V , Note 2) . . . . . . . . . . (V-) -2V to (V+) +2V
IN OUT
Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA
70
70
Operating Conditions
o
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
Temperature Ranges
HI-506/507/508/509-2 . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-506/508/509-4 . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C
HI-506/507/508/509-5 . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
o
o
o
o
o
o
o
o
(SOIC and PLCC - Lead Tips Only)
o
o
HI-506/508-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage
condition is anticipated (analog input exceeds either power supply voltage), the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are
recommended.
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V; V (Logic Level Low) = 0.8V,
AH
AL
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section
-2
-4, -5, -9
TYP
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Access Time, t
25
Full
25
-
-
250
-
500
-
-
250
-
-
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
dB
pF
A
1000
1000
Break-Before-Make Delay, t
25
-
80
250
-
-
25
-
80
250
-
-
OPEN
Enable Delay (ON), t
25
500
-
ON(EN)
Full
25
-
1000
-
1000
Enable Delay (OFF), t
-
250
-
500
-
250
-
-
OFF(EN)
Full
25
-
1000
-
1000
Settling Time, t
(HI-506 and HI-507)
To 0.1%
To 0.01%
To 0.1%
To 0.01%
Note 6
-
1.2
2.4
360
600
68
10
-
-
-
-
-
-
-
1.2
2.4
360
600
68
10
-
-
-
-
-
-
S
25
-
-
Settling Time, t
(HI-508 and HI-509)
25
-
-
S
25
-
-
Off Isolation
25
50
-
50
-
Channel Input Capacitance, C
S(OFF)
25
Channel Output Capacitance, C
HI-506
D(OFF)
25
25
25
25
25
25
-
-
-
-
-
-
52
30
-
-
-
-
-
-
-
-
-
-
-
-
52
30
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
HI-507
HI-508
HI-509
17
17
12
12
Digital Input Capacitance, C
6
6
A
Input to Output Capacitance, C
0.08
0.08
DS(OFF)
7
HI-506, HI-507, HI-508, HI-509
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V; V (Logic Level Low) = 0.8V,
AH
AL
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)
-2
-4, -5, -9
TYP
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
Full
Full
Full
-
2.4
-
-
-
-
0.8
-
-
2.4
-
-
-
-
0.8
-
V
V
Input High Threshold, V
AH
Input Leakage Current
(High or Low), I
Note 5
1.0
1.0
µA
A
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
Full
25
-15
-
180
5
+15
-15
-
180
5
+15
V
IN
On Resistance, r
Note 3
Note 4
Note 4
-
-
-
-
-
300
-
-
-
-
-
400
Ω
ON
∆r , (Any Two Channels)
25
-
-
-
-
%
ON
Off Input Leakage Current, I
25
0.03
-
0.03
-
nA
nA
nA
S(OFF)
Full
25
50
-
50
-
Off Output Leakage Current,
0.3
0.3
I
)
D(OFF
HI-506
HI-507
HI-508
HI-509
Full
Full
Full
Full
25
-
-
-
-
-
-
-
-
-
-
-
300
200
200
100
-
-
-
-
-
-
-
-
-
-
-
-
300
200
200
100
-
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
-
-
-
-
-
-
On Channel Leakage Current, I
Note 4
0.3
0.3
D(ON)
HI-506
HI-507
HI-508
HI-509
Full
Full
Full
Full
Full
-
-
-
-
-
300
200
200
100
50
-
-
-
-
-
300
200
200
100
50
Differential Off Output Leakage Current, I
(HI-507, HI-509 Only)
DIFF
POWER SUPPLY CHARACTERISTICS
Current, I+
HI-506/HI-507
Note 7
Note 7
Full
Full
-
-
1.5
1.5
3.0
2.4
-
-
1.5
1.5
3.0
2.4
mA
mA
HI-508/HI-509
Current, I-
HI-506/HI-507
Note 7
Note 7
Full
Full
-
-
0.4
0.4
1.0
1.0
-
-
0.4
0.4
1.0
1.0
mA
mA
HI-508/HI-509
Power Dissipation, P
HI-506/HI-507
D
Full
Full
-
-
-
-
60
51
-
-
-
-
60
51
mW
mW
HI-508/HI-509
NOTES:
3. V
OUT
= ±10V, I
= +1mA.
OUT
4. 10nA is the practical lower limit for high speed measurement in the production test environment.
o
5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25 C.
6. V
= 0.8V, R = 1K, C = 15pF, V = 7V
, f = 100kHz.
RMS
EN
L
L
S
7. V , V = 0V or 2.4V.
EN
A
8
HI-506, HI-507, HI-508, HI-509
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified
A
SUPPLY AH AL
1mA
V
2
IN
OUT
r
V
2
V
=
IN
ON
1mA
FIGURE 1A. TEST CIRCUIT
400
300
200
100
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
o
o
-55 C TO 125 C
= 0V
V
IN
o
125 C
o
25 C
o
-55 C
0.6
-15
-10
-5
0
5
10
15
7
8
9
10
11
12
13
14
15
ANALOG INPUT (V)
SUPPLY VOLTAGE (±V)
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY
VOLTAGE
FIGURE 1. ON RESISTANCE
100nA
10nA
1nA
OFF OUTPUT
LEAKAGE CURRENT
I
D(OFF)
0.8V
EN
I
D(ON)
OUT
A
I
D(OFF)
±10V
+10V
OFF INPUT
LEAKAGE CURRENT
S(OFF)
100pA
10pA
I
25
50
75
100
125
o
TEMPERATURE ( C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. I
TEST CIRCUIT (NOTE 8)
D(OFF)
9
HI-506, HI-507, HI-508, HI-509
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified (Continued)
A
SUPPLY AH AL
OUT
OUT
0.8V
I
A
I
A
S(OFF)
D(ON)
EN
EN
A
A
1
0
±10V
+10V
±10V
+10V
2.4V
FIGURE 2C. I
TEST CIRCUIT (NOTE 8)
FIGURE 2D. I TEST CIRCUIT (NOTE 8)
D(ON)
S(OFF)
FIGURE 2. LEAKAGE CURRENTS
NOTE:
8. Two measurements per channel: ±10V and +10V. (Two measurements per device for I
±10V and +10V)
D(OFF)
70
60
o
-55 C
50
o
25 C
40
o
125 C
30
20
10
0
A
±V
IN
0
2
4
6
8
10
12
14
16
VOLTAGE ACROSS SWITCH (±V)
FIGURE 3A. ON CHANNEL CURRENT vs VOLTAGE
FIGURE 3. ON CHANNEL CURRENT
FIGURE 3B. TEST CIRCUIT
+15V/+10V
+I
8
6
4
2
0
SUPPLY
A
V
= ±15V
SUPPLY
V+
±10V/±5V
+10V/+5V
A
A
A
A
IN 1
3
2
1
0
HI-506†
IN 2
THRU
V
50Ω
A
IN 7/15
IN 8/16
EN
OUT
V-
3.5V
GND
14
10
HIGH = 3.5V
LOW = 0V
V
= ±10V
SUPPLY
1M
pF
MΩ
V
A
50% DUTY CYCLE
-I
A
SUPPLY
1K
10K
100K
10M
†Similar connection for HI-507/HI-508/
HI-509
-15V/-10V
TOGGLE FREQUENCY (Hz)
FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY
FIGURE 4. DYNAMIC SUPPLY CURRENT
FIGURE 4B. TEST CIRCUIT
10
HI-506, HI-507, HI-508, HI-509
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified (Continued)
AH AL
A
SUPPLY
+15V
V+
600
400
200
0
±10V
A
A
A
A
IN 1
3
2
1
0
IN 2 THRU
IN 7/15
V
50Ω
A
HI-506†
+10V
IN 16
EN
OUT
V-
3.5V
GND
50
pF
10
kΩ
-15V
†Similar connection for HI-507/HI-508/
2
3
4
5
13
14
15
HI-509
LOGIC LEVEL (HIGH) (V)
FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH)
FIGURE 5B. TEST CIRCUIT
3.5V
ADDRESS
V
INPUT
DRIVE (V )
A
A
2V/DIV.
50%
0V
S
ON
1
+10V
OUTPUT
10%
OUTPUT
5V/DIV.
-10V
t
A
S
ON
16
200ns/DIV.
FIGURE 5C. MEASUREMENT POINTS
FIGURE 5D. WAVEFORMS
FIGURE 5. ACCESS TIME
+15V
V+
A
A
3
+5V
HI-506†
IN 1
2
IN 2 THRU
IN 7/IN 15
V
50Ω
A
A
A
1
IN 8 /16
0
V
OUT
3.5V
EN
OUT
V-
GND
50pF
200Ω
-15V
†Similar connection for HI-507/HI-508/HI-509
FIGURE 6A. TEST CIRCUIT
11
HI-506, HI-507, HI-508, HI-509
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified (Continued)
A
SUPPLY AH AL
3.5V
V
INPUT
A
2V/DIV.
S
ON
S
ON
16
1
ADDRESS
DRIVE (V )
A
0V
OUTPUT
1V/DIV.
OUTPUT
50%
50%
t
OPEN
100ns/DIV.
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6C. WAVEFORMS
FIGURE 6. BREAK-BEFORE-MAKE DELAY
+15V
V+
A
A
3
HI-506†
+10V
IN 1
2
IN 2 THRU
IN 7/IN 15
A
A
1
IN 8 /16
0
V
OUT
EN
OUT
V-
GND
V
50pF
50Ω
200Ω
A
-15V
†Similar connection for HI-507/HI-508/HI-509
FIGURE 7A. TEST CIRCUIT
3.5V
ENABLE
DRIVE
2V/DIV.
ENABLE DRIVE (V )
A
50%
50%
0V
OUTPUT
90%
ENABLED
10%
(S ON)
DISABLED
1
0V
OUTPUT
2V/DIV.
t
ON(EN)
t
OFF(EN)
100ns/DIV
FIGURE 7B. MEASUREMENT POINTS
FIGURE 7C. WAVEFORMS
FIGURE 7. ENABLE DELAYS
12
HI-506, HI-507, HI-508, HI-509
o
Typical Performance Curves T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified
AH AL
A
SUPPLY
4
3
2
1
0
100
80
60
40
20
0
R
= 1K
L
R
= 10M
L
V
C
V
= 0V
EN
= 28pF
LOAD
= 7V
S
RMS
4
5
6
7
6
8
10
12
14
16
18
20
10
10
10
FREQUENCY (Hz)
10
POWER SUPPLY VOLTAGE (±V)
FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE
FIGURE 9. OFF ISOLATION vs FREQUENCY
3
2
1
0
3
2
V
= 2.4V
EN
EN = 5V
EN = 0V
V
= 0V
EN
1
0
-55
-55
-35
-15
-5
25
45
65
85
105
125
-35
-15
-5
25
45
65
85
105 125
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 10A. HI-506/HI-507
FIGURE 10B. HI-508/HI-509
FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE
13
HI-506, HI-507, HI-508, HI-509
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
129 mils x 82 mils
Type: Nitride/Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.4 x 10 A/cm
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-V
SUPPLY
421
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -V
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
SUPPLY
conductor at -V
potential.
SUPPLY
Metallization Mask Layout
HI-506
HI-507
EN
A
A
A
A
GND
EN
A
A
A NC
2
GND
0
1
2
3
0
1
IN 9
IN 1B
IN 2B
IN 3B
IN 1
IN 2
IN 1A
IN 2A
IN 10
IN 11
IN 3
IN 4
IN 5
IN 6
IN 7
IN 3A
IN 4A
IN 5A
IN 6A
IN 7A
IN 12
IN 13
IN 4B
IN 5B
IN 14
IN 15
IN 6B
IN 7B
IN 16
IN 8B
IN 8
IN 8A
NC
-V
+V
OUT
-V OUT A
+V OUT B
14
HI-506, HI-507, HI-508, HI-509
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
81.9 mils x 90.2 mils
Type: Nitride/Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.4 x 10 A/cm
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-V
SUPPLY
234
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -V
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
SUPPLY
conductor at -V
potential.
SUPPLY
Metallization Mask Layout
HI-508
HI-509
A
A
A
2
EN
GND
A
A
1
EN
GND
0
1
0
+V
+V
SUP
-V
-V
SUP
SUP
SUP
IN 5
IN 6
IN 1B
IN 2B
IN 1
IN 2
IN 1A
IN 2A
IN 3
IN 3A
IN 7
IN 3B
IN 4 OUT
IN 8
IN 4A OUT A
OUT B IN 4B
15
HI-506, HI-507, HI-508, HI-509
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C A B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
16
HI-506, HI-507, HI-508, HI-509
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
N
E1
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
A2
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
A
-C-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
35.1
5
eB
0.010 (0.25) M
C
B S
D1
E
0.13
15.24
12.32
5
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.700
0.200
-
17.78
5.08
7
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
28
28
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
17
HI-506, HI-507, HI-508, HI-509
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
18
HI-506, HI-507, HI-508, HI-509
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
19
HI-506, HI-507, HI-508, HI-509
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N20.35 (JEDEC MS-018AA ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
2.29
9.78
8.89
3.59
9.78
8.89
3.59
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.385
0.350
0.141
0.385
0.350
0.141
0.180
0.120
0.395
0.356
0.169
0.395
0.356
0.169
-
3.04
-
-
D2/E2
D2/E2
10.03
9.04
C
L
D1
D2
E
3
E1 E
4.29
4, 5
-
10.03
9.04
VIEW “A”
E1
E2
N
3
4.29
4, 5
6
0.020 (0.51)
MIN
20
20
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controllingdimension:INCH. Convertedmillimeterdimensionsare
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
20
HI-506, HI-507, HI-508, HI-509
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.485
0.450
0.191
0.485
0.450
0.191
0.180
0.120
0.495
0.456
0.219
0.495
0.456
0.219
-
2.29
3.04
-
-
D2/E2
D2/E2
12.32
11.43
4.86
12.57
11.58
5.56
C
L
D1
D2
E
3
E1 E
4, 5
-
12.32
11.43
4.86
12.57
11.58
5.56
VIEW “A”
E1
E2
N
3
4, 5
6
0.020 (0.51)
MIN
28
28
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
21
HI-506, HI-507, HI-508, HI-509
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
22
HI-506, HI-507, HI-508, HI-509
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.490
0.610
MIN
-
MAX
5.92
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
1.65
-
1.14
4
BASE
PLANE
Q
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
37.85
15.49
5
S1
b2
eA
A A
e
E
0.500
12.70
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
28
28
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
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TEL: (407) 724-7000
FAX: (407) 724-7240
23
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