HFA1212_04 [INTERSIL]
Dual 350MHz, Low Power Closed Loop Buffer Amplifier; 350MHz的双通道，低功耗闭环缓冲放大器
| 型号： | HFA1212_04 |
| 厂家： | 
Intersil |
| 描述： | Dual 350MHz, Low Power Closed Loop Buffer Amplifier |
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1212
®
J uly 2004
FN3607.6
Dual 350MHz, Low Power Clos ed Loop
Buffer Amplifier
Features
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
The HFA1212 is a dual closed loop Buffer featuring user
programmable gain and high speed performance.
Manufactured on Intersil’s proprietary complementary
bipolar UHF-1 process, these devices offer wide -3dB
bandwidth of 350MHz, very fast slew rate, excellent gain
flatness and high output current.
• Wide -3dB Bandwidth (A = +2) . . . . . . . . . . . . . 350MHz
V
• Very Fast Slew Rate (A = -1) . . . . . . . . . . . . . . 1100V/µs
V
• Low Supply Current . . . . . . . . . . . . . . . . . . . . 6mA/Buffer
• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . 60mA
• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via
connections to the inputs, as described in the “Application
Information” section. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns
• Standard Operational Amplifier Pinout
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
Applications
• High Resolution Monitors
• Professional Video Processing
• Medical Imaging
Part # Information
• Video Digitizing Boards/Systems
• RF/IF Processors
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
8 Ld SOIC
• Battery Powered Communications
• Flash Converter Drivers
• High Speed Pulse Amplifiers
HFA1212IB
(H1212I)
-40 to 85
M8.15
Pinout
HFA1212 (SOIC)
TOP VIEW
OUT1
-IN1
+IN1
V-
1
2
3
4
8
7
6
5
V+
-
+
-
OUT2
-IN2
+IN2
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004. All Rights Reserved
1
HFA1212
Absolute Maximum Rating
Thermal Information
o
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Output Current (Note 1) . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
SUPPLY
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
o
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . .175 C
o
ESD Rating
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 30mA for maximum reliability.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified.
SUPPLY
V
L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage
MIN
TYP
MAX
UNITS
A
A
B
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
C
C
A
A
B
B
25
Full
Full
25
-
2
3
10
15
70
15
30
-
mV
mV
-
o
Average Output Offset Voltage Drift
-
22
-
µV/ C
Channel-to-Channel Output Offset
Voltage Mismatch
-
mV
mV
dB
dB
dB
dB
dB
dB
µA
µA
Full
25
-
42
40
40
45
43
43
-
-
Common-Mode Rejection Ratio
∆V
∆V
∆V
= ±1.8V
= ±1.8V
= ±1.2V
45
44
45
49
48
48
1
CM
CM
CM
85
-
-40
25
-
Power Supply Rejection Ratio
∆V = ±1.8V
PS
-
∆V = ±1.8V
PS
85
-
∆V = ±1.2V
PS
-40
25
-
Input Bias Current
15
25
80
15
25
1
Full
Full
25
-
3
o
Input Bias Current Drift
-
30
-
nA/ C
Channel-to-Channel Input Bias Current
Mismatch
-
µA
µA
Full
25
-
-
Input Bias Current Power Supply Sensitivity
Input Resistance
∆V = ±1.25V
PS
-
0.5
-
µA/V
µA/V
MΩ
MΩ
MΩ
Ω
Full
25
-
3
∆V
∆V
∆V
= ±1.8V
= ±1.8V
= ±1.2V
0.8
0.5
0.5
-
1.1
1.4
1.3
350
2
-
CM
CM
CM
85
-
-40
25
-
Inverting Input Resistance
Input Capacitance
-
25
-
-
pF
Input Voltage Common Mode Range
(Implied by V CMRR and +R tests)
IO IN
25, 85
-40
25
±1.8
±1.2
-
±2.4
±1.7
7
-
V
-
V
Input Noise Voltage Density (Note 4)
Input Noise Current Density (Note 4)
f = 100kHz
f = 100kHz
-
nV/√Hz
pA/√Hz
25
-
3.6
-
2
HFA1212
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified. (Continued)
SUPPLY
V
L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
UNITS
TRANSFER CHARACTERISTICS
Gain (V = -1V to +1V)
IN
A
A
A
A
A
A
= -1
= +1
= +2
= -1
= +1
= +2
A
A
A
A
A
A
A
A
A
A
A
A
25
Full
25
-0.98
0.996
-1.02
-1.025
1.02
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V
V
V
V
V
V
0.975
1.000
0.98
0.992
Full
25
0.975
0.993
1.025
2.04
1.96
1.988
Full
25
1.95
1.990
2.05
Channel-to-Channel Gain Mismatch
-
-
-
-
-
-
-
-
-
-
-
-
±0.02
±0.025
±0.025
±0.025
±0.04
±0.05
Full
25
Full
25
Full
AC CHARACTERISTICS
-3dB Bandwidth
A
A
A
A
A
A
A
A
= -1
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
300
240
350
165
150
125
±0.03
±0.04
-65
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
V
V
V
V
V
V
V
(V
= 0.2V
, Note 4)
P-P
OUT
= +1, +R = 620Ω
S
= +2
= -1
Full Power Bandwidth
(V
V
= 5V
= 4V
at A = +2 or -1,
at A = +1, Note 4)
V
OUT
OUT
P-P
P-P
V
= +1, +R = 620Ω
S
= +2
Gain Flatness
(V = 0.2V
= +2, To 25MHz
= +2, To 50MHz
, Note 4)
P-P
OUT
dB
Crosstalk
(All Channels Hostile, Note 4)
5MHz
dB
10MHz
-60
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
(Note 4)
A
A
= -1
A
A
A
A
B
B
B
B
B
B
B
25
Full
25, 85
-40
25
±3.0
±3.2
±3.0
55
-
-
-
-
-
-
-
-
-
-
-
V
V
V
±2.8
V
Output Current
(Note 4)
= -1, R = 50Ω
50
28
-
mA
mA
mA
Ω
L
42
Output Short Circuit Current
DC Closed Loop Output Impedance
Second Harmonic Distortion
100
0.2
-60
-50
-60
-50
-65
A
= +2
25
-
V
10MHz
20MHz
10MHz
20MHz
25
-
dBc
dBc
dBc
dBc
dB
(A = +2, V
= 2V , Note 4)
V
OUT P-P
25
-
Third Harmonic Distortion
(A = +2, V = 2V , Note 4)
25
-
V
OUT
P-P
25
-
Reverse Isolation (S , Note 4)
12
30MHz, A = +2
25
-
V
TRANSIENT RESPONSE A = +2, Unless Otherwise Specified
V
Rise and Fall Times
(V = 0.5V
Rise Time
Fall Time
B
B
25
25
-
-
1.0
1.1
-
-
ns
ns
)
P-P
OUT
3
HFA1212
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified. (Continued)
SUPPLY
V
L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
4
MAX
UNITS
%
Overshoot
+OS
-OS
B
B
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(V
= 0.5V
, V = 1ns, Note 5)
t
OUT
P-P IN RISE
13
%
Slew Rate
A
= -1
+SR
-SR
+SR
-SR
+SR
-SR
2000
1150
1100
850
1300
900
24
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
ns
V
(V
V
= 5V
= 4V
at A = +2 or -1,
V
OUT
OUT
P-P
P-P
at A = +1)
V
A
= +1,
V
+R = 620Ω
S
A
= +2
V
Settling Time
(V = +2V to 0V Step, Note 4)
To 0.1%
To 0.05%
To 0.02%
OUT
37
ns
60
ns
Overdrive Recovery Time
V
= ±2V
8.5
ns
IN
VIDEO CHARACTERISTICS
Differential Gain (f = 3.58MHz, A = +2)
R
R
= 150Ω
= 150Ω
B
B
25
25
-
-
0.025
0.03
-
-
%
V
L
Differential Phase (f = 3.58MHz, A = +2)
V
Degrees
L
POWER SUPPLY CHARACTERISTICS
Power Supply Range
C
A
A
25
25
±4.5
-
±5.5
6.1
V
Power Supply Current
-
-
5.9
6.1
mA/Op Amp
mA/Op Amp
Full
6.3
NOTE:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
5. Negative overshoot dominates for output signal swings below GND (e.g. 0.5V
), yielding a higher overshoot limit compared to the
P-P
V
= 0V to 0.5V condition. See the “Application Information” section for details.
OUT
+2 or -1 (see “Unity Gain Considerations” for discussion of
parasitic impact on unity gain performance).
Application Information
HFA1212 Advantages
The HFA1212’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
The HFA1212 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
Implementing a dual, gain of 2, cable driver with this IC
eliminates the four gain setting resistors, which frees up
board space for termination resistors.
Clos ed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2, with
gain selection accomplished via connections to the ±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.
Like most newer high performance amplifiers, the HFA1212 is
a current feedback amplifier (CFA). CFAs offer high bandwidth
and slew rate at low supply currents, but can be difficult to use
because of their sensitivity to feedback capacitance and
parasitics on the inverting input (summing node). The HFA1212
eliminates these concerns by bringing the gain setting resistors
on-chip. This yields the optimum placement and value of the
feedback resistor, while minimizing feedback and summing
node parasitics. Because there is no access to the summing
node, the PCB parasitics do not impact performance at gains of
The table below summarizes these connections:
CONNECTIONS
GAIN
(A
)
+INPUT
50Ω to GND
Input
-INPUT
Input
CL
-1
+1
+2
NC (Floating)
GND
Input
4
HFA1212
Unity Gain Cons iderations
PC Board Layout
Unity gain selection is accomplished by floating the -Input of
the HFA1212. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Table 1 lists five alternate methods for configuring the
HFA1212 as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth decreases from 430MHz to 280MHz, but
excellent gain flatness is the benefit. A drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R ) in series with the output
S
prior to the capacitance.
Figure 1 details starting points for the selection of this
Another straightforward approach is to add a 620W resistor
in series with the amplifier’s positive input. This resistor and
the HFA1212 input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration was employed to obtain the data sheet
AC and transient parameters for a gain of +1.
resistor. The points on the curve indicate the R and C
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
S
L
Puls e Overs hoot
R
and C form a low pass network at the output, thus
L
S
limiting system bandwidth well below the amplifier bandwidth
The HFA1212 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased overshoot on the negative portion
of the output waveform (see Figure 6, Figure 9, and Figure
12). This overshoot isn’t present for small bipolar signals
(see Figure 4, Figure 7, and Figure 10) or large positive
signals (see Figure 5, Figure 8 and Figure 11).
of 350MHz. By decreasing R as C increases (as illustrated
S
L
in the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS
IMPLEMENTATIONS
PEAKING
(dB)
BW
±0.1dB GAIN
APPROACH
(MHz) FLATNESS (MHz)
Remove -IN Pin
4.5
0
430
220
215
21
27
15
+R = 620Ω
S
+R = 620Ω and
0.5
S
Remove -IN Pin
Short +IN to -IN (e.g.,
Pins 2 and 3)
0.6
0.7
280
290
70
40
100pF Capacitor
Between +IN and -IN
5
HFA1212
50
40
30
20
10
0
50Ω
OUT
1
2
3
4
8
7
6
5
+5V
10µF
R
1
(NOTE)
0.1µF
−
+
IN
GND
A
= +1
50Ω
V
GND
A
= +2
150
V
−5V
10µF
∞ (A = +1)
=
or 0Ω (A = +2)
NOTE: R
V
1
0.1µF
V
0
100
200
300
400
50
250
350
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
Evaluation Board
The performance of the HFA1212 may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the con-
nections open.
2. a. For A = +1 evaluation, remove the gain setting
V
resistors (R ), and leave pins 2 and 6 floating.
1
b. For A = +2, replace the gain setting resistors (R ) with
V
1
0Ω resistors to GND.
3. Replace the 0Ω series output resistors with 50Ω.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
NOTE: Note: The SOIC version may be evaluated in the DIP board
by using a SOIC-to-DIP adapter such as Aries Electronics Part
Number 08-350000-10.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
FIGURE 3A. TOP LAYOUT
6
HFA1212
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
SUPPLY
A
L
200
2.0
1.5
1.0
0.5
A
= +2
V
A = +2
V
150
100
50
0
0
-0.5
-1.0
-1.5
-2.0
-50
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
2.0
1.5
1.0
0.5
0
200
A
= +1
V
A
= +2
V
150
100
50
0
-50
-100
-150
-0.5
-1.0
-1.5
-200
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
2.0
2.0
1.5
1.0
0.5
0
A
= +1
A
= +1
V
V
1.5
1.0
0.5
0
-0.5
-0.5
-1.0
-1.5
-2.0
-1.0
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
7
HFA1212
o
Typical Performance Curves (Continued) V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
SUPPLY
A
L
200
2.0
1.5
1.0
0.5
0
A
= −1
A
= -1
V
V
150
100
50
0
-0.5
-1.0
-1.5
-2.0
-50
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE
FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE
2.0
1.5
1.0
0.5
0
6
3
A
= -1
V
A
= +2
V
GAIN
0
-3
-6
-9
A
= +1
V
A
= -1
V
PHASE
0
-90
-180
-0.5
-1.0
-1.5
A
= +1
V
V
= 200mV
OUT
P-P
-270
-360
A
= +2
V
+R = 620Ω (+1)
S
+R = 0Ω (-1, +2)
S
1
10
FREQUENCY (MHz)
100
600
-2.0
TIME (5ns/DIV.)
FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 13. FREQUENCY RESPONSE
6
3
0.7
V
= 200mV
P-P
OUT
0.6
0.5
0.4
0.3
0.2
0.1
0
+R = 620Ω (+1)
S
+R = 0Ω (-1, +2)
0
S
-3
-6
A
A
A
= -1
= +2
= +1
V
V
V
A
= +2
-9
V
V
V
= 4V
= 5V
(+1)
OUT
OUT
P-P
-0.1
-0.2
-0.3
(-1, +2)
P-P
A
= -1
A
= +1
V
V
+R = 620Ω (+1)
S
1
10
FREQUENCY (MHz)
100
1
10
100
300
FREQUENCY (MHz)
FIGURE 14. FULL POWER BANDWIDTH
FIGURE 15. GAIN FLATNESS
8
HFA1212
o
Typical Performance Curves (Continued) V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
SUPPLY
A
L
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
A
= +2
V
R
= ∞
L
-40
-50
-60
-70
A = -1
V
R = 100Ω
L
A
= +1
V
-80
-90
-80
-90
A
= +2
V
-100
-100
-110
-110
0.3
1
10
FREQUENCY (MHz)
100
0.3
1
10
100
500
FREQUENCY (MHz)
FIGURE 16. REVERSE ISOLATION
FIGURE 17. ALL HOSTILE CROSSTALK
-40
-45
-50
-55
-60
-65
-70
-40
-45
20MHz
10MHz
-50
-55
-60
-65
-70
20MHz
10MHz
-10
-5
0
5
10
15
-10
-5
0
5
10
15
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 18. 2nd HARMONIC DISTORTION vs P
FIGURE 19. 3rd HARMONIC DISTORTION vs P
OUT
OUT
20
16
12
8
20
16
12
8
A
= +1
0.10
0.05
0
V
-0.05
-0.10
E
NI
4
4
I
NI
0
0
13
33
53
73
93
113 133 153 173
0.1
1
10
100
TIME (ns)
FREQUENCY (kHz)
FIGURE 20. SETTLING RESPONSE
FIGURE 21. INPUT NOISE CHARACTERISTICS
9
HFA1212
o
Typical Performance Curves (Continued) V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
A L
SUPPLY
3.6
A
= -1
|-V
(R = 100Ω)
| (R = 100Ω)
OUT
V
L
3.5
+V
OUT
L
3.4
3.3
3.2
3.1
|-V
| (R = 50Ω)
OUT
L
+V
(R = 50Ω)
L
OUT
3.0
2.9
2.8
2.7
2.6
-50
-25
0
25
50
75
100
125
o
TEMPERATURE ( C)
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
Die Characteris tics
DIE DIMENSIONS:
69 mils x 92 mils x 19 mils
1750µm x 2330µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PASSIVATION:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
TRANSISTOR COUNT:
180
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
10
HFA1212
Metallization Mas k Layout
HFA1212
OUT1
-IN1
NC
V+
NC
OUT2
+IN1
NC
NC
-IN2
NC
V-
+IN2
NC
11
HFA1212
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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