HFA1145IPZ [INTERSIL]
330MHz, Low Power, Current Feedback Video Operational Amplifier with Output Disable; 330MHz的低功耗与输出禁用电流反馈型视频运算放大器
| 型号： | HFA1145IPZ |
| 厂家： | 
Intersil |
| 描述： | 330MHz, Low Power, Current Feedback Video Operational Amplifier with Output Disable |
| 文件： | 总13页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1145
®
Data Sheet
June 1, 2006
FN3955.5
330MHz, Low Power, Current Feedback
Video Operational Amplifier with Output
Disable
Features
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 5.8mA
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 330MHz
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1000V/μs
• Gain Flatness (to 75MHz) . . . . . . . . . . . . . . . . . . ±0.1dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Output Enable/Disable Time . . . . . . . . . . . . . 180ns/35ns
• Pin Compatible Upgrade for CLC410
The HFA1145 is a high speed, low power current feedback
amplifier built with Intersil’s proprietary complementary
bipolar UHF-1 process.
This amplifier features a TTL/CMOS compatible disable
control, pin 8, which when pulled low reduces the supply
current and forces the output into a high impedance state.
This allows easy implementation of simple, low power video
switching and routing systems. Component and composite
video systems also benefit from this op amp’s excellent gain
flatness, and good differential gain and phase specifications.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Multiplexed A/D applications will also find the HFA1145
useful as the A/D driver/multiplexer.
Applications
The HFA1145 is a low power, high performance upgrade for
the CLC410.
• Flash A/D Drivers
• Video Switching and Routing
• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems
For Military grade product, please refer to the HFA1145/883
data sheet.
Ordering Information
PART
NUMBER
(BRAND)
TEMP.
RANGE
(°C)
• RGB Preamps
PART
MARKING
PKG.
PACKAGE DWG. #
• Medical Imaging
HFA1145IB
1145IB
-40 to 85 8 Ld SOIC
M8.15
M8.15
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
HFA1145IBZ
(Note)
1145IBZ
-40 to 85 8 Ld SOIC
(Pb-free)
HFA1145IP
HFA1145IP
-40 to 85 8 Ld PDIP
E8.3
E8.3
Pinout
HFA1145IPZ
(Note)
HFA1145IPZ -40 to 85 8 Ld PDIP*
(Pb-free)
HFA1145 (SOIC)
TOP VIEW
HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps
Note: Requires a SOIC-to-DIP adapter. See
“Evaluation Board” section inside.
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
DISABLE
V+
-
+
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
OUT
NC
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HFA1145
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SUPPLY
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Output Current (Note 1) . . . . . . . . . . . . . . . . .Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>600V
Maximum Junction Temperature (Die Only) . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±5V, A = +1, R = 510Ω, R = 100Ω, Unless Otherwise Specified
SUPPLY V F L
(NOTE 3)
TEST
PARAMETER
INPUT CHARACTERISTICS
Input Offset Voltage
TEST CONDITIONS
LEVEL
TEMP. (°C)
MIN
TYP
MAX
UNITS
A
A
B
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A
B
A
A
A
25
Full
Full
25
-
-
2
3
5
8
mV
mV
Average Input Offset Voltage Drift
-
1
10
-
μV/°C
dB
Input Offset Voltage
Common-Mode Rejection Ratio
ΔV
ΔV
ΔV
= ±1.8V
= ±1.8V
= ±1.2V
47
45
45
50
47
47
-
50
48
48
54
50
50
6
CM
CM
CM
85
-
dB
-40
25
-
dB
Input Offset Voltage
Power Supply Rejection Ratio
ΔV = ±1.8V
PS
-
dB
ΔV = ±1.8V
PS
85
-
dB
ΔV = ±1.2V
PS
-40
25
-
dB
Non-Inverting Input Bias Current
15
25
60
1
μA
Full
Full
25
-
10
5
μA
Non-Inverting Input Bias Current Drift
-
nA/°C
μA/V
μA/V
μA/V
MΩ
MΩ
MΩ
μA
Non-Inverting Input Bias Current
Power Supply Sensitivity
ΔV = ±1.8V
PS
-
0.5
0.8
0.8
1.2
0.8
0.8
2
ΔV = ±1.8V
PS
85
-
3
ΔV = ±1.2V
PS
-40
25
-
3
Non-Inverting Input Resistance
ΔV
ΔV
ΔV
= ±1.8V
= ±1.8V
= ±1.2V
0.8
0.5
0.5
-
-
CM
CM
CM
85
-
-40
25
-
Inverting Input Bias Current
7.5
15
200
6
Full
Full
25
-
5
μA
Inverting Input Bias Current Drift
-
60
3
nA/°C
μA/V
μA/V
μA/V
Inverting Input Bias Current
Common-Mode Sensitivity
ΔV
ΔV
ΔV
= ±1.8V
= ±1.8V
= ±1.2V
-
CM
CM
CM
85
-
4
8
-40
-
4
8
FN3955.5
June 1, 2006
2
HFA1145
Electrical Specifications
V
= ±5V, A = +1, R = 510Ω, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
(NOTE 3)
TEST
PARAMETER
TEST CONDITIONS
LEVEL
TEMP. (°C)
MIN
TYP
2
MAX
UNITS
μA/V
μA/V
μA/V
Ω
Inverting Input Bias Current
Power Supply Sensitivity
ΔV = ±1.8V
A
A
A
C
C
A
A
25
85
-
5
8
8
-
PS
ΔV = ±1.8V
-
4
PS
ΔV = ±1.2V
-40
25
-
-
4
PS
Inverting Input Resistance
Input Capacitance
60
25
-
1.6
±2.4
±1.7
-
pF
Input Voltage Common Mode Range
25, 85
-40
±1.8
±1.2
-
V
(Implied by V CMRR, +R , and -I
CMS
IO IN
BIAS
-
V
tests)
Input Noise Voltage Density (Note 6)
f = 100kHz
f = 100kHz
B
B
25
25
-
-
3.5
2.5
-
-
nV/√Hz
pA/√Hz
Non-Inverting Input Noise Current Density
(Note 6)
Inverting Input Noise Current Density
(Note 6)
f = 100kHz
B
C
25
25
-
-
20
-
-
pA/√Hz
kΩ
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain
A
= -1
500
V
AC CHARACTERISTICS
R = 510Ω, Unless Otherwise Specified
F
-3dB Bandwidth
A
= +1, +R = 510Ω
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
25
Full
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
270
240
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
S
(V
= 0.2V , Note 6)
P-P
OUT
A
= -1, R = 425Ω
300
V
F
A
= +2
25
330
V
Full
25
260
A
= +10, R = 180Ω
130
V
F
Full
25
90
Full Power Bandwidth
(V = 5V at A = +2/-1,
A
= +1, +R = 510Ω
135
V
S
OUT
4V
P-P
V
A
= -1
25
140
V
at A = +1, Note 6)
P-P
V
A
= +2
25
115
V
Gain Flatness
(A = +2, V
To 25MHz
25
±0.03
±0.04
±0.11
±0.22
±0.03
±0.09
1
= 0.2V , Note 6)
OUT P-P
V
Full
25
dB
To 75MHz
dB
Full
25
dB
Gain Flatness
(A = +1, +R = 510Ω, V = 0.2V , Note 6)
OUT P-P
To 25MHz
To 75MHz
dB
V
S
25
dB
Minimum Stable gain
Full
V/V
OUTPUT CHARACTERISTICS
A = +2, R = 510Ω, Unless Otherwise Specified
V F
Output Voltage Swing
(Note 6)
A
= -1, R = 100Ω
A
A
A
A
B
B
25
Full
25, 85
-40
±3
±2.8
50
28
-
±3.4
±3
-
-
-
-
-
-
V
V
V
L
Output Current
(Note 6)
A
= -1, R = 50Ω
60
mA
mA
mA
Ω
V
L
42
Output Short Circuit Current
25
90
Closed Loop Output Impedance (Note 6)
DC
25
-
0.08
FN3955.5
June 1, 2006
3
HFA1145
Electrical Specifications
V
= ±5V, A = +1, R = 510Ω, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
(NOTE 3)
TEST
PARAMETER
TEST CONDITIONS
10MHz
LEVEL
TEMP. (°C)
MIN
TYP
-48
-44
-50
-45
-55
MAX
UNITS
dBc
dBc
dBc
dBc
dB
Second Harmonic Distortion
B
B
B
B
B
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
(V
= 2V , Note 6)
P-P
OUT
20MHz
10MHz
20MHz
30MHz
Third Harmonic Distortion
(V = 2V , Note 6)
OUT
P-P
Reverse Isolation (S , Note 6)
12
TRANSIENT CHARACTERISTICS
A = +2, R = 510Ω, Unless Otherwise Specified
V F
Rise and Fall Times
V
= 0.5V
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
25
Full
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.1
1.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
OUT
P-P
Overshoot (Note 4)
+OS
-OS
+OS
-OS
+SR
3
%
(V
= 0 to 0.5V, V
t
IN RISE
= 1ns)
= 1ns)
OUT
25
5
%
Overshoot (Note 4)
(V = 0.5V , V
25
3
%
t
P-P IN RISE
OUT
25
11
%
Slew Rate
(V = 4V , A = +1, +R = 510Ω)
25
1000
975
650
580
1400
1200
800
700
2100
1900
1000
900
15
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
ns
OUT
P-P
V
S
Full
25
-SR (Note 5)
+SR
Full
25
Slew Rate
(V = 5V , A = +2)
OUT
P-P
V
Full
25
-SR (Note 5)
+SR
Full
25
Slew Rate
(V = 5V , A = -1)
OUT
P-P
V
Full
25
-SR (Note 5)
Full
25
Settling Time
(V = +2V to 0V step, Note 6)
To 0.1%
OUT
To 0.05%
To 0.02%
25
23
ns
25
30
ns
Overdrive Recovery Time
V
= ±2V
25
8.5
ns
IN
A = +2, R = 510Ω, Unless Otherwise Specified
V
VIDEO CHARACTERISTICS
F
Differential Gain
(f = 3.58MHz)
R
R
R
R
= 150Ω
= 75Ω
B
B
B
B
25
25
25
25
-
-
-
-
0.02
0.03
0.03
0.05
-
-
-
-
%
L
L
L
L
%
Differential Phase
(f = 3.58MHz)
= 150Ω
= 75Ω
Degrees
Degrees
DISABLE CHARACTERISTICS
Disabled Supply Current
V
= 0V
= 0V
A
A
A
A
A
Full
Full
-
-
3
4
0.8
-
mA
V
DISABLE
DISABLE
DISABLE Input Logic Low
DISABLE Input Logic High
-
25, 85
-40
2.0
2.4
-
-
-
V
-
V
DISABLE Input Logic Low Current
V
Full
100
200
μA
FN3955.5
June 1, 2006
4
HFA1145
Electrical Specifications
V
= ±5V, A = +1, R = 510Ω, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
(NOTE 3)
TEST
PARAMETER
DISABLE Input Logic High Current
Output Disable Time (Note 6)
TEST CONDITIONS
LEVEL
TEMP. (°C)
MIN
TYP
1
MAX
15
-
UNITS
μA
V
= 5V
A
B
Full
25
-
-
DISABLE
= ±1V,
V
V
35
ns
IN
DISABLE
= 2.4V to 0V
Output Enable Time (Note 6)
V
V
= ±1V,
B
25
-
180
-
ns
IN
= 0V to 2.4V
= 0V
DISABLE
DISABLE
DISABLE
Disabled Output Capacitance
Disabled Output Leakage
V
B
A
25
-
-
2.5
3
-
pF
±
V
V
= 0V, V
=
2V,
Full
10
μA
IN
= ±3V
OUT
Off Isolation
At 5MHz
B
B
25
25
-
-
-75
-60
-
-
dB
dB
(V
= 0V, V = 1V , Note 6)
DISABLE
IN P-P
At 25MHz
POWER SUPPLY CHARACTERISTICS
Power Supply Range
C
A
A
25
25
±4.5
-
±5.5
6.1
V
Power Supply Current (Note 6)
-
-
5.8
5.9
mA
mA
Full
6.3
NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. Undershoot dominates for output signal swings below GND (e.g. 0.5V
condition. See the “Application Information” section for details.
), yielding a higher overshoot limit compared to the V
P-P
= 0 to 0.5V
OUT
5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric positive and
negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.
6. See Typical Performance Curves for more information.
Application Information
GAIN
(A
BANDWIDTH
(MHz)
)
R (Ω)
F
CL
Optimum Feedback Resistor
-1
+1
425
300
270
330
300
130
Although a current feedback amplifier’s bandwidth
510 (+R = 510Ω)
S
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may be
minimized by taking advantage of the current feedback
+2
510
200
180
+5
+10
amplifier’s unique relationship between bandwidth and R . All
F
Non-inverting Input Source Impedance
current feedback amplifiers require a feedback resistor, even
for unity gain applications, and R , in conjunction with the
internal compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier’s bandwidth is
For best operation, the DC source impedance seen by the
non-inverting input should be ≥50Ω. This is especially
important in inverting gain configurations where the non-
inverting input would normally be connected directly to GND.
F
inversely proportional to R . The HFA1145 design is optimized
F
for R = 510Ω at a gain of +2. Decreasing R decreases
F
F
DISABLE Input TTL Compatibility
stability, resulting in excessive peaking and overshoot (Note:
Capacitive feedback will cause the same problems due to the
feedback impedance decrease at higher frequencies). At
The HFA1145 derives an internal GND reference for the
digital circuitry as long as the power supplies are
symmetrical about GND. With symmetrical supplies the
digital switching threshold (V = (V + V )/2 = (2.0 +
higher gains, however, the amplifier is more stable so R can
be decreased in a trade-off of stability for bandwidth.
F
TH
IH
IL
0.8)/2) is 1.4V, which ensures the TTL compatibility of the
DISABLE input. If asymmetrical supplies (e.g. +10V, 0V) are
utilized, the switching threshold becomes:
V+ + V-
The table below lists recommended R values for various
F
gains, and the expected bandwidth. For a gain of +1, a
resistor (+R ) in series with +IN is required to reduce gain
S
-------------------
+ 1.4V
V
=
peaking and increase stability.
TH
2
and the V and V levels will be V ± 0.6V, respectively.
IH IL TH
FN3955.5
June 1, 2006
5
HFA1145
Driving Capacitive Loads
Optional GND Pad (Die Use Only) for
TTL Compatibility
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
The die version of the HFA1145 provides the user with a GND
pad for setting the disable circuitry GND reference. With
symmetrical supplies the GND pad may be left unconnected, or
tied directly to GND. If asymmetrical supplies (e.g. +10V, 0V)
are utilized, and TTL compatibility is desired, die users must
connect the GND pad to GND. With an external GND, the
DISABLE input is TTL compatible regardless of supply voltage
utilized.
avoided by placing a resistor (R ) in series with the output
S
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R and C
S
L
combinations for the optimum bandwidth, stability, and
Pulse Undershoot and Asymmetrical Slew Rates
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
The HFA1145 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added distortion
for signals swinging below ground, and an increased
undershoot on the negative portion of the output waveform
(See Figures 5, 8, and 11). This undershoot isn’t present for
small bipolar signals, or large positive signals. Another artifact
of the composite device is asymmetrical slew rates for output
signals with a negative voltage component. The slew rate
degrades as the output signal crosses through 0V (See Figures
5, 8, and 11), resulting in a slower overall negative slew rate.
Positive only signals have symmetrical slew rates as illustrated
in the large signal positive pulse response graphs (See Figures
4, 7, and 10).
R and C form a low pass network at the output, thus limiting
S
L
system bandwidth well below the amplifier bandwidth of
270MHz (for A = +1). By decreasing R as C increases (as
V
S
L
illustrated in the curves), the maximum bandwidth is obtained
without sacrificing stability. In spite of this, the bandwidth
decreases as the load capacitance increases. For example, at
A = +1, R = 62Ω, C = 40pF, the overall bandwidth is
V
S
L
limited to 180MHz, and bandwidth drops to 75MHz at A = +1,
V
R = 8Ω, C = 400pF.
S
L
50
40
30
20
10
0
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
A
= +1
V
A
= +2
150
V
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
(0.1μF) chip capacitor works well in most cases.
0
100
200
300
400
50
250
350
Terminated microstrip signal lines are recommended at the
device’s input and output connections. Capacitance,
parasitic or planned, connected to the output must be
minimized, or isolated as discussed in the next section.
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN), as this
capacitance causes gain peaking, pulse overshoot, and if
large enough, instability. To reduce this capacitance, the
designer should remove the ground plane under traces
connected to -IN, and keep connections to -IN as short as
possible.
The performance of the HFA1145 may be evaluated using
the HFA11XX Evaluation Board and a SOIC to DIP adaptor
like the Aries Electronics Part Number 14-350000-10. The
layout and schematic of the board are shown in Figure 2.
The V connection may be used to exercise the DISABLE
H
pin, but note that this connection has no 50Ω termination. To
order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
An example of a good high frequency layout is the Evaluation
Board shown in Figure 2.
FN3955.5
June 1, 2006
6
HFA1145
V
H
1
+IN
OUT
V-
V+
V
L
GND
FIGURE 2A. TOP LAYOUT
FIGURE 2B. TOP LAYOUT
510
510
V
H
R
1
1
2
3
4
8
7
6
5
10μF
0.1μF
50Ω
+5V
50Ω
IN
OUT
V
L
GND
0.1μF
10μF
-5V
GND
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Typical Performance Curves V
= ±5V, R = 510Ω, T = 25°C, R = 100Ω, Unless Otherwise Specified
F A L
SUPPLY
200
3.0
2.5
2.0
1.5
1.0
0.5
0
A
= +1
A
= +1
V
V
+R = 510Ω
+R = 510Ω
S
150
100
50
S
0
-50
-100
-0.5
-1.0
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 3. SMALL SIGNAL PULSE RESPONSE
FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE
FN3955.5
June 1, 2006
7
HFA1145
Typical Performance Curves V
= ±5V, R = 510Ω, T = 25°C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
F
A
L
2.0
200
150
100
50
A
= +1
A
= +2
V
V
+R = 510Ω
S
1.5
1.0
0.5
0
0
-0.5
-1.0
-50
-100
-1.5
-2.0
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
3.0
2.0
1.5
1.0
0.5
0
A
= +2
A = +2
V
V
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-0.5
-1.0
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE
200
3.0
A
R
= +10
V
F
A
R
= +10
V
F
= 180Ω
= 180Ω
150
100
50
2.5
2.0
1.5
1.0
0.5
0
0
-50
-100
-0.5
-1.0
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE
FN3955.5
June 1, 2006
8
HFA1145
Typical Performance Curves V
= ±5V, R = 510Ω, T = 25°C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
F
A
L
2.0
A
R
= +10
V
F
= 180Ω
1.5
1.0
0.5
0
DISABLE
800mV/DIV.
(0.4V to 2.4V)
OUT
400mV/DIV.
-0.5
-1.0
0V
-1.5
-2.0
A
= +1, V = 1V
IN
V
TIME (5ns/DIV.)
TIME (50ns/DIV.)
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 12. OUTPUT ENABLE AND DISABLE RESPONSE
V
= 200mV
P-P
OUT
+R = 510Ω (+1)
A
= +2
V
3
3
0
S
A
A
= +1
= -1
V
V
+R = 0Ω (-1)
S
0
A
= +10
V
-3
-3
A
= +5
V
A
= +2
V
0
0
A
= -1
V
90
90
A
= +5
V
= 200mV
P-P
V
OUT
180
270
R
R
R
= 510Ω (+2)
= 200Ω (+5)
= 180Ω (+10)
180
270
F
F
F
A
= +10
100
V
A
= +1
V
0.3
1
10
100
500
0.3
1
10
FREQUENCY (MHz)
500
FREQUENCY (MHz)
FIGURE 13. FREQUENCY RESPONSE
FIGURE 14. FREQUENCY RESPONSE
A
= +2
V
V
= 200mV
P-P
OUT
3
0
3
A
= -1
V
0
V
V
= 4V
= 5V
(+1)
(-1, +2)
OUT
OUT
P-P
P-P
V
= 1.5V
= 5V
-3
-3
OUT
P-P
A
= +1
V
V
OUT
P-P
+R = 510Ω (+1)
S
A
= +2
V
V
= 200mV
OUT
P-P
0
90
V
= 1.5V
P-P
180
270
OUT
V
= 5V
P-P
OUT
1
10
100
200
0.3
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 16. FULL POWER BANDWIDTH
FN3955.5
June 1, 2006
9
HFA1145
Typical Performance Curves V
= ±5V, R = 510Ω, T = 25°C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
F
A
L
V
= 200mV
P-P
OUT
= +2
R
= 1kΩ
500
400
300
200
100
0
L
R
= 500Ω
3
L
A
A
= +2
V
V
= 200mV
P-P
V
OUT
= 180Ω (+10)
R
F
0
+R = 510Ω (+1)
S
R
= 50Ω
L
-3
R
= 100Ω
L
A
= +1
V
R
= 50Ω
L
= 100Ω
R
0
L
90
R
= 1kΩ
= 500Ω
A
= +10
L
L
V
R
180
270
-100
-50
0
50
100
150
0.3
1
10
FREQUENCY (MHz)
100
500
TEMPERATURE (°C)
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FIGURE 18. -3dB BANDWIDTH vs TEMPERATURE
-30
V
= 200mV
P-P
OUT
+R = 510Ω (+1)
A
V
= +2
V
-40
-50
-60
-70
-80
-90
S
= 1V
IN
P-P
0.25
0.20
0.15
0.10
0.05
0
A
= +2
A
V
= +1
V
-0.05
-0.10
0.3
1
10
100
1
10
75
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 19. GAIN FLATNESS
FIGURE 20. OFF ISOLATION
-40
A
= +2
V
= 2V
V
OUT
P-P
A
= +1, +2
-50
-60
-70
-80
-90
V
1K
100
10
A
= -1
V
1
0.1
0.01
0.3
1
10
FREQUENCY (MHz)
100
0.3
1
10
100
1000
FREQUENCY (MHz)
FIGURE 21. REVERSE ISOLATION (S
)
FIGURE 22. ENABLED OUTPUT IMPEDANCE
12
FN3955.5
June 1, 2006
10
HFA1145
Typical Performance Curves V
= ±5V, R = 510Ω, T = 25°C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
F
A
L
-30
-40
-50
-60
-70
A
= +2
= 2V
V
0.8
0.6
0.4
A
= +2
V
V
OUT
20MHz
0.2
0.1
0
10MHz
-0.2
-0.4
-0.6
-0.8
-5
0
5
10
15
3
8
13
18
23
28
33
38
43
48
TIME (ns)
OUTPUT POWER (dBm)
FIGURE 23. SETTLING RESPONSE
FIGURE 24. SECOND HARMONIC DISTORTION vs P
OUT
-30
-40
3.6
A
= -1
|-V
| (R = 100Ω)
OUT
A
= +2
V
L
V
3.5
+V
(R = 100Ω)
L
OUT
3.4
3.3
3.2
3.1
-50
-60
-70
+V
OUT
(R = 50Ω)
L
3.0
2.9
2.8
|-V
| (R = 50Ω)
L
OUT
2.7
2.6
-50
-25
0
25
50
75
100
125
-5
0
5
10
15
OUTPUT POWER (dBm)
TEMPERATURE (°C)
FIGURE 25. THIRD HARMONIC DISTORTION vs P
FIGURE 26. OUTPUT VOLTAGE vs TEMPERATURE
OUT
100
100
6.1
6.0
5.9
5.8
5.7
5.6
I
NI-
10
10
E
NI
I
NI+
1
100
1
0.1
3.5
4
4.5
5
5.5
6
6.5
7
7.5
1
10
POWER SUPPLY VOLTAGE (±V)
FREQUENCY (kHz)
FIGURE 27. INPUT NOISE CHARACTERISTICS
FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN3955.5
June 1, 2006
11
HFA1145
PASSIVATION:
Die Characteristics
DIE DIMENSIONS:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
59 mils x 59 mils x 19 mils
1500μm x 1500μm x 483μm
TRANSISTOR COUNT:
METALLIZATION:
75
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
Thickness: Metal 2: 16kÅ ±0.8kÅ
Metallization Mask Layout
HFA1145
DISABLE
-IN
V+
OUT
+IN
V-
OPTIONAL GND (NOTE)
NOTE: This pad is not bonded out on packaged units. Die users may set a GND reference, via this pad, to ensure the TTL compatibility
of the DIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). See the “Application Information” section for details.
FN3955.5
June 1, 2006
12
HFA1145
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3955.5
June 1, 2006
13
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