HCS74K [INTERSIL]
Radiation Hardened Dual-D Flip-Flop with Set and Reset; 抗辐射双D触发器具有置位和复位
| 型号： | HCS74K |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| 文件： | 总9页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS74MS
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
September 1995
Features
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
TOP VIEW
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
R1N
D1
1
2
3
4
5
6
7
14 VCC
13 R2N
12 D2
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
CP1
S1N
Q1
11 CP2
10 S2N
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
Q1N
GND
9
8
Q2
Q2N
• Input Logic Levels
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
R1
D1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
R2
Description
CP1
S1
D2
The Intersil HCS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
CP2
S2
Q1
The HCS74MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Q1
Q2
GND
8
Q2
The HCS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS74DMSR
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
14 Lead SBDIP
o
o
-55 C to +125 C
o
o
HCS74KMSR
-55 C to +125 C
14 Lead Ceramic Flatpack
14 Lead SBDIP
o
HCS74D/Sample
HCS74K/Sample
HCS74HMSR
+25 C
o
+25 C
Sample
14 Lead Ceramic Flatpack
Die
o
+25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518772
File Number 2142.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
83
HCS74MS
Functional Diagram
S
CL
4(10)
P
N
CL
CL
D
P
N
CL
P
N
2(12)
CL
CL
CL
P
N
Q
CL
6(8)
R
1(13)
Q
5(9)
CP
3(11)
CL
CL
TRUTH TABLE
INPUTS
OUTPUTS
SET
L
RESET
CP
D
X
X
X
H
L
Q
H
Q
L
H
L
X
X
X
H
L
H
L
L
H*
H
H*
L
H
H
H
H
H
L
H
H
L
X
Q0
Q0
NOTE: L = Logic Level Low, H = Logic Level High, X = Don’t Care
= Transition from Low to High Level
Q0 = The level of Q before the indicated input conditions were established.
* This configuration is non-stable, that is, it will not persist when set and reset inputs return to their inactive (High) level.
Spec Number 518772
84
Specifications HCS74MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 116 C/W
Maximum Package Power Dissipation at +125 C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/ C
θ
θ
JA
JC
o
o
74 C/W
24 C/W
o
o
30 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
20
o
o
+125 C, -55 C
-
400
µA
o
Output Current
(Sink)
IOL
IOH
VOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25 C
4.8
4.0
-4.8
-4.0
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
-
-
o
Output Current
(Source)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-
o
o
o
Output Voltage Low
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
0.1
IOL = 50µA, VIL = 1.35V
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
0.1
V
V
V
o
o
o
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
+25 C, +125 C, -55 C
VCC
-0.1
-
-
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
+25 C, +125 C, -55 C
VCC
-0.1
o
Input Leakage
Current
IIN
FN
VCC = 5.5V, VIN = VCC or
GND
1
+25 C
-
-
-
±0.5
±5.0
-
µA
µA
-
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V,
VIH = 0.70(VCC), (Note 2)
VIL = 0.30(VCC)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518772
85
Specifications HCS74MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
MIN
(NOTES 1, 2)
A SUB-
PARAMETER
CP to Q, Q
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MAX
27
32
26
31
26
31
27
32
24
29
25
30
UNITS
ns
o
TPHL
VCC = 4.5V
9
10, 11
9
+25 C
2
2
2
2
2
2
2
2
2
2
2
2
o
o
+125 C, -55 C
ns
o
TPLH
TPLH
TPHL
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
S to Q
S to Q
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
R to Q
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
R to Q
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
-
MAX
UNITS
pF
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, f = 1MHz
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+25 C
53
55
10
10
15
22
-
o
o
+125 C, -55 C
-
pF
o
Input Capacitance
CIN
VCC = 5.0V, f = 1MHz
VCC = 4.5V
+25 C
-
pF
o
o
+125 C, -55 C
-
pF
o
Output Transition
Time
TTHL
TTLH
+25 C
-
ns
o
o
+125 C, -55 C
-
ns
o
Max Operating
Frequency
FMAX
TSU
TH
VCC = 4.5V
+25 C
30
20
11
12
3
MHz
MHz
ns
o
o
+125 C, -55 C
-
o
Data to CP Set-up
Time
VCC = 4.5V
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Hold Time
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
3
-
ns
o
Removal Time
R, S to CP
TREM
TW
VCC = 4.5V
+25 C
5
-
ns
o
o
+125 C, -55 C
6
-
ns
o
Pulse Width R, S
Pulse Width CP
NOTE:
VCC = 4.5V
+25 C
14
16
14
16
-
ns
o
o
+125 C, -55 C
-
ns
o
TW
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
-
ns
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 518772
86
Specifications HCS74MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
MAX
0.4
-
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
-
o
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25 C
4.0
mA
o
Output Current
(Source)
IOH
VOL
VOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25 C
-4.0
-
-
0.1
-
mA
V
o
Output Voltage Low
Output Voltage High
Input Leakage Current
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
+25 C
o
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
+25 C
VCC
-0.1
V
o
IIN
FN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
+25 C
-
-
o
CP to Q, Q
TPHL
TPLH
TPLH
TPHL
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
2
2
2
2
32
31
31
32
29
30
ns
ns
ns
ns
ns
ns
o
+25 C
o
S to Q
S to Q
+25 C
o
+25 C
o
R to Q
+25 C
o
R to Q
+25 C
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
o
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)
GROUP B
PARAMETER
SUBGROUP
DELTA LIMIT
6µA
ICC
IOL/IOH
5
5
-15% of 0 Hour
Spec Number 518772
87
Specifications HCS74MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H
1, 7, 9
1, 7, 9
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
ICC, IOL/H
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
Interim Test III (Postburn-In)
PDA
1, 7, 9
ICC, IOL/H
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Group A (Note 1)
Group B
Subgroup B-5
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
Subgroup B-6
Sample/5005
Sample/5005
1, 7, 9
1, 7, 9
Group D
NOTES:
1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
STATIC BURN-IN I TEST CONDITIONS (Note 1)
5, 6, 8, 9 1 - 4, 7, 10 - 13
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
5, 6, 8, 9
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
14
-
-
-
-
7
-
1, 2, 3, 4, 10, 11, 12,
13, 14
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
5, 6, 8, 9
1, 4, 10, 13, 14
3, 11
2, 12
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
5, 6, 8, 9
7
1 - 4, 10 - 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518772
88
HCS74MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518772
89
HCS74MS
Pulse Width, Setup, Hold Timing Diagram
AC Timing Diagrams and Load Circuit
Positive Edge Trigger and Load Circuit
VIH
TW
INPUT
VS
INPUT
VIH
VIL
VIL
TPLH
TH
TPHL
TSU
VOH
VOL
VOH
VOL
TW
VS
OUTPUT
CP INPUT
VIH
VS
VIL
TTLH
TTHL
80%
80%
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
20%
20%
OUTPUT
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
AC VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
V
V
V
V
V
VIH
VS
VIH
VS
VIL
VIL
GND
0
GND
0
DUT
TEST
POINT
DUT
TEST
POINT
CL
RL
CL
RL
CL = 50pF
CL = 50pF
RL = 500Ω
RL = 500Ω
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
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Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number 518772
90
HCS74MS
Die Characteristics
DIE DIMENSIONS:
89 x 88 mils
2.25 x 2.24mm
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS74MS
D1
(2)
R1
(1)
VCC
(14)
CP1 (3)
(13) R2
(12) D2
NC
S1 (4)
NC
(11) CP2
Q1 (5)
(10) S2
Q1 (6)
(7)
GND
(8)
Q2
(9)
Q2
Spec Number 518772
91
相关型号：
HCS74K/SAMPLE
HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14
RENESAS
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