HCS74KTR [INTERSIL]
Radiation Hardened Dual-D Flip-Flop with Set and Reset; 抗辐射双D触发器具有置位和复位
| 型号： | HCS74KTR |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| 文件： | 总3页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS74T
Data Sheet
July 1999
File Number 4615.1
Radiation Hardened Dual-D Flip-Flop with
Set and Reset
Features
• QML Class T, Per MIL-PRF-38535
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
• Radiation Performance
5
- Gamma Dose (γ) 1 x 10 RAD(Si)
- Latch-Up Free Under Any Conditions, SOS Process
2
- SEP Effective LET No Upsets: >100 MEV-cm /mg
-9
- Single Event Upset (SEU) Immunity < 2 x 10
Errors/Bit-Day (Typ)
The Intersil HCS74T is a Radiation Hardened Positive Edge
Triggered Flip-Flop with set and reset.
• 3 Micron Radiation Hardened SOS CMOS
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
The HCS74T utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
- V = 30% of V
IL CC
Max
Min
Specifications
- V = 70% of V
IH
CC
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
• Input Current Levels Ii ≤ 5µA at V , V
OL OH
Pinouts
Detailed Electrical Specifications for the HCS74T are
contained in SMD 5962-95782. A “hot-link” is provided from
our website for downloading.
HCS74T (SBDIP), CDIP2-T14
TOP VIEW
www.intersil.com/spacedefense/newsafclasst.asp
R1
D1
1
2
3
4
5
6
7
14 V
CC
13 R2N
12 D2
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
CP1
S1N
Q1
11 CP2
10 S2N
www.intersil.com/quality/manuals.asp
Q1N
GND
9
8
Q2
Ordering Information
Q2N
TEMP.
ORDERING
INFORMATION
PART
NUMBER
RANGE
( C)
o
HCS74T (FLATPACK), CDFP3-F14
5962R9578201TCC
5962R9578201TXC
HCS74DTR
HCS74KTR
-55 to 125
-55 to 125
TOP VIEW
R1
D1
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
R2
D2
CP2
S2
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
CP1
S1
Q1
Q1
Q2
Q2
GND
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HCS74T
Functional Diagram
S
CL
4(10)
2(12)
P
N
CL
CL
D
P
N
CL
P
N
CL
CL
CL
P
N
Q
CL
6(8)
R
1(13)
Q
5(9)
CP
3(11)
CL
CL
TRUTH TABLE
INPUTS
OUTPUTS
SET
L
RESET
CP
X
D
X
X
X
H
L
Q
H
Q
L
H
L
H
X
L
H
L
L
X
H†
H
H†
L
H
H
H
H
H
L
H
H
L
X
Q0
Q0
NOTE: L = Logic Level Low, H = Logic Level High, X = Don’t Care
= Transition from Low to High Level
Q0 = The level of Q before the indicated input conditions were established.
† This configuration is non-stable, that is, it will not persist when set and reset inputs return to their inactive (High) level.
2
HCS74T
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Silox (S O )
(2261µm x 2235µm x 533µm ±51µm)
89 x 88 x 21mils ±2mil
i
2
Thickness: 13kÅ ±2.6kÅ
METALLIZATION:
Type: Al Si
WORST CASE CURRENT DENSITY:
2
< 2.0e5 A/cm
Thickness: 11kÅ ±1kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
192
Unbiased (Silicon on Sapphire)
PROCESS:
BACKSIDE FINISH:
CMOS SOS
Sapphire
Metallization Mask Layout
HCS74T
D1
(2)
R1
(1)
V
CC
(14)
CP1 (3)
(13) R2
(12) D2
NC
S1 (4)
NC
(11) CP2
Q1 (5)
(10) S2
Q1 (6)
(7)
GND
(8)
Q2
(9)
Q2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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