HA7-5147R5254 [INTERSIL]
120MHz, Ultra-Low Noise Precision Operational Amplifiers; 120MHz的,超低噪声精密运算放大器型号: | HA7-5147R5254 |
厂家: | Intersil |
描述: | 120MHz, Ultra-Low Noise Precision Operational Amplifiers |
文件: | 总10页 (文件大小:627K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HA-5147
®
Data Sheet
July 12, 2006
FN2910.9
120MHz, Ultra-Low Noise Precision
Operational Amplifiers
Features
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V/µs
The HA-5147 operational amplifier features an unparalleled
combination of precision DC and wideband high speed
characteristics. Utilizing the Intersil D. I. technology and
advanced processing techniques, this unique design unites
low noise (3.2nV/√Hz) precision instrumentation
• Wide Gain Bandwidth (A ≥ 10). . . . . . . . . . . . . . 120MHz
V
• Low Noise . . . . . . . . . . . . . . . . . . . . . 3.2nV/√Hz at 1kHz
[ /Title
(HA-
5147)
/Sub-
ject
(120M
Hz,
Ultra-
Low
Noise
Preci-
sion
Opera-
tional
Ampli-
fiers)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
• Low V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV
OS
• High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120dB
• High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V/mV
• Pb-Free Available (RoHS Compliant)
performance with high speed (35V/µs) wideband capability.
This amplifier’s impressive list of features include low V
OS
(30mV), wide gain bandwidth (120MHz), high open loop gain
(1500V/mV), and high CMRR (120dB). Additionally, this
flexible device operates over a wide supply range (±5V to
±20V) while consuming only 140mW of power.
Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers
• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• Pulse/RF Amplifiers
Using the HA-5147 allows designers to minimize errors while
maximizing speed and bandwidth in applications requiring
gains greater than ten.
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5147’s qualities include instrumentation amplifiers, pulse
or RF amplifiers, audio preamplifiers, and signal conditioning
circuits.
• For Further Design Ideas See Application Note AN553
This device can easily be used as a design enhancement by
directly replacing the 725, OP25, OP06, OP07, OP27 and
OP37 where gains are greater than ten. For military grade
product, refer to the HA-5147/883 data sheet.
Pinout
HA-5147 (CERDIP)
TOP VIEW
1
2
3
4
8
7
6
5
BAL
-IN
BAL
V+
-
+
+IN
V-
OUT
NC
Ordering Information
ductor,
single,
opera-
tional
ampli-
fier,
low
power
op
TEMP.
o
PKG.
PART NUMBER
HA7-5147-2
HA7-5147R5254 (Note) HA7- 5147R5254
PART MARKING RANGE ( C)
PACKAGE
DWG. #
HA7- 5147-2
-55 to 125
-55 to 125
8 Ld CerDIP
8 Ld CerDIP with Pb-free Hot Solder DIP Lead Finish (SnAgCu)
F8.3A
F8.3A
NOTE: Intersil Pb-free hermetic packaged products employ SnAgCu or Au termination finish, which are RoHS compliant termination finishes and
compatible with both SnPb and Pb-free soldering operations. Ceramic dual in-line packaged products (CerDIPs) do contain lead (Pb) in the seal
glass and die attach glass materials. However, lead in the glass materials of electronic components are currently exempted per the RoHS directive.
Therefore, ceramic dual inline packages with Pb-free termination finish are considered to be RoHS compliant.
amp,
low
input
bias
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-5147
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
o
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 44V
Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 0.7V
Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
135
50
o
Maximum Junction Temperature (Hermetic Package). . . . . . . .175 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
Temperature Range
HA-5147-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±15V, C ≤ 50pF, R ≤ 100Ω
SUPPLY L S
TEMP.
o
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
TEST CONDITIONS
( C)
MIN
TYP
MAX
UNITS
25
Full
Full
25
-
30
70
100
300
1.8
80
150
75
135
-
µV
µV
-
o
Average Offset Voltage Drift
Bias Current
-
0.4
15
µV/ C
-
nA
nA
nA
nA
V
Full
25
-
35
Offset Current
-
12
Full
Full
25
-
30
Common Mode Range
±10.3
±11.5
4
Differential Input Resistance (Note 3)
Input Noise Voltage (Note 4)
0.8
-
MΩ
0.1Hz to 10Hz
25
-
-
-
-
-
-
-
0.09
3.8
3.3
3.2
1.7
1.0
0.4
0.25
8.0
4.5
3.8
-
µV
P-P
Input Noise Voltage Density (Note 5)
f = 10Hz
25
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
f = 100Hz
f = 1000Hz
f = 10Hz
Input Noise Current Density (Note 5)
25
f = 100Hz
f = 1000Hz
-
0.6
TRANSFER CHARACTERISTICS
Minimum Stable Gain
25
25
10
700
300
100
120
-
-
-
-
-
-
-
-
V/V
V/mV
V/mV
dB
Large Signal Voltage Gain
V
V
= ±10V, R = 2kΩ
1500
800
120
140
120
OUT
L
Full
Full
25
Common Mode Rejection Ratio
Gain-Bandwidth-Product
= ±10V
CM
f = 10kHz
f = 1MHz
MHz
MHz
2
HA-5147
Electrical Specifications
V
= ±15V, C ≤ 50pF, R ≤ 100Ω (Continued)
SUPPLY
L
S
TEMP.
o
PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Swing
TEST CONDITIONS
( C)
MIN
TYP
MAX
UNITS
R
R
= 600Ω
25
Full
25
±10.0
±11.4
445
-
±11.5
±13.5
500
70
-
-
-
-
-
V
V
L
= 2kΩ
L
Full Power Bandwidth (Note 6)
Output Resistance
kHz
Ω
Open Loop
25
Output Current
25
16.5
25
mA
TRANSIENT RESPONSE (Note 7)
Rise Time
25
25
25
25
-
28
-
22
35
50
-
ns
V/µs
ns
Slew Rate
V
= ±3V
OUT
Settling Time
Note 8
400
20
-
Overshoot
-
40
%
POWER SUPPLY CHARACTERISTICS
Supply Current
25
-
-
-
3.5
-
-
mA
mA
Full
Full
4.0
51
Power Supply Rejection Ratio
NOTES:
V
= ±4V to ±18V
16
µV/V
S
3. This parameter value is based upon design calculations.
4. Refer to Typical Performance section of the data sheet.
5. The limits for this parameter are guaranteed based on lab characterization, and reflect lot-to-lot variation.
Slew Rate
6. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- .
2πV
PEAK
7. Refer to Test Circuits section of the data sheet.
8. Settling time is specified to 0.1% of final value for a 10V output step and A = -10.
V
3
HA-5147
Test Circuits and Waveforms
+
IN
OUT
-
1.8kΩ
200Ω
50pF
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
IN
IN
OUT
OUT
Vertical Scale: Input = 0.5V/Div.
Vertical Scale: Input = 10mV/Div.
Output = 100mV/Div.
Output = 5V/Div.
Horizontal Scale: 500ns/Div.
Horizontal Scale: 100ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
+15V
2N4416
TO
OSCILLOSCOPE
500Ω
5kΩ
2kΩ
+15V
+
V
NOTES:
AUT
OUT
9. A = -10.
-
V
V
IN
50pF
200Ω
10. Feedback and summing resistors should be
0.1% matched.
-15V
11. Clipping diodes are optional. HP5082-2810
recommended.
2kΩ
FIGURE 2. SETTLING TIME TEST CIRCUIT
4
Schematic Diagram
7
1
8
BALANCE
R
Q
R
1
25
R
R
R
R
R
R
16
C
15
2
20
21
17
7
P32
Q
P37
Q
P38
Q
Q
P44
Q
P43
P35
D
1
Q
D
Q
P55
N45
C
C
5
Q
N19
Q
8
N46
4
Q
N13
Q
P56
Q
Q
N15
N14
Q
N47
R
R
1A
2A
C
Q
N29
1
Q
N20
Q
Q
P17
P16
Q
N51
D
33
R
7
R
3
Q
N52
D
C
9
Q
6
P26
R
R
12
6
14
Q
Q
N4
N3
D
D
54
53
Q
Q
Q
P26
R
R
P36
9
18
OUT-
PUT
Q
N2
Q
P
P36A
R
27
24
D
41
Q
R
N18
13
Q
N12
Q
Q
Q
Q
N1A
N1
N2A
P40
D
34
Q
N7
D
22
23
Q
R
C
P30
19
D
Z
Q
P21
58
Q
R
N42
4
D
59
Q
Q
N6
3
Q
N42A
Q
Q
N5
Q
N48
R
N25
N24
Q
Q
N50
N57
Q
N49
Q
N39
D
60
R
R
R
R
8
R
R
11
5
6
10
22
23
C
2
Q
N10
Q
N11
4
3
2
HA-5147
Application Information
V+
R
P
10K
8
1
3
7
5
NOTE: Tested Offset Adjustment
Range is |V +1mV| minimum re-
-
+
2
6
OS
ferred to output. Typical range is ±4mV
with R = 10kΩ.
P
4
FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT
C
S
R
1
+
-
R
2
R
1
-
R
C
3
+
R
R
3
2
S
NOTE: Low resistances are preferred for low noise applications as a 1kΩ resistor has 4nV/√Hz of thermal noise. Total resistances of greater than
10kΩ on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will
improve stability.
FIGURE 4. SUGGESTED STABILITY CIRCUITS
o
Typical Performance Curves T = 25 C, V
= ±15V, Unless Otherwise Specified
SUPPLY
A
12
6
5
o
= ±15V, T = 25 C
30
V
S
A
20
10
10
8
6
4
3
0
-10
-20
-30
-40
-50
-60
NOISE VOLTAGE
NOISE CURRENT
4
2
1
0
2
0
-60
-40 -20
0
20
40
60
o
80
100 120
1
10
100
1K
10K
100K
1M
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 5. TYPICAL OFFSET VOLTAGE vs TEMPERATURE
FIGURE 6. NOISE CHARACTERISTICS
6
HA-5147
o
Typical Performance Curves T = 25 C, V
= ±15V, Unless Otherwise Specified (Continued)
A
SUPPLY
0.14
o
T
= 25 C
V
T
= ±15V
= 25 C
A
S
A
o
160
120
80
0.12
0.1
0.08
0.06
0.04
0.02
0
40
0
4
6
8
10
12
14
16
18
20
10
100
1K
10K
100K
1M
10M
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 7. NOISE vs SUPPLY VOLTAGE
FIGURE 8. CMRR vs FREQUENCY
120
100
80
60
40
20
0
0
o
T
= 25 C
A
20
40
60
GAIN
0
80
PHASE
90
100
120
180
10
100
1K
10K
100K
1M
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. OPEN LOOP GAIN AND PHASE vs FREQUENCY
17
16
15
14
13
12
11
10
9
1.05
o
o
T
= 25 C
R
= 2K, C = 50pF, T = 25 C
A
L
L
A
1.04
1.03
1.02
1.01
A
VOL
V
OUT
1.0
0.99
8
0.98
0.97
7
6
0.96
5
4
0.95
0
2
4
6
8
10
-60
-40 -20
0
20
40
60
o
80 100 120
LOAD RESISTANCE (kΩ)
TEMPERATURE ( C)
FIGURE 11. A
AND V
vs LOAD RESISTANCE
FIGURE 12. NORMALIZED SLEW RATE vs TEMPERATURE
VOL
OUT
7
HA-5147
o
Typical Performance Curves T = 25 C, V
= ±15V, Unless Otherwise Specified (Continued)
A
SUPPLY
28
24
20
16
12
8
o
R
= 2K, C = 50pF, T = 25 C
L A
V
= 0V, V = ±15V
S
L
2.82
2.80
O
2.78
2.76
2.74
2.72
2.70
2.68
4
-55
25
TEMPERATURE ( C)
125
0
0.4
0.8
1.2
1.6
2
o
FREQUENCY (MHz)
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. V
MAX (UNDISTORTED SINEWAVE OUTPUT)
OUT
vs FREQUENCY
o
R
= 2K, C = 50pF, T = 25 C
L
L
A
40
30
20
10
0
GAIN
0
PHASE
90
180
A
= 25,000V/V; E = 0.08µV
RTI
P-P
CL
N
1K
10K
100K
1M
10M
100M
Horizontal Scale = 1s/Div.; Vertical Scale = 0.002µV/Div.
FREQUENCY (Hz)
FIGURE 15. CLOSED LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 16. PEAK-TO-PEAK NOISE VOLTAGE (0.1Hz TO 10Hz)
8
HA-5147
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
104 mils x 65 mils x 19 mils
2650µm x 1650µm x 483µm
3
4
2
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
63
SUBSTRATE POTENTIAL (POWERED UP):
PROCESS:
V-
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5147
BAL
BAL
-IN
V+
+IN
OUT
NC
V-
9
HA-5147
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
Q
PLANE
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
C A - B
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S
M
S
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
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