HA7-5170-5 [INTERSIL]
8MHz, Precision, JFET Input Operational Amplifier; 为8MHz ，精密JFET输入运算放大器
| 型号： | HA7-5170-5 |
| 厂家： | 
Intersil |
| 描述： | 8MHz, Precision, JFET Input Operational Amplifier |
| 文件： | 总9页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5170
TM
Data Sheet
July 2000
File Number 2912.4
8MHz, Precision, JFET Input
Operational Amplifier
Features
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 100µV
The Intersil HA-5170 is a precision, JFET input, operational
amplifier which features low noise, low offset voltage and low
offset voltage drift. Constructed using FET/Bipolar
technology, the Intersil Dielectric Isolation (DI) process, and
laser trimming this amplifier offers low input bias and offset
currents. This operational amplifier design also completely
eliminates the troublesome errors due to warm-up drift.
o
• Low Offset Voltage Drift . . . . . . . . . . . . . . . . . . . . .2µV/ C
• Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nV/ Hz
• High Open Loop Gain. . . . . . . . . . . . . . . . . . . . . . 600kV/V
• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz
• Unity Gain Stable
Complementing these excellent input characteristics are
dynamic performance characteristics never before available
from precision operational amplifiers. An 8V/µs slew rate and
8MHz bandwidth allow the designer to extend precision
instrumentation applications in both speed and bandwidth.
These characteristics make the HA-5170 well suited for
precision integrator amplifier designs.
Applications
• High Gain Instrumentation Amplifiers
• Precision Data Acquisition
• Precision Integrators
• Precision Threshold Detectors
• For Further Design Ideas, Refer to Application Note 540
The superior input characteristics also make the HA-5170
ideally suited for transducer signal amplifiers, precision
voltage followers and precision data acquisition systems. For
application assistance, please refer to Application Note
AN540 addressing specifically this device.
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
HA7-5170-5 0 to 75
8 Ld CERDIP
F8.3A
Pinout
HA-5170
(CERDIP)
TOP VIEW
NC
BAL
-IN-
1
2
3
4
8
7
6
5
V+
-
+
OUT
BAL
+IN
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HA-5170
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
CERDIP Package. . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
115
28
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
Temperature Range
o
o
HA-5170-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications
V
= ±15V, Unless Otherwise Specified
SUPPLY
HA-5170-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
MIN
MAX
UNITS
25
Full
Full
25
-
0.1
-
0.3
0.5
5
mV
mV
-
o
Average Offset Voltage Drift (Note 3)
Bias Current
-
2
µV/ C
-
20
0.1
3
100
2
pA
nA
Full
Full
25
-
o
Bias Current Average Drift
Offset Current
-
-
pA/ C
-
3
60
0.1
1
pA
nA
Full
Full
Full
Full
25
-
-
o
Offset Current Average Drift (Note 3)
Common Mode Range
-
0.3
+15.1
-12
80
pA/ C
±10
-
V
V
-
-
-
Differential Input Capacitance
100
-
pF
Ω
10
10
Differential Input Resistance (Note 3)
Input Capacitance (Single Ended)
Input Noise Voltage (Note 3)
25
1 x 10
6 x 10
25
-
-
-
-
-
-
-
-
12
0.5
20
-
pF
0.1Hz to10Hz
f = 10Hz
25
5
µV
P-P
Input Noise Voltage Density (Note 3)
25
150
50
25
-
nV/ Hz
nV/ Hz
nV/ Hz
pA/ Hz
pA/ Hz
pA/ Hz
f = 100Hz
f = 1000Hz
f = 10Hz
25
12
25
10
Input Noise Current Density (Note 3)
25
0.05
0.01
0.01
f = 100Hz
f = 1000Hz
25
-
25
0.1
2
HA-5170
Electrical Specifications
V
= ±15V, Unless Otherwise Specified (Continued)
SUPPLY
HA-5170-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
MIN
MAX
UNITS
V
R
= ±10V,
25
Full
Full
25
300
250
90
1
600
-
-
-
-
-
kV/V
kV/V
dB
OUT
= 2kΩ
L
-
100
-
Common Mode Rejection Ratio
Minimum Stable Gain
Closed Loop Bandwidth
OUTPUT CHARACTERISTICS
Output Voltage Swing
Full Power Bandwidth (Note 4)
Output Current (Note 5)
Output Resistance (Note 3)
TRANSIENT RESPONSE
Rise Time
∆V
CM
= ±10V
V/V
A
= +1
25
4
8
MHz
VCL
R
= 2kΩ
25
25
25
25
±10
80
±10
-
±12
120
±15
45
-
V
kHz
mA
Ω
L
R
= 2kΩ
= ±10V
-
-
L
V
OUT
Open Loop, 100Hz
100
Note 2
Note 2
25
25
25
-
5
-
45
8
100
ns
V/µs
µs
Slew Rate
-
Settling Time (Notes 3, 6)
1
5
POWER SUPPLY CHARACTERISTICS
Supply Current
Full
Full
-
1.9
2.5
-
mA
dB
Power Supply Rejection Ratio (Note 7)
90
105
NOTES:
2. See “Test Circuits and Waveforms” section.
3. Parameter is not 100% tested. 90% of all units meet or exceed these specifications.
Slew Rate
4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- .
2πV
PEAK
5. I
turns on at 23mA.
SC
6. Settling time is measured to 0.1% of final value for a 10V output step and A = -1.
V
7. V+ = +15V, V- = -10V to -20V and V- = -15V, V+ = +10V to +20V.
Test Circuits and Waveforms
V+
7
3
+
IN
+
6
OUT
OUT
-
2
-
2kΩ
50pF
5
1
4
100kΩ
V-
Tested Offset Adjustment Range is |V
+ 1mV| minimum referred to
output. Typical range is ±5mV with R = 1kΩ and ±15mV with
OS
T
R
= 100kΩ.
T
FIGURE 1. V
OS
ADJUSTMENT
FIGURE 2. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
3
HA-5170
Test Circuits and Waveforms (Continued)
Vertical Scale: 5V/Div.
Vertical Scale: 10mV/Div.
Horizontal Scale: 1µs/Div.
Horizontal Scale: 100ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
+15V
100Ω
3
7
3.5kΩ
+
6
OUT
100Ω
2
-
4
4.7µF
-15V
2.5MΩ
10Hz FILTER
= 25,000
A
V
Vertical Scale: 200nV/Div. (Noise Referred to Input)
5mV/Div. at Output, A
= 25,000
VCL
Horizontal Scale: 1s/Div.
FIGURE 3. LOW FREQUENCY NOISE TEST CIRCUIT
HA-5170 LOW FREQUENCY NOISE (0.1HZ TO 10HZ)
4
Schematic Diagram
V+
R
13
R
R
20
Q
R
Q
6
Q
46
5
48
44
R
R
R
Q
R
9
10
11
12
Q
23
Q
36
Q
19
Q
33
Q
Q
14
16
15
Q
Q
Q
Q
4
43
3
21
J
4
Q
Q
47
45
Q
42
R
14
D
1
Q
Q
24
Q
8
-INPUT
Q
Q
NC
5
31
J
J2
Q
1
7
D
C
5
R
18
1
+INPUT
Q
32
J
R
8
37
J
3
D
3
D
4
Q
12
R
19
35
C
3
D
2
OUT
Q
Q
11
10
Q
Q
22
Q
Q
30
26
R
Q
7
13
Q
29
Q
25
Q
27
28
Q
Q
9
21
R
R
16
17
Q
51
Q
34
R
Q
Q
23
6
R
24
Q
40
18
Q
38
Q
39
Q
1
Q
Q
41
5
R
R
15
21
C
2
R
R
4
3
Q
50
Q
49
BAL
BAL
Q
Q
20
17
Q
52
R
R
R
2
22
1
V-
HA-5170
Typical Performace Curves
1000
0.6
0.5
0.4
0.3
0.2
0.1
0
100
0.1
INPUT NOISE CURRENT
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
10
0.01
0.001
INPUT NOISE VOLTAGE
1
-55
-25
0
25
50
75
100
125
1
10
100
1K
10K
100K
o
FREQUENCY (Hz)
TEMPERATURE ( C)
FIGURE 4. INPUT NOISE vs FREQUENCY
FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE OF
REPRESENTATIVE UNITS
10
1
10
5
10mV
1mV
0
0.1
1mV
-5
0.01
0.001
10mV
-10
0
0.5
1
1.5
-50
-25
0
25
50
75
100
125
o
SETTLING TIME (µs)
TEMPERATURE ( C)
FIGURE 6. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
FIGURE 7. BIAS CURRENT vs TEMPERATURE
1.2
3
1.1
1.0
2
BANDWIDTH
o
125 C
o
25 C
o
-55 C
SLEW RATE
1
0.9
0.8
±5
±10
±15
±20
-55
-25
0
25
50
75
100
125
o
SUPPLY VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 8. POWER SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. NORMALIZED AC PARAMETERS vs TEMPERATURE
6
HA-5170
Typical Performace Curves (Continued)
120
120
100
80
100
80
60
40
20
PSRR+
PSRR-
60
40
20
10
100
1K
10K
100K
1M
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 11. COMMON MODE REJECTION RATIO vs FREQUENCY
R
C
= 2kΩ
= 50pF
L
L
R
= 2kΩ
L
28
24
20
16
8
60
50
40
30
20
6
5
4
3
2
1
0
±15V SUPPLIES
±10V SUPPLIES
±5V SUPPLIES
BANDWIDTH
PHASE MARGIN
100
4
10
0
0
10
1000
10000
1K
10K
100K
1M
LOAD CAPACITANCE (pF)
FREQUENCY (Hz)
FIGURE 12. SMALL SIGNAL BANDWIDTH AND PHASE MARGIN
vs LOAD CAPACITANCE
FIGURE 13. OUTPUT VOLTAGE SWING vs FREQUENCY AND
SUPPLY VOLTAGE
35
30
o
T
= 25 C
A
V
= ±15V
= ±10V
S
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5
BANDWIDTH
V
S
V
= ±5V
S
SLEW RATE
0
100
±2
±4
±6 ±8 ±10 ±12 ±14 ±16 ±18 ±20
1K
10K
100K
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (Ω)
FIGURE 14. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE
FIGURE 15. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD
RESISTANCE
7
HA-5170
Typical Performace Curves (Continued)
110
R
C
= 2kΩ
= 50pF
L
L
100
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
0
GAIN
45
90
135
180
PHASE
-10
10
10
100
1K
10K
100K
1M
10M
100M
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 16. OPEN LOOP FREQUENCY RESPONSE
FIGURE 17. CLOSED LOOP FREQUENCY RESPONSE FOR
VARIOUS CLOSED LOOP GAINS
8
HA-5170
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
D
S
M
S
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9
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