HA5022 [INTERSIL]
Dual, 125MHz, Video Current Feedback Amplifier with Disable; 双通道， 125MHz的，视频电流反馈放大器具有禁用
| 型号： | HA5022 |
| 厂家： | 
Intersil |
| 描述： | Dual, 125MHz, Video Current Feedback Amplifier with Disable |
| 文件： | 总16页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA5022
Data Sheet
May 1999
File Number 3392.6
Dual, 125MHz, Video Current Feedback
Amplifier with Disable
Features
• Dual Version of HA-5020
The HA5022 is a dual version of the popular Intersil HA5020.
It features wide bandwidth and high slew rate, and is
optimized for video applications and gains between 1 and
10. It is a current feedback amplifier and thus yields less
bandwidth degradation at high closed loop gains than
voltage feedback amplifiers.
• Individual Output Enable/Disable
• Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800µV
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/µs
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%
• Differential Phase . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA
• ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
• Guaranteed Specifications at ±5V Supplies
The low differential gain and phase, 0.1dB gain flatness, and
ability to drive two back terminated 75Ω cables, make this
amplifier ideal for demanding video applications.
The HA5022 also features a disable function that
significantly reduces supply current while forcing the output
to a true high impedance state. This functionality allows 2:1
video multiplexers to be implemented with a single IC.
Applications
The current feedback design allows the user to take
• Video Multiplexers; Video Switching and Routing
• Video Gain Block
advantage of the amplifier’s bandwidth dependency on the
feedback resistor. By reducing R , the bandwidth can be
F
increased to compensate for decreases at higher closed
loop gains or heavy output loads.
• Video Distribution Amplifier/RGB Amplifier
• Flash A/D Driver
Ordering Information
• Current to Voltage Converter
• Medical Imaging
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
16 Ld PDIP
16 Ld SOIC
• Radar and Imaging Systems
HA5022IP
-40 to 85
-40 to 85
E16.3
M16.15
HA5022IB
Pinout
HA5022EVAL
High Speed Op Amp DIP Evaluation Board
HA5022
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
-IN1
+IN1
DIS1
V-
OUT1
NC
-
+
NC
V+
DIS2
+IN2
-IN2
NC
NC
NC
+
-
OUT2
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HA5022
Absolute Maximum Ratings
Thermal Information
o
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 36V
DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . ±V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
Output Current (Note 4) . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating (Note 3)
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
SUPPLY
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
115
o
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . .175 C
Maximum Junction Temperature (Plastic Package, Note 1) . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Human Body Model (Per MIL-STD-883 Method 3015.7) . . 2000V
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±4.5V to ±15V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
o
o
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175 C for die, and below 150 C
for plastic packages. See Application Information section for safe operating area information.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
3. The non-inverting input of unused amplifiers must be connected to GND.
4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 15mA for maximum reliability.
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified
SUPPLY
F
V
L
L
(NOTE 11)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Input Offset Voltage (V
)
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
25
Full
Full
Full
25
-
0.8
-
3
5
mV
mV
mV
IO
-
Delta V Between Channels
IO
-
1.2
5
-
3.5
-
o
Average Input Offset Voltage Drift
-
µV/ C
V
V
Common Mode Rejection Ratio
Note 5
53
-
dB
dB
IO
IO
Full
25
50
-
-
Power Supply Rejection Ratio
±3.5V ≤ V ≤ ±6.5V
60
-
-
dB
S
Full
Full
25
55
-
-
dB
Input Common Mode Range
Note 5
Note 5
±2.5
-
-
V
Non-Inverting Input (+IN) Current
-
-
-
-
-
-
-
-
-
-
-
-
3
-
8
µA
Full
25
20
0.15
0.5
0.1
0.3
12
30
15
30
0.4
1.0
µA
+IN Common Mode Rejection
1
-
µA/V
µA/V
µA/V
µA/V
µA
(+I
=
)
BCMR
+R
Full
25
-
IN
+IN Power Supply Rejection
Inverting Input (-IN) Current
±3.5V ≤ V ≤ ±6.5V
-
S
Full
25, 85
-40
25, 85
-40
25
-
4
10
6
10
-
µA
Delta -IN BIAS Current Between
Channels
µA
µA
-IN Common Mode Rejection
Note 5
µA/V
µA/V
Full
-
2
HA5022
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified (Continued)
SUPPLY
F
V
L
L
(NOTE 11)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
MIN
TYP
-
MAX
UNITS
µA/V
-IN Power Supply Rejection
±3.5V ≤ V ≤ ±6.5V
A
A
B
B
B
25
Full
25
-
-
-
-
-
0.2
S
-
0.5
µA/V
Input Noise Voltage
f = 1kHz
f = 1kHz
f = 1kHz
4.5
2.5
25.0
-
-
-
nV/√Hz
pA/√Hz
pA/√Hz
+Input Noise Current
-Input Noise Current
25
25
TRANSFER CHARACTERISTICS
Transimpedance
Note 16
A
A
A
A
A
A
25
Full
25
1.0
0.85
70
-
-
-
-
-
-
-
-
-
-
-
-
MΩ
MΩ
dB
Open Loop DC Voltage Gain
Open Loop DC Voltage Gain
R
R
= 400Ω, V
= 100Ω, V
= ±2.5V
= ±2.5V
L
L
OUT
Full
25
65
dB
50
dB
OUT
Full
45
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
R
= 150Ω
= 150Ω
A
A
B
A
A
25
±2.5
±2.5
±16.6
±40
-
±3.0
±3.0
±20.0
±60
-
-
-
V
L
Full
Full
Full
Full
V
Output Current
-
mA
mA
µA
L
Output Current, Short Circuit
Output Current, Disabled
V
= ±2.5V, V
OUT
= 0V
-
IN
V
= ±2.5V, V = 0V,
IN
2
OUT
DISABLE = 0V
Output Disable Time
Note 12
B
B
B
25
25
25
-
-
-
40
40
15
-
-
-
µs
ns
pF
Output Enable Time
Note 13
Output Capacitance, Disabled
Note 14
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
A
A
A
A
25
5
-
-
15
10
V
Quiescent Supply Current
Full
Full
Full
7.5
5
mA/Op Amp
mA/Op Amp
mA
Supply Current, Disabled
DISABLE = 0V
DISABLE = 0V
-
7.5
1.5
-
1.0
Disable Pin Input Current
Minimum Pin 8 Current to Disable
Maximum Pin 8 Current to Enable
Note 6
Note 7
A
A
Full
Full
350
-
-
-
-
µA
µA
20
AC CHARACTERISTICS (A = +1)
V
Slew Rate
Note 8
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
275
400
28
6
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
Note 9
22
-
Note 10
Note 10
Note 10
Fall Time
-
6
ns
Propagation Delay
Overshoot
-
6
ns
-
4.5
125
50
75
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.25%
V
= 100mV
-
MHz
ns
OUT
2V Output Step
2V Output Step
-
-
ns
3
HA5022
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified (Continued)
SUPPLY
F
V
L
L
(NOTE 11)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (A = +2, R = 681Ω)
V
F
Slew Rate
Note 8
B
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
475
26
-
-
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
Note 9
Note 10
Note 10
Note 10
6
Fall Time
6
ns
Propagation Delay
Overshoot
6
ns
12
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.25%
Gain Flatness
V
= 100mV
95
MHz
ns
OUT
2V Output Step
2V Output Step
5MHz
50
100
0.02
0.07
ns
dB
dB
20MHz
AC CHARACTERISTICS (A = +10, R = 383Ω)
V
F
Slew Rate
Note 8
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
350
475
38
8
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
Note 9
28
-
Note 10
Note 10
Note 10
Fall Time
-
9
ns
Propagation Delay
Overshoot
-
9
ns
-
1.8
65
75
130
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.1%
V
= 100mV
-
MHz
ns
OUT
2V Output Step
2V Output Step
-
-
ns
VIDEO CHARACTERISTICS
Differential Gain (Note 15)
Differential Phase (Note 15)
R
R
= 150Ω
= 150Ω
B
B
25
25
-
-
0.03
0.03
-
-
%
L
L
Degrees
NOTES:
5. V
o
= ±2.5V. At -40 C Product is tested at V
= ±2.25V because short test duration does not allow self heating.
CM
CM
6. R = 100Ω, V = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is
L
IN
considered disabled when -10mV ≤ V
≤ +10mV.
OUT
7. V = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA5022 remaining enabled. The HA5022 is
IN
considered disabled when the supply current has decreased by at least 0.5mA.
8. V
9.
switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
Slew Rate
OUT
.
= 2V
----------------------------
FPBW =
; V
PEAK
2πV
PEAK
10. R = 100Ω, V
= 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
11. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
L
OUT
12. V = +2V, DISABLE = +5V to 0V. Measured from the 50% point of DISABLE to V
IN
= 0V.
= 2V.
OUT
13. V = +2V, DISABLE = 0V to +5V. Measured from the 50% point of DISABLE to V
IN
OUT
14. V = 0V, Force V
IN OUT
from 0V to ±2.5V, t = t = 50ns, DISABLE = 0V.
R F
15. Measured with a VM700A video tester using an NTC-7 composite VITS.
o
16. V
= ±2.5V. At -40 C Product is tested at V
= ±2.25V because short test duration does not allow self heating.
OUT
OUT
4
HA5022
Test Circuits and Waveforms
+
-
DUT
50Ω
HP4195
NETWORK
ANALYZER
50Ω
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
(NOTE 17)
100Ω
(NOTE 17)
100Ω
DUT
V
+
-
IN
DUT
V
OUT
V
+
-
IN
V
OUT
50Ω
R
L
400Ω
50Ω
R
100Ω
L
R , 681Ω
F
R
681Ω
I
R , 1kΩ
F
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT
NOTE:
17. A series input resistor of ≥100Ω is recommended to limit input currents in case input signals are present before the HA5022 is powered up.
Vertical Scale: V = 100mV/Div., V
= 100mV/Div.
Horizontal Scale: 20ns/Div.
Vertical Scale: V = 1V/Div., V
= 1V/Div.
Horizontal Scale: 50ns/Div.
IN OUT
IN OUT
FIGURE 4. SMALL SIGNAL RESPONSE
FIGURE 5. LARGE SIGNAL RESPONSE
5
Schematic Diagram (One Amplifier of Two)
V+
R
800
R
2.5K
R
6
15K
R
820
2
5
10
R
R
400
R
R
15
400
19
33
29
9.5
D
Q
Q
P9
2
P8
R
2K
27
200
Q
P19
Q
Q
P14
P11
Q
P18
R
Q
31
P1
Q
R
11
1K
P5
R
280
5
R
18
17
280
R
24
140
Q
Q
N5
P16
6
Q
P20
Q
P10
R
20
140
Q
R
N12
8
1.25K
Q
P15
C
1.4pF
1
Q
N8
Q
P2
Q
P12
R
20
28
R
60K
1
Q
P6
Q
Q
Q
P3
N6
-IN
R
R
7
15K
12
Q
P17
Q
280
N1
Q
Q
N13
P4
+IN
Q
N17
DIS
0
R
25
P13
R
6K
3
20
C
1.4pF
2
Q
N15
Q
N2
R
21
140
Q
Q
R
N10
N21
Q
R
R
R
14
280
P7
22
280
25
140
D
1
Q
N4
32
Q
N14
5
Q
N16
Q
N18
R
1K
Q
13
Q
Q
N19
N20
N3
Q
N7
R
7
30
R
R
R
R
26
200
16
400
23
400
26
200
OUT
R
800
R
4
33
800
R
820
9
Q
Q
N11
N9
V-
HA5022
as short as possible to minimize the capacitance from this
node to ground.
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 11 and Figure 12 in the Typical Performance
Curves section, illustrate the performance of the HA5022 in
various closed loop gain configurations. Although the
bandwidth dependency on closed loop gain isn’t as severe
as that of a voltage feedback amplifier, there can be an
appreciable decrease in bandwidth at higher gains. This
decrease may be minimized by taking advantage of the
current feedback amplifier’s unique relationship between
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
100Ω
R
V
+
-
IN
V
OUT
R
T
bandwidth and R . All current feedback amplifiers require a
C
F
L
feedback resistor, even for unity gain applications, and R , in
F
conjunction with the internal compensation capacitor, sets
the dominant pole of the frequency response. Thus, the
R
F
R
I
amplifier’s bandwidth is inversely proportional to R . The
F
HA5022 design is optimized for a 1000Ω R at a gain of +1.
F
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
Decreasing R in a unity gain application decreases stability,
F
resulting in excessive peaking and overshoot. At higher
gains the amplifier is more stable, so R can be decreased
in a trade-off of stability for bandwidth.
The selection criteria for the isolation resistor is highly
dependent on the load, but 27Ω has been determined to be
a good starting value.
F
The table below lists recommended R values for various
F
gains, and the expected bandwidth.
Power Dissipation Considerations
Due to the high supply current inherent in dual amplifiers,
care must be taken to insure that the maximum junction
GAIN
(A
BANDWIDTH
(MHz)
)
R (Ω)
F
CL
temperature (T see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient
temperature versus supply voltage for the available package
-1
+1
750
1000
681
100
125
95
J,
+2
styles (PDIP, SOIC). At V = ±5V quiescent operation both
S
+5
1000
383
52
package styles may be operated over the full industrial range
+10
-10
65
o
o
of -40 C to 85 C. It is recommended that thermal
calculations, which take into account output power, be
performed by the designer.
750
22
PC Board Layout
140
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
130
PDIP
120
110
100
90
Attention must be given to decoupling the power supplies. A
large value (10µF) tantalum or electrolytic capacitor in
parallel with a small value (0.1µF) chip capacitor works well
in most cases.
SOIC
80
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
FIGURE 7. MAXIMUM OPERATING AMBIENT
TEMPERATURE vs SUPPLY VOLTAGE
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is
Enable/Disable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical
specifications table being valid and applicable. When
recommended that the ground plane be removed under
traces connected to -IN, and that connections to -IN be kept
7
HA5022
disabled the amplifier output assumes a true high
impedance state and the supply current is reduced
significantly.
position 1. At position 1 the switch pulls the disable pin up to
the plus supply rail thereby enabling the amplifier. Since all
of the actual signal switching takes place within the amplifier,
it’s differential gain and phase parameters, which are 0.03%
and 0.03 degrees respectively, determine the circuit’s
The circuit shown in Figure 8 is a simplified schematic of the
enable/disable function. The large value resistors in series
with the DISABLE pin makes it appear as a current source to
the driver. When the driver pulls this pin low current flows out
of the pin and into the driver. This current, which may be as
large as 350µA when external circuit and process variables
are at their extremes, is required to insure that point “A”
achieves the proper potential to disable the output. The
driver must have the compliance and capability of sinking all
of this current.
performance. The other circuit, U , operates in a similar
1B
manner.
When the plus supply rail is 5V the disable pin can be driven
by a dedicated TTL gate as discussed earlier. If a multiplexer
IC or its equivalent is used to select channels its logic must
be break before make. When these conditions are satisfied
the HA5022 is often used as a remote video multiplexer, and
the multiplexer may be extended by adding more amplifier
ICs.
V+
Low Impedance Multiplexer
R
15K
R
6
33
R
10
Two common problems surface when you try to multiplex
multiple high speed signals into a low impedance source
such as an A/D converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA5022, eliminates the
multiplexer problems because the external mux chip is not
needed, and the HA5022 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
Q
P18
D
1
R
8
R
15K
7
A
Q
P3
ENABLE/DISABLE INPUT
FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE
FUNCTION
When V
CC
is +5V the DISABLE pin may be driven with a
dedicated TTL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D will not
turn on, and the TTL gate will sink enough current to keep
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 75Ω is typical for video
applications. Since the drivers usually are terminated in their
characteristic impedance the input gain is 0.5, thus the
1
point “A” at its proper voltage. When V
is greater than +5V
CC
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than V
amplifiers, U , are configured in a gain of +2 to set the circuit
2
.
CC
gain equal to one. Resistors R and R determine the
2
3
amplifier gain, and if a different gain is desired R should be
2
Referring to Figure 8, it can be seen that R will act as a pull-
6
changed according to the equation G = (1 + R /R ). R sets
3
2
3
up resistor to +V
CC
if the DISABLE pin is left open. In those
the frequency response of the amplifier so you should refer
to the manufacturers data sheet before changing its value.
cases where the enable/disable function is not required on
all circuits some circuits can be permanently enabled by
letting the DISABLE pin float. If a driver is used to set the
enable/disable level, be sure that the driver does not sink
more than 20µA when the DISABLE pin is at a high level.
TTL gates, especially CMOS versions, do not violate this
criteria so it is permissible to control the enable/disable
function with TTL.
R , C and D are an asymmetrical charge/discharge time
5
1
1
circuit which configures U as a break before make switch to
1
prevent both amplifiers from being active simultaneously. If
this design is extended to more channels the drive logic
must be designed to be break before make. R is enclosed
4
in the feedback loop of the amplifier so that the large open
loop amplifier gain of U will present the load with a small
2
closed loop output impedance while keeping the amplifier
stable for all values of load capacitance.
Typical Applications
Two Channel Video Multiplexer
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved.The frequency and gain
characteristics of the circuit are now those of the amplifier
independent of any multiplexing action; thus, problem two
has been solved. The multiplexer transition time is
Referring to the amplifier U in Figure 9, R terminates the
1A
1
cable in its characteristic impedance of 75Ω, and R back
4
terminates the cable in its characteristic impedance. The
amplifier is set up in a gain configuration of +2 to yield an
overall network gain of +1 when driving a double terminated
cable. The value of R can be changed if a different network
3
approximately 15µs with the component values shown.
gain is desired. R holds the disable pin at ground thus
5
inhibiting the amplifier until the switch, S , is thrown to
1
8
HA5022
(NOTE 17)
R
75
4
U
100Ω
1A
16
1
VIDEO INPUT #1
VIDEO OUTPUT
TO 75Ω LOAD
+
-
R
2
1
3
75
R
5
R
2000
2
R
681
3
681
1
2
R
11
100
(NOTE 17)
R
75
9
U
100Ω
1B
7
6
3
+5V
10
VIDEO INPUT #2
+
-
S
1
ALL
OFF
R
6
5
75
R
10
2000
R
7
R
681
8
681
+5V IN
+5V
-5V IN
0.1µF
-5V
10µF
+
0.1µF
10µF
+
NOTES:
18. U is HA5022.
1
19. All resistors in Ω.
20. S is break before make.
1
21. Use ground plane.
FIGURE 9. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER
R
3A
681
INPUT B
R
1A
681
R
R
1A
75
4A
27
U
2A
16
-
1
2
+
4
-5V
0.01µF
INPUT A
100Ω
(NOTE 17)
3
D
1A
1N4148
R
1B
75
R
5A
2000
R
3B
681
U
1C
R
681
C
2B
1A
0.047µF
R
4B
27
U
2B
CHANNEL
SWITCH
7
6
10
-
OUTPUT
+
13
5
+5V
0.01µF
100Ω
(NOTE 17)
R
5B
2000
U
1D
U
1B
U
C
1A
1B
INHIBIT
0.047µF
D
1B
1N4148
R
6
100K
NOTES:
22. U : HA5022.
2
23. U : CD4011.
1
FIGURE 10. LOW IMPEDANCE MULTIPLEXER
9
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified
V F L A
SUPPLY
5
5
V
C
= 0.2V
P-P
OUT
= 10pF
V
C
R
= 0.2V
P-P
= 10pF
= 750Ω
OUT
A
= +1, R = 1kΩ
4
3
V
F
4
3
L
L
F
A
= 2, R = 681Ω
V
F
A
= -1
= -2
V
2
A
= 5, R = 1kΩ
2
V
F
1
1
A
V
0
0
-1
-1
-2
-3
-4
-2
-3
-4
A
= -10
V
A
= 10, R = 383Ω
F
V
A
= -5
V
-5
-5
2
10
100
200
2
10
FREQUENCY (MHz)
100
200
FREQUENCY (MHz)
FIGURE 12. INVERTING FREQUENCY RESPONSE
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE
140
V
C
= 0.2V
P-P
OUT
= 10pF
180
135
90
0
-45
A
= +1, R = 1kΩ
F
V
L
A
= +1
V
130
120
-90
A
= -1, R = 750Ω
F
V
45
0
-135
-100
-225
A
= +10, R = 383Ω
F
V
10
-3dB BANDWIDTH
-45
-90
-270
A
= -10, R = 750Ω
F
V
5
0
-135
-180
-315
-360
V
= 0.2V
P-P
OUT
= 10pF
C
GAIN PEAKING
700
L
2
10
FREQUENCY (MHz)
100
200
500
900
1100
1300
1500
FEEDBACK RESISTOR (Ω)
FIGURE 14. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 13. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY
100
130
V
C
= 0.2V
P-P
OUT
= 10pF
L
A
= +2
V
120
95
90
-3dB BANDWIDTH
110
100
6
-3dB BANDWIDTH
10
4
2
5
0
V
C
= 0.2V
P-P
90
80
OUT
= 10pF
GAIN PEAKING
L
A
= +1
V
GAIN PEAKING
0
1000
0
200
400
600
800
350
500
650
800
950
1100
LOAD RESISTOR (Ω)
FEEDBACK RESISTOR (Ω)
FIGURE 16. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
FIGURE 15. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
10
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
16
80
V
C
= 0.1V
= 10pF
OUT
P-P
V
= 0.2V
P-P
= 10pF
= +10
OUT
L
C
A
L
V
= ±5V, A = +2
V
V
SUPPLY
60
12
40
20
0
6
V
= ±15V, A = +2
V
SUPPLY
V
= ±5V, A = +1
SUPPLY
V
V
= ±15V, A = +1
V
SUPPLY
0
200
350
500
650
800
950
0
200
400
600
800
1000
FEEDBACK RESISTOR (Ω)
LOAD RESISTANCE (Ω)
FIGURE 18. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE
FIGURE 17. BANDWIDTH vs FEEDBACK RESISTANCE
0.08
0.10
FREQUENCY = 3.58MHz
FREQUENCY = 3.58MHz
0.08
0.06
0.04
R
= 75Ω
L
0.06
0.04
R
= 150Ω
R
L
= 150Ω
L
R
= 75Ω
L
0.02
0.00
0.02
0.00
R
= 1kΩ
L
R
= 1kΩ
L
3
5
7
9
11
13
15
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 20. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
FIGURE 19. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE
-40
A
= +1
V
C
= 2.0V
V
OUT
= 30pF
P-P
0
-10
-20
-30
L
-50
-60
HD2
3RD ORDER IMD
-40
-50
CMRR
-70
HD2
HD3
-60
-70
-80
-80
-90
NEGATIVE PSRR
POSITIVE PSRR
0.1
HD3
0.3
1
10
0.001
0.01
1
10
30
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 22. REJECTION RATIOS vs FREQUENCY
FIGURE 21. DISTORTION vs FREQUENCY
11
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
12
8.0
R
= 100Ω
= 1.0V
= +1
L
R
= 100Ω
LOAD
V
OUT
P-P
V
= 1.0V
OUT
P-P
A
V
10
7.5
A
= +10, R = 383Ω
F
V
8
7.0
6.5
6.0
A
= +2, R = 681Ω
F
V
6
4
A
= +1, R
kΩ
=1
7
V
F
-50
-25
0
25
50
75
100
125
3
5
9
11
13
15
o
SUPPLY VOLTAGE (±V)
TEMPERATURE ( C)
FIGURE 23. PROPAGATION DELAY vs TEMPERATURE
FIGURE 24. PROPAGATION DELAY vs SUPPLY VOLTAGE
0.8
500
V
C
= 0.2V
P-P
V
= 2V
P-P
OUT
= 10pF
OUT
0.6
0.4
0.2
0
450
400
350
300
250
L
+ SLEW RATE
A = +2, R = 681Ω
V
F
- SLEW RATE
-0.2
-0.4
-0.6
A = +5, R = 1kΩ
V
F
A
= +1, R = 1kΩ
F
V
200
150
100
-0.8
-1.0
-1.2
A
= +10, R = 383Ω
V
F
5
10
15
20
25
30
-50
-25
0
25
50
75
100
125
o
FREQUENCY (MHz)
TEMPERATURE ( C)
FIGURE 25. SLEW RATE vs TEMPERATURE
FIGURE 26. NON-INVERTING GAIN FLATNESS vs FREQUENCY
0.8
100
80
1000
800
V
C
R
= 0.2V
P-P
OUT
L
F
A
= +10, R = 383Ω
F
V
0.6
0.4
= 10pF
= 750Ω
-INPUT NOISE CURRENT
0.2
A
= -1
= -5
V
0
600
60
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
+INPUT NOISE CURRENT
INPUT NOISE VOLTAGE
400
40
A
V
200
0
20
0
A
= -2
V
A
= -10
V
5
10
15
20
25
30
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (kHz)
FIGURE 27. INVERTING GAIN FLATNESS vs FREQUENCY
FIGURE 28. INPUT NOISE CHARACTERISTICS
12
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
1.5
2
0
1.0
-2
-4
0.5
0.0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 30. +INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 29. INPUT OFFSET VOLTAGE vs TEMPERATURE
4000
22
3000
2000
1000
20
18
16
-60 -40 -20
0
20
40
60
o
80
100 120 140
-60 -40 -20
0
20
40
60
o
80
100 120 140
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 31. -INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 32. TRANSIMPEDANCE vs TEMPERATURE
74
25
+PSRR
-PSRR
72
70
68
66
64
62
60
o
125 C
20
o
55 C
15
10
CMRR
o
25 C
58
-100
5
3
4
5
6
7
8
9
10 11 12
13 14 15
-50
0
50
100
150
200
250
o
SUPPLY VOLTAGE (±V)
TEMPERATURE ( C)
FIGURE 34. REJECTION RATIO vs TEMPERATURE
FIGURE 33. SUPPLY CURRENT vs SUPPLY VOLTAGE
13
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
40
4.0
+10V
+15V
30
20
+5V
3.8
10
0
3.6
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
-60 -40 -20
0
20
40
60
80
100 120 140
o
DISABLE INPUT VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 35. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE
30
FIGURE 36. OUTPUT SWING vs TEMPERATURE
1.2
1.1
V
= ±15V
S
20
10
1.0
V
= ±10V
S
0.9
0.8
V
= ±4.5V
S
0
0.01
0.10
1.00
10.00
-60 -40 -20
0
20
40
60
80
100 120 140
o
LOAD RESISTANCE (kΩ)
TEMPERATURE ( C)
FIGURE 38. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS vs TEMPERATURE
FIGURE 37. OUTPUT SWING vs LOAD RESISTANCE
30
1.5
o
-55 C
25
20
1.0
o
25 C
15
10
0.5
0.0
o
125 C
5
3
4
5
6
7
8
9
10 11 12 13 14 15
-60 -40 -20
20
40
60
80 100 120 140
0
o
SUPPLY VOLTAGE (±V)
TEMPERATURE ( C)
FIGURE 39. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS vs TEMPERATURE
FIGURE 40. DISABLE SUPPLY CURRENT vs SUPPLY VOLTAGE
14
HA5022
o
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
-30
32
30
20
18
A
= +1
= 2V
V
V
OUT
P-P
ENABLE
-40
-50
-60
-70
-80
28
26
24
22
16
14
12
10
ENABLE
20
8
18
16
14
12
6
4
2
0
DISABLE
DISABLE
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
0.1
1
10
30
FREQUENCY (MHz)
OUTPUT VOLTAGE (V)
FIGURE 41. CHANNEL SEPARATION vs FREQUENCY
FIGURE 42. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
10
DISABLE = 0V
0
R
= 100Ω
V
= 5V
P-P
L
1
IN
R
= 750Ω
F
-10
-20
-30
0.1
0.01
180
135
90
45
0
0.001
-40
-50
-60
-70
-80
-45
-90
-135
100
0.1
1
10
20
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 43. DISABLE FEEDTHROUGH vs FREQUENCY
FIGURE 44. TRANSIMPEDANCE vs FREQUENCY
10
1
R
= 400Ω
L
0.1
180
135
90
0.01
0.001
45
0
-45
-90
-135
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 45. TRANSIMPEDENCE vs FREQUENCY
15
HA5022
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
1650µm x 2540µm x 483µm
Type: Nitride
Thickness: 4kÅ ±0.4kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AlCu (1%)
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AlCu (1%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
124
PROCESS:
High Frequency Bipolar Dielectric Isolation
SUBSTRATE POTENTIAL (POWERED UP):
V-
Metallization Mask Layout
HA5022
-IN1
OUT1
V+
+IN1
DIS1
V-
NC
DIS2
+IN2
-IN2
OUT2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
16
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