EL5220TIYZ-T13 [INTERSIL]
12MHz Rail-to-Rail Input-Output Operational Amplifier; 12MHz的轨至轨输入输出运算放大器
| 型号： | EL5220TIYZ-T13 |
| 厂家： | 
Intersil |
| 描述： | 12MHz Rail-to-Rail Input-Output Operational Amplifier |
| 文件： | 总15页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12MHz Rail-to-Rail Input-Output Operational Amplifier
EL5220T
Features
• 12MHz (-3dB) Bandwidth
The EL5220T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5220T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
• 4.5V to 19V Maximum Supply Voltage Range
• 12V/μs Slew Rate
• 550μA Supply Current (per Amplifier)
• ±65mA Continuous Output Current
• ±200mA Output Short Circuit Current
• Unity-gain Stable
The maximum operating voltage range is from 4.5V to
19V. It can be configured for single or dual supply
operation, and typically consumes only 550μA per
amplifier. The EL5220T has an output short circuit
capability of ±200mA and a continuous output current
capability of ±65mA.
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
The EL5220T features a slew rate of 12V/μs. Also, the
device provides common mode input capability beyond
the supply rails, rail-to-rail output capability, and a
bandwidth of 12MHz (-3dB). This enables the amplifiers
to offer maximum dynamic range at any supply voltage.
These features make the EL5220T an ideal amplifier
• -40°C to +85°C Ambient Temperature Range
• Pb-free (RoHS Compliant)
Applications*(see page 13)
• TFT-LCD Panels
solution for use in TFT-LCD panels as a V
or static
COM
• V
Amplifiers
COM
gamma buffer, and in high speed filtering and signal
conditioning applications. Other applications include
battery power and portable devices, especially where low
power consumption is important.
• Static Gamma Buffers
• Electronics Notebooks
• Electronics Games
The EL5220T is available in an 8 Ld MSOP package, and a
thermally enhanced 8 Ld DFN package. Both feature a
standard operational amplifier pinout. The devices
operate over an ambient temperature range of -40°C to
+85°C.
• Touch-screen Displays
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Sampling ADC Amplifiers
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffer
5
10kΩ
PANEL
CAPACITANCE
+15V
0
+
EL5220T
VOUTA
VINA-
VS+
0.1μF
+15V
4.7μF
1kΩ
VOUTB
-5
560Ω
150Ω
0
PANEL
CAPACITANCE
VINB-
VINA+
-10
-15
V
= ±5V
= 1
= 8pF
0
S
A
VS-
VINB+
V
L
C
TFT-LCD
PANEL
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. TYPICAL TFT-LCD V
APPLICATION
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS R
L
COM
May 4, 2010
FN6892.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5220T
Pin Configuration
EL5220T
EL5220T
(8 LD DFN)
TOP VIEW
(8 LD MSOP)
TOP VIEW
VOUTA 1
VINA- 2
VINA+ 3
VS- 4
8 VS+
VOUTA
VS+
1
2
3
4
8
7
6
5
-
+
-
7 VOUTB
6 VINB-
5 VINB+
VINA-
VINA+
VS-
VOUTB
VINB-
VINB+
PD
+
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
Pin Descriptions
PIN NUMBER
PIN
EQUIVALENT
(MSOP, DFN)
NAME
FUNCTION
CIRCUIT
1
2
VOUTA
VINA-
VINA+
VS-
Amplifier A output
(Reference Circuit 1)
(Reference Circuit 2)
(Reference Circuit 2)
Amplifier A inverting input
3
Amplifier A non-inverting input
Negative power supply
4
5
VINB+
VINB-
VOUTB
VS+
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
6
7
8
Positive power supply
PD
Thermal Pad Functions as a heat sink. Electrically connected to VS-. Connect the thermal
pad to VS- plane on the PCB for optimum thermal performance.
V
S+
V
V
S+
V
OUTx
V
INx
S-
GND
V
S-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL5220TILZ-T13 (Note 1)
EL5220TIYZ
20T
8 Ld DFN
L8.2x3
BBBMA
BBBMA
BBBMA
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
M8.118A
M8.118A
M8.118A
EL5220TIYZ-T7 (Note 1)
EL5220TIYZ-T13 (Note 1)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5220T. For more information on MSL please see
techbrief TB363.
FN6892.0
May 4, 2010
2
EL5220T
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . .+19.8V
Thermal Resistance (Typical)
θ (°C/W) θ (°C/W)
JA JC
S
S
Input Voltage Range (V ) . . . V - - 0.5V, V + + 0.5V
, V
INx+ INx- S S
8 Ld MSOP (Notes 6, 7) . . . . . . . .
8 Ld DFN (Notes 4, 5). . . . . . . . . .
170
58
60
8
Input Differential Voltage (V
- V
) . . . . . . . . . . . . . .
INx-
INx+
. . . . . . . . . . . . . . . . . . . . . . . (V + + 0.5V)-(V - - 0.5V)
S
S
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature. . . . . . . . . -40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . .See Figures 32 and 33
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Continuous Output Current . . . . . . . . . . .±65mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
JA
TB379 for details.
7. For θ , the “case temp” location is taken at the package top center.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 10kΩ to 0V, T = +25°C, unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 0V
3
5
3
2
1
2
18
50
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 8)
8 Ld MSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 0V
B
CM
R
C
Input Impedance
GΩ
IN
Input Capacitance
pF
IN
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open Loop Gain
-5.5
50
+5.5
V
CMRR
For V
from -5.5V to +5.5V
-4.5V ≤ V ≤ +4.5V
75
dB
INx
A
75
105
dB
VOL
OUTx
OUTPUT CHARACTERISTICS
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
-4.94 -4.85
V
V
OL
OH
SC
L
V
I = +5mA
4.85 4.94
±200
L
I
V
= 0V, Source: V
OUTx
short to V -,
mA
CM
Sink: V
S
short to V +
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
19
V
S
S
I
Supply Current (Per Amplifier)
Power Supply Rejection Ratio
V
= 0V, No load
550
750
μA
dB
S
CM
PSRR
Supply is moved from ±2.25V to ±9.5V 60
75
FN6892.0
May 4, 2010
3
EL5220T
Electrical Specifications V + = +5V, V - = -5V, R = 10kΩ to 0V, T = +25°C, unless otherwise specified. (Continued)
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 9)
-4.0V ≤ V
≤ +4.0V, 20% to 80%
12
V/μs
OUTx
t
Settling to +0.1% (Note 10)
A = +1, V
= 2V step,
500
ns
S
V
OUTx
L
R = 10kΩ, C = 8pF
L
BW
-3dB Bandwidth
R = 10kΩ, C = 8pF
12
8
MHz
MHz
L
L
GBWP
Gain-Bandwidth Product
A = -50, R = 5kΩ, R = 100Ω
V F G
R = 10kΩ, C = 8pF
L
L
PM
CS
Phase Margin
A = -50, R = 5kΩ, R = 100Ω
50
85
°
V
F
G
R = 10kΩ, C = 8pF
L
L
Channel Separation
f = 5MHz
dB
Electrical Specifications V + = +5V, V - = 0V, R = 10kΩ to 2.5V, T = +25°C, unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
INPUT CHARACTERISTICS
Input Offset Voltage
V
V
= 2.5V
3
5
3
2
1
2
18
50
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 8) 8 Ld MSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 2.5V
B
CM
R
C
Input Impedance
GΩ
IN
Input Capacitance
pF
IN
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open Loop Gain
-0.5
45
+5.5
V
CMRR
For V
from -0.5V to +5.5V
70
dB
INx
A
0.5V ≤ V
≤ + 4.5V
OUTx
75
105
dB
VOL
OUTPUT CHARACTERISTICS
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -2.5mA
30
150
mV
V
OL
OH
SC
L
V
I = +2.5mA
4.85 4.97
±125
L
I
V
= 2.5V, Source: V
OUTx
short to V -,
mA
CM
Sink: V
S
short to V +
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
19
V
S
S
I
Supply Current (Per Amplifier)
Power Supply Rejection Ratio
V
= 2.5V, No load
550
750
μA
dB
S
CM
PSRR
Supply is moved from 4.5V to 19V
60
75
DYNAMIC PERFORMANCE
SR Slew Rate (Note 9)
1V ≤ V
≤ 4V, 20% to 80%
12
V/μs
OUTx
t
Settling to +0.1% (Note 10)
A = +1, V
= 2V step,
500
ns
S
V
OUTx
L
R = 10kΩ, C = 8pF
L
BW
-3dB Bandwidth
R = 10kΩ, C = 8pF
12
8
MHz
MHz
L
L
GBWP
Gain-Bandwidth Product
A = -50, R = 5kΩ, R = 100Ω
V F G
R = 10kΩ, C = 8pF
L
L
PM
CS
Phase Margin
A = -50, R = 5kΩ, R = 100Ω
50
85
°
V
F
G
R = 10kΩ, C = 8pF
L
L
Channel Separation
f = 5MHz
dB
FN6892.0
May 4, 2010
4
EL5220T
Electrical Specifications V + = +18V, V - = 0V, R = 10kΩ to 9V, T = +25°C, unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP MAX UNIT
INPUT CHARACTERISTICS
Input Offset Voltage
V
V
= 9V
5
6
4
2
1
2
18
50
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 8) 8 Ld MSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 9V
B
CM
R
C
Input Impedance
GΩ
IN
Input Capacitance
pF
IN
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open Loop Gain
-0.5
53
+18.5
V
CMRR
For V
from -0.5V to +18.5V
78
90
dB
INx
A
0.5V ≤ V
≤ 17.5V
OUTx
75
dB
VOL
OUTPUT CHARACTERISTICS
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -9mA
120
150
mV
V
OL
OH
SC
L
V
I = +9mA
17.85 17.88
±200
L
I
V
= 9V, Source: V
OUTx
short to V -,
mA
CM
Sink: V
S
short to V +
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
19
V
S
S
I
Supply Current (Per Amplifier)
Power Supply Rejection Ratio
V
= 9V, No load
650
850
μA
dB
S
CM
PSRR
Supply is moved from 4.5V to 19V
60
75
DYNAMIC PERFORMANCE
SR Slew Rate (Note 9)
1V ≤ V
≤ 17V, 20% to 80%
12
V/μs
OUTx
t
Settling to +0.1% (Note 10)
A = +1, V
= 2V step,
500
ns
S
V
OUTx
L
R = 10kΩ, C = 8pF
L
BW
-3dB Bandwidth
R = 10kΩ, C = 8pF
12
8
MHz
MHz
L
L
GBWP
Gain-Bandwidth Product
A = -50, R = 5kΩ, R = 100Ω
V F G
R = 10kΩ, C = 8pF
L
L
PM
Phase Margin
A = -50, R = 5kΩ, R = 100Ω
50
85
°
V
F
G
R = 10kΩ, C = 8pF
L
L
CS
Channel Separation
f = 5MHz
dB
NOTES:
8. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCV
the “Typical Performance Curves” on page 6.
production distribution shown in
OS
9. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of
the output signal.
10. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output
level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]
FN6892.0
May 4, 2010
5
EL5220T
Typical Performance Curves
500
18
16
14
12
10
8
V
= ±5V
= +25°C
S
TYPICAL
PRODUCTION
DISTRIBUTION
V
= ±5V
S
T
A
-40°C TO +85°C
400
300
200
100
0
TYPICAL
PRODUCTION
DISTRIBUTION
6
4
2
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
2
4
6
8
10 12 14 16 18 20 22 24 26 28
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE DRIFT (|μV|/°C)
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 4. INPUT OFFSET VOLTAGE DRIFT (MSOP)
18
10.0
V
= ±5V
S
16
14
12
10
8
V
= ±5V
S
-40°C TO +85°C
7.5
5.0
2.5
0.0
TYPICAL
PRODUCTION
DISTRIBUTION
6
4
2
0
1
3
5
7
9
11
13
15
17
-50
0
50
100
150
INPUT OFFSET VOLTAGE DRIFT (mV)
TEMPERATURE (°C)
FIGURE 5. INPUT OFFSET VOLTAGE DRIFT (DFN)
FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE
4.96
5
V
= ±5V
= 5mA
V
= ±5V
S
S
I
OUT
4
3
4.95
4.94
4.93
4.92
2
1
0
-1
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 8. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FN6892.0
May 4, 2010
6
EL5220T
Typical Performance Curves(Continued)
-4.91
-4.92
140
120
100
80
V
= ±5V
= -5mA
V
R
= ±5V
= 10kΩ
S
S
L
I
OUT
-4.93
-4.94
-4.95
60
40
-4.96
-4.97
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 10. OPEN-LOOP GAIN vs TEMPERATURE
13.0
590
V
R
= ±5V
= 10kΩ
S
L
V
= ±5V
S
NO LOAD
INPUT AT GND
12.5
12.0
11.5
11.0
570
550
530
510
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. SLEW RATE vs TEMPERATURE
FIGURE 12. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
16
800
700
600
500
400
T
= +25°C
= 1
T
= +25°C
A
V
L
A
A
NO LOAD
INPUT AT GND
R = 10kΩ
C = 8pF
L
14
12
10
8
2
4
6
8
10
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 13. SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE
FN6892.0
May 4, 2010
7
EL5220T
Typical Performance Curves(Continued)
250
200
150
100
50
100
80
60
40
20
5
0
10kΩ
GAIN
1kΩ
-5
560Ω
PHASE
150Ω
V
T
= ±5V
= +25°C
= 10kΩ
= 8pF
S
A
-10
-15
0
V
V
L
= ±5V
= 1
= 8pF
0
S
R
L
L
A
C
C
-50
10M 100M
-20
10
100
1k
10k
100k
1M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. OPEN LOOP GAIN AND PHASE vs
FREQUENCY
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS R
L
1000
20
V = ±5V
S
V
V
L
= ±5V
= 1
= 10kΩ
S
R = 2kVΩ
A
R
F
15
10
5
R
= 1kΩ
100
10
G
R = 450Ω
L
SOURCE = 0dBm
100pF
0
1
0.1
50pF
8pF
-5
-10
-15
1000pF
0.01
10
1k
100k
1M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS C
FIGURE 18. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
L
12
10
8
0
V
T
V
= ±5V
= +25°C
S
A
-10
-20
-30
-40
-50
-60
-70
-80
= -10dBm
INx
6
4
2
0
V
T
= ±5V
= +25°C
= 1
= 10kΩ
= 8pF
S
A
A
R
V
L
L
C
10k
100k
1M
10M
10
1k
100k
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 20. CMRR vs FREQUENCY
FN6892.0
May 4, 2010
8
EL5220T
Typical Performance Curves(Continued)
0
-10
-20
-30
-40
-50
-60
-70
-80
1000
100
10
V
= ±5V
S
T
= +25°C
A
T
= +25°C
A
1
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. PSRR vs FREQUENCY
FIGURE 22. INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs FREQUENCY
0.050
0.045
0.040
0.035
0.030
0.025
0.020
-60
V
= ±5V
= 1
= 0dBm
S
V
= ±5V
= 10kΩ
= 1
S
A
V
R
A
V
V
L
INx
V
-70
-80
= 1.4V
RMS
IN
-90
0.015
0.010
0.005
-100
10k
100k
1M
10M
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 23. TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
FIGURE 24. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
100
80
5
V
T
= ±5V
= +25°C
= 1
S
A
4
3
A
V
R = 10kΩ
0.1%
0.1%
L
2
C = 8pF
L
60
1
0
40
-1
-2
-3
-4
-5
V
T
= ±5V
= +25°C
= 1
S
A
A
V
20
R = 10kΩ
L
V
= ±50mV
INx
0
10
100
200
300
400
500
600
700
100
LOAD CAPACITANCE (pF)
1000
SETTLING TIME (ns)
FIGURE 25. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 26. STEP SIZE vs SETTLING TIME
FN6892.0
May 4, 2010
9
EL5220T
Typical Performance Curves(Continued)
V
= ±5V
= +25°C
= 1
S
A
T
V
= ±5V
= +25°C
= 1
S
A
A
V
T
R = 10kΩ
L
A
V
C = 8pF
L
R = 10kΩ
L
C = 8pF
L
200ns/DIV
100mV STEP
6V STEP
1μs/DIV
FIGURE 27. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 28. SMALL SIGNAL TRANSIENT RESPONSE
EL5220T
(8LD MSOP/DFN SHOWN)
V +
S
+
8
7
1
4.7μF
VOUTA
VINA-
V +
S
VOUTA
0.1μF
C
R
R
FA
LA
LA
2
3
VOUTB
LB
VOUTB
VINB-
VINB+
R
GA
R
R
LB
C
FB
6
5
VINA+
VINA+
R
GB
49.9
4
VINB+
V -
S
V -
S
+
4.7μF
0.1μF
49.9
THERMAL PAD
CONNECTED TO V -
S
(DFN ONLY)
FIGURE 29. BASIC TEST CIRCUIT
FN6892.0
May 4, 2010
10
EL5220T
Applications Information
V = ±2.5V, T = +25°C, A = 1, V
= 6V R = 10kΩ TO GND
P-P, L
S
A
V
INx
Product Description
The EL5220T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5220T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability,
and is unity gain stable.
OUTPUT
The EL5220T features a slew rate of 12V/μs. Also, the
device provides common mode input capability beyond
the supply rails, rail-to-rail output capability, and a
bandwidth of 12MHz (-3dB). This enables the
amplifiers to offer maximum dynamic range at any
supply voltage.
INPUT
100μs/DIV
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS
INPUT
Operating Voltage, Input and Output
Capability
V = ±5V, T = +25°C, A = 1, V
INx
= 10V R = 10kΩ TO GND
P-P, L
S
A
V
The EL5220T can operate on a single supply or dual
supply configuration. The EL5220T operating voltage
ranges from a minimum of 4.5V to a maximum of 19V.
This range allows for a standard 5V (or ±2.5V) supply
voltage to dip to -10%, or a standard 18V (or ±9V) to
rise by +5.5% without affecting performance or
reliability.
The input common-mode voltage range of the EL5220T
extends 500mV beyond the supply rails. Also, the
EL5220T is immune to phase reversal. However, if the
common mode input voltage exceeds the supply voltage
by more than 0.5V, electrostatic protection diodes in the
input stage of the device begin to conduct. Even though
phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage
conditions. Figure 30 shows the input voltage driven
500mV beyond the supply rails and the device output
swinging between the supply rails.
100μs/DIV
FIGURE 31. OPERATION WITH RAIL-TO-RAIL INPUT
AND OUTPUT
Output Current
The EL5220T is capable of output short circuit currents
of 200mA (source and sink), and the device has
built-in protection circuitry which limits the output
current to ±200mA (typical).
The EL5220T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 31
shows the input and output waveforms for the device in
a unity-gain configuration. Operation is from ±5V
supply with a 10kΩ load connected to GND. The input is
To maintain maximum reliability the continuous output
current should never exceed ±65mA. This ±65mA limit
is determined by the characteristics of the internal
metal interconnects. Also, see “Power Dissipation” on
page 12 for detailed information on ensuring proper
device operation and reliability for temperature and
load conditions.
a 10V
approximately 9.9V
sinusoid and the output voltage is
P-P
.
P-P
Refer to the “Electrical Specifications” Table beginning
on page 3 for specific device parameters. Parameter
variations with operating voltage, loading and/or
temperature are shown in the “Typical Performance
Curves” on page 6.
Unused Amplifiers
It is recommended that any unused amplifiers be
configured as a unity gain follower. The inverting input
should be directly connected to the output and the
non-inverting input tied to the ground.
Thermal Shutdown
The EL5220T has a built-in thermal protection which
ensures safe operation and prevents internal damage
to the device due to overheating. When the die
temperature reaches +165°C (typical) the device
automatically shuts OFF the outputs by putting them in
a high impedance state. When the die cools by +15°C
FN6892.0
May 4, 2010
11
EL5220T
(typical) the device automatically turns ON the outputs
• V = Total supply voltage (V + - V -)
S S
S
by putting them in a low impedance (normal)
operating state.
• V + = Positive supply voltage
S
• V - = Negative supply voltage
S
Driving Capacitive Loads
• I
(I
= Maximum supply current per amplifier
= EL5220T quiescent current ÷ 2)
SMAX
SMAX
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability,
a snubber circuit or a series resistor may be added to
the output of the EL5220T.
• V
• I
= Output voltage
= Load current
OUT
LOAD
Device overheating can be avoided by calculating the
minimum resistive load condition, R
the highest power dissipation. To find R
, resulting in
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5220T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
LOAD
set the
LOAD
two P
V
equations equal to each other and solve for
. Reference the package power dissipation
DMAX
/I
OUT LOAD
curves, Figures 32 and 33, for further information.
Another method to reduce peaking is to add a series
output resistor (typically between 1Ω to 10Ω).
Depending on the capacitive loading, a small value
resistor may be the most appropriate choice to
minimize any reduction in gain.
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.0
781mW
0.8
DFN8
JA
Power Dissipation
595mW
θ
= +160°C/W
0.6
0.4
0.2
0.0
With the high-output drive capability of the EL5220T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5220T in the
application. Proper load conditions will ensure that the
EL5220T junction temperature stays within a safe
operating region.
MSOP8
θ
= +210°C/W
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
The maximum power dissipation allowed in a package is
determined according to Equation 1:
FIGURE 32. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
T
– T
AMAX
JMAX
P
= --------------------------------------------
(EQ. 1)
DMAX
θ
JA
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
where:
2.4
2.16W
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
2.0
• T
DFN8
θ
= +58°C/W
JA
1.6
1.2
0.8
0.4
0.0
• θ = Thermal resistance of the package
JA
• P
= Maximum power dissipation allowed
MSOP8
= +170°C/W
DMAX
θ
JA
The total power dissipation produced by an IC is the
total quiescent supply current times the total power
supply voltage, plus the power dissipation in the IC
due to the loads, or:
740mW
P
= Σi[V × I
+ (V + – V
i) × I
i]
LOAD
0
25
50
75
100
125
150
85
(EQ. 2)
DMAX
S
SMAX
S
OUT
AMBIENT TEMPERATURE (°C)
when sourcing, and:
FIGURE 33. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
P
= Σi[V × I
+ (V
i – V -) × I
i]
LOAD
(EQ. 3)
DMAX
S
SMAX
OUT
S
when sinking, where:
• i = 1 to 2
(1, 2 corresponds to Channel A, B respectively)
FN6892.0
May 4, 2010
12
EL5220T
as possible. One 4.7μF capacitor may be used for
Power Supply Bypassing and Printed Circuit
Board Layout
multiple devices. For dual supply operation the same
capacitor combination should be placed at each supply
pin to ground.
The EL5220T can provide gain at high frequency, so
good printed circuit board layout is necessary for
optimum performance. Ground plane construction is
highly recommended, trace lengths should be as short
as possible and the power supply pins must be well
bypassed to reduce any risk of oscillation.
It is highly recommended that EL5220T exposed
thermal pad packages should always have the pad
connected to the lowest potential, V -, to optimize
S
thermal and operating performance. PCB vias should
be placed below the device’s exposed thermal pad to
For normal single supply operation (the V - pin is
S
connected to ground) a 4.7μF capacitor should be
transfer heat to the V - plane and away from the
S
device.
placed from V + to ground, then a parallel 0.1μF
S
capacitor should be connected as close to the amplifier
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
5/4/10
FN6892.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: EL5220T
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
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For additional products, see www.intersil.com/product_tree
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6892.0
May 4, 2010
13
EL5220T
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0±0.1
8
0.25 CAB
4.9±0.15
DETAIL "X"
0.18 ± 0.05
3.0±0.1
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
GAUGE
PLANE
H
C
0.25
SEATING PLANE
0.10 ± 0.05
0.33 +0.07/ -0.08
0.08 C AB
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
1. Dimensions are in millimeters.
4.40
3.00
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
0.65
0.40
4. Plastic interlead protrusions of 0.25mm max per side are not
included.
1.40
5. Dimensions “D” and “E1” are measured at Datum Plane “H”.
6. This replaces existing drawing # MDP0043 MSOP 8L.
TYPICAL RECOMMENDED LAND PATTERN
FN6892.0
May 4, 2010
14
EL5220T
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
2.00
A
2X 1.50
PIN 1
INDEX AREA
6X 0.50
B
1
6
PIN #1
1.80 +0.10/-0.15
INDEX AREA
(4X)
0.15
8
4
8X 0.25 +0.07/-0.05
8X 0.40 ±0.10
0.10 M C A B
TOP VIEW
1.65 +0.10/-0.15
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.90 ±0.10
(1.65)
(1.50)
C
BASE PLANE
SEATING PLANE
(8X 0.60)
0.08 C
0.05 MAX
SIDE VIEW
0.20 REF
(1.80)
(2.80)
C
(6X 0.50)
0.05 MAX
DETAIL "X"
(8X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compies to JEDEC MO-229 VCED-2.
7.
FN6892.0
May 4, 2010
15
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