CDP1852CD3 [INTERSIL]
High-Reliability Byte-Wide Input/Output Port; 高可靠性字节宽的输入/输出端口
| 型号： | CDP1852CD3 |
| 厂家： | 
Intersil |
| 描述： | High-Reliability Byte-Wide Input/Output Port |
| 文件： | 总7页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1852/3,
CDP1852C/3
March 1997
High-Reliability Byte-Wide Input/Output Port
Features
Description
• Static Silicon-Gate CMOS Circuitry
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, mode-
programmable input/output ports. They are compatible and
will interface directly with CDP1800-Series microprocessors.
They are also useful as 8-bit address latches when used
with the CDP1800 multiplexed address bus and as I/O ports
in general-purpose applications.
• Interfaces Directly with CDP1800-Series Microproces-
sors
The mode control is used to program the device as an input
port (mode = 0) or as an output port (mode = 1). The SR/SR
output can be used as a signal to indicate when data is
ready to be transferred. In the input mode, a peripheral
device can strobe data into the CDP1852/3, and micropro-
cessor can read that data by device selection. In the output
mode, a microprocessor strobes data into the CDP1852/3,
and handshaking is established with a peripheral device
when the CDP1852/3 is deselected.
• Single Voltage Supply
• Full Military Temperature Range
(-55oC to +125oC)
Ordering Information
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request
output low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out
terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are tristated
and the service request output returns high (SR/SR =1).
PACK-
AGE
TEMP.
RANGE
PKG.
NO
5V
10V
o
o
SBDIP
-55 C to +125 C CDP1852CD3 CDP1852D3 D24.6
Pinout
CDP1852/3, CDP1852C/3 (SBDIP)
TOP VIEW
In the output mode, the output drivers are enabled at all
times. Data at the data-in terminals (DI0-DI7) is strobed into
the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and
CS2 and the clock are high (1), and are present at the data-
out terminals (DO0-DO7). The negative high-to-low transi-
tion of the clock latches the data in the register. The SR/SR
output goes high (SR/SR = 1) when the device is deselected
(CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the
following trailing edge of the clock.
CSI/CSI
MODE
DI0
1
2
3
4
5
6
7
8
9
24
VDD
23 SR/SR
22 DI7
21 DO7
20 DI6
DO0
DI1
DO1
DI2
19 DO6
18 DI5
DO2
DI3
17 DO5
16 DI4
A CLEAR control is provided for resetting the port’s register
(DO0-DO7
= 0) and service request flip-flop (input
DO3 10
CLOCK 11
VSS 12
15 DO4
14 CLEAR
13 CS2
mode: SR/SR = 1 and output mode: SR/SR = 0).
The CDP1852/3 is functionally identical to the CDP1852C/3.
The CDP1852/3 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1852C/3 has a recom-
mended operating voltage range of 4V to 6.5V.
The CDP1852/3 and CDP1852C/3 are supplied in 24-lead,
dual-in-line side-brazed ceramic packages (D suffix).
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1694.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
CDP1852/3, CDP1852C/3
Block Diagram of CDP1852/3
1
DEVICE
SELECT
DECODE
CSI/CSI†
CONTROL
LOGIC
23
SR/SR†
13
CS2
24
12
VDD
VSS
MODE
CLOCK
CLEAR
2
11
14
3
5
7
9
16
18
20
22
4
6
8
10
15
17
19
21
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
RESET CLOCK
ENABLE
THREE-
STATE
OUTPUT
DRIVERS
8-BIT
DATA
REGISTER
† POLARITY DEPENDS ON MODE
MODE = 1
CSI
SR
MODE = 0
CSI
P1
P23
SR
FIGURE 1.
CS2
13
CSI/CSI
1
SR/SR
23
S
MODE
2
D
Q
VSS
SERVICE
REQUEST
R
CL LATCH
CLEAR
14
CLOCK
11
VDD
DI0
3
P
TG
N
P
DO0
4
N
P
TG
N
VSS
DO1
6
DI1
5
D17
22
DO7
21
FIGURE 2. CDP1852/3 LOGIC DIAGRAM
2
CDP1852/3, CDP1852C/3
:
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V ):
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(All Voltages Referenced to V Terminal)
CDP1852/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +11V
CDP1852C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
65
20
SS
T = Full Package Temperature Range
A
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V +0.5V
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T )
DD
A
o
o
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
Storage Temperature Range (T
) . . . . . . . . . . . . -65 C to +150 C
STG
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 in (1.59 ± 0.79mm)
From Case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions T = Full-Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges.
LIMITS
CPP1852/3
CDP1852C/3
PARAMETER
DC Operating Voltage Range
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
Input Voltage Range
V
V
V
V
DD
SS
DD
SS
Static Electrical Specifications
V
= 0 or V , Except as Noted
IN DD
LIMITS
o
o
o
-55 C, +25 C
MIN MAX
10
+125 C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Quiescent Device Current (Note 1)
I
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
-
-
100
µA
µA
mA
mA
mA
mA
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
-
2.6
6.1
-1.8
-4.4
-
20
-
-
1.9
4.1
-1.3
-2.9
-
300
Output Low Drive (Sink) Current
Output High Drive (Source) Current
Output Voltage Low Level
Output Voltage High Level
Input Low Voltage
I
= 5V, V = 0.4V
-
-
OL
O
= 10V, V = 0.5V
-
O
I
= 5V, V = 4.6V
-
-
OH
O
= 10V, V = 9.5V
-
-
O
V
= 5V, I = 0µA
0.1
0.1
-
0.2
0.2
-
OL
OL
= 10V, I = 0µA
-
-
V
OL
V
= 5V, I = 0µA
4.9
9.9
-
4.8
9.8
-
V
OH
OL
= 10V, I = 0µA
-
-
V
OL
V
= 5V, V = 0.2, 4.8V
1.5
3
1.5
3
V
IL
IH
IL
O
= 10V, V = 0.2, 9.8V
-
-
V
O
Input High Voltage
V
= 5V, V = 0.2, 4.8V
3.5
7
-
3.5
7
-
V
O
= 10V, V = 0.2, 9.8V
-
-
V
O
Input Leakage Low
I
= 5V, V = 0V
-
-1
-1
1
-
-5
-5
5
µA
µA
µA
µA
IN
= 10V, V = 0V
-
-
IN
Input Leakage High
I
= 5V, V = 5V
-
-
IH
IN
= 10V, V = 10V
-
1
-
5
IN
3
CDP1852/3, CDP1852C/3
Static Electrical Specifications
V
= 0 or V , Except as Noted (Continued)
IN
DD
LIMITS
o
o
o
-55 C, +25 C
+125 C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
-1
MIN
MAX
UNITS
µA
Three-State Output Leakage Low
I
V
V
V
V
= 5V, V = 0V
-
-
-
-
-
-
-
-5
-5
5
OZL
DD
DD
DD
DD
O
= 10V, V = 0V
-
-
-
-
-
-1
1
µA
O
Three-State Output Leakage High
I
= 5V, V = 5V
µA
OZH
O
= 10V, V = 10V
1
5
µA
O
Input Capacitance
Output Capacitance
NOTES:
C
Note 2
Note 2
10
15
10
15
pF
IN
C
pF
OUT
o
1. The CDP1852C/3 meets all 5V static electrical specifications of the CDP1852/3 except +125 C quiescent device current for which the
limit is I = 300µA.
DD
2. Input and output capacitance are guaranteed but not tested.
Static Burn-In Circuit
VDD
TYPE NO.
CDP1852/3
CDP1852C/3
V
TEMPERATURE
TIME
DD
1
2
24
23
22
21
20
19
18
17
16
15
14
13
o
11V
7V
+125 C
160 Hrs. Min.
160 Hrs. Min.
VDD
o
+125 C
3
4
5
6
7
8
9
10
11
12
VSS
VSS
ALL RESISTORS 47kΩ (±20%)
Dynamic Electrical Specifications Mode = 0 Input Port, See Figure 3, Input t , t ≤ 15ns; C = 50pF
r
f
L
LIMITS (NOTE 1)
o
o
o
-55 C, +25 C
+125 C
V
(NOTE 1)
(NOTE 1)
DD
PARAMETER
SYMBOL
VOLTS
MIN
250
150
150
90
MAX
MIN
360
180
200
110
160
80
MAX
UNITS
ns
Select Duration
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SW
ns
Clock Pulse Width
t
ns
WW
10
5
ns
Clear Pulse Width
t
110
50
ns
CLR
10
5
ns
Data-In to Clock Fall Setup Time
t
-10
-5
-10
-5
ns
DS
10
ns
4
CDP1852/3, CDP1852C/3
Dynamic Electrical Specifications Mode = 0 Input Port, See Figure 3, Input t , t ≤ 15ns; C = 50pF (Continued)
r
f
L
LIMITS (NOTE 1)
o
o
o
-55 C, +25 C
+125 C
V
(NOTE 1)
(NOTE 1)
DD
PARAMETER
SYMBOL
VOLTS
MIN
150
70
MAX
MIN
170
100
MAX
UNITS
ns
Data-In After Clock Fall Hold Time
t
5
-
-
-
-
DH
10
ns
Propagation Delay Times:
Clear to SR
t
t
t
5
10
5
-
-
-
-
-
-
200
110
175
110
175
110
-
-
-
-
-
-
340
170
220
130
240
120
ns
ns
ns
ns
ns
ns
RSR
CSR
SSR
Clock to SR
Deselect to SR
NOTE:
10
5
10
1. Time required by a device to allow for the indicated function.
(NOTE 1)
CS1 • CS2
tSW
tWW
CLOCK
tDH
DATA IN
tDS
HIGH
DATA BUS
IMPEDANCE
tSSR
SR
tRSR
tCSR
tCLR
CLEAR
NOTE:
1. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.
MODE = 0 TRUTH TABLE
SERVICE REQUEST
TRUTH TABLE
CLOCK
CS1 • CS2 (Note 1)
CLEAR
DATA OUT EQUALS
High Impedance
0
X
0
0
1
0
1
1
1
X
0
1
X
Clock =
SR = 0
CS1 or CS2 =
or CLEAR = 0
Data Latch
Data In
SR = 1
NOTE:
1. CS1 • CS2 = CS1 = 1, CS2 = 1.
FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
5
CDP1852/3, CDP1852C/3
Dynamic Electrical Specification Mode = 1 Output Port, See Figure 4, Input tr, tf ≤ 15ns; C = 50pF
L
LIMITS (NOTE 1)
o
o
o
-55 C, +25 C
+125 C
V
(NOTE 1)
(NOTE 1)
DD
PARAMETER
Clock Pulse Width
SYMBOL
VOLTS
MIN
170
90
MAX
MIN
260
130
260
130
135
75
MAX
UNITS
ns
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK
ns
Write Width Duration
t
200
110
110
60
ns
WW
CLR
10
5
ns
Clear Pulse Width
t
ns
10
5
ns
Data-In to Clock Fall Setup Time
Data Hold from Write Termination
Select-After Clock-Fall Hold Time
t
-10
-5
-10
-5
ns
DS
10
5
ns
t
130
70
170
90
ns
DH
10
5
ns
t
0
0
ns
SH
10
0
0
ns
Propagation Delay Times:
Clear to Data
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
215
140
250
130
150
80
-
-
-
-
-
-
-
-
-
-
-
-
290
190
350
190
200
100
240
160
240
120
240
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RDO
Write to Data Out
Data In to Data Out
Clear to SR
t
WDO
10
5
t
DDO
10
5
t
175
120
170
90
RSR
CSR
10
5
Clock to SR
t
10
5
Deselect to SR
NOTE:
t
170
90
SSR
10
1. Time required by a device to allow for the indicated function.
6
CDP1852/3, CDP1852C/3
(NOTE 2)
tWW
(NOTE 1)
CS1 • CS2
tSH
tDH
tDS
tCLK
CLOCK
DATA IN
tDDO
tRDO
DATA OUT
tWDO
tSSR
SR
tRSR
tCLR
tCSR
CLEAR
NOTES:
1. CS1 • CS2 is the overlap of the CS1 = 0 and CS2 = 1.
2. Write is the overlap of CS1 • CS2 and clock.
MODE = 1 TRUTH TABLE
SERVICE REQUEST
TRUTH TABLE
CLOCK
CS1 • CS2 (NOTE 1)
CLEAR
DATA OUT EQUALS
0
0
X
1
X
X
0
0
1
1
X
0
CS1
or
Clock • (CS1 • CS2)
or
Data Latch
Data Latch
Data In
CS2
CLEAR = 0
1
SR = 1
SR = 0
NOTE:
1. CS1 • CS2 = CS1 = 0, CS2 = 1
FIGURE 4. MODE = 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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