CDP1852D [INTERSIL]
Byte-Wide Input/Output Port; 字节宽的输入/输出端口
| 型号： | CDP1852D |
| 厂家： | 
Intersil |
| 描述： | Byte-Wide Input/Output Port |
| 文件： | 总9页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1852,
CDP1852C
March 1997
Byte-Wide Input/Output Port
Features
Description
The CDP1852 and CDP1852C are parallel, 8-bit, mode-pro-
grammable input/output ports. They are compatible and will
interface directly with CDP1800-series microprocessors. They
are also useful as 8-bit address latches when used with the
CDP1800 multiplexed address bus and as I/O ports in general-
purpose applications.
• Static Silicon-Gate CMOS Circuitry
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
• Interfaces Directly with CDP1800-Series
Microprocessors
The mode control is used to program the device as an input port
(mode = 0) or as an output port (mode = 1). The SR/SR output
can be used as a signal to indicate when data is ready to be
transferred. In the input mode, a peripheral device can strobe
data into the CDP1852, and microprocessor can read that data
by device selection. In the output mode, a microprocessor
strobes data into the CDP1852, and handshaking is established
with a peripheral device when the CDP1852 is deselected.
• Single Voltage Supply
• Full Military Temperature Range (-55oC to +125oC)
Ordering Information
PKG.
NO.
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request out-
put low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out ter-
minals (D00-D07). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are three-stated
and the service request output returns high (SR/SR =1).
PACKAGE TEMP. RANGE
5V
10V
o
o
PDIP
-40 C to +85 C CDP1852CE CDP1852E E24.6
o
o
SBDIP
-40 C to +85 C CDP1852CD CDP1852D D24.6
In the output mode, the output drivers are enabled at all times.
Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit
register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the
clock are high (1), and are present at the data-out terminals
(D00-D07). The negative high-to-low transition of the clock
latches the data in the register. The SR/SR output goes high
(SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or
CS2 = 0) and returns low (SR/SR = 0) on the following trailing
edge of the clock.
Pinout
Typical CDP1802 Microprocessor System
24 LEAD DIP
TOP VIEW
CSI/CSI
MODE
DI0
1
2
3
4
5
6
7
8
9
24
VDD
N0 - N2 MRD
ADDR BUS
ADDR BUS
TPA
23 SR/SR
22 DI7
TPB
TPA
Q
21 DO7
20 DI6
DO0
DI1
DATA
CPU
CDP1802
I/O
SC0 SC1
ROM
RAM
CDP1852
INTERRUPT
DO1
DI2
19 DO6
18 DI5
CONTROL
MRD
CEO
MRD
MWR
DMA - IN DMA - OUT
EF1 - EF4
DO2
DI3
17 DO5
16 DI4
DO3 10
CLOCK 11
VSS 12
15 DO4
14 CLEAR
13 CS2
BIDIRECTIONAL DATA BUS
FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1166.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
CDP1852, CDP1852C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply-voltage Range, (V
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(Voltage Referenced to V Terminal)
CDP1852 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V
CDP1852C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to V +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
65
65
N/A
20
SS
Operating-Temperature Range (T )
A
o
o
Package Type D, H . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
DD
o
o
o
o
Device Dissipation Per Output Transistor. . . . . . . . . . . . . . . 100mW
Storage Temperature Range (T
) . . . . . . . . . . . . -65 C to +150 C
STG
o
For T = Full Package-Temperature Range
Lead Temperature (During Soldering): . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
from Case for 10s max
A
(All Package Type)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions At T = Full Package Temperature Range. For Maximum Reliability, Operating Conditions Should be
A
Selected so that Operation is Always within the Following Ranges:
LIMITS
CDP1852
CDP1852C
PARAMETER
DC Operating Voltage Range
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
Input Voltage Range
V
V
V
V
DD
SS
DD
SS
Functional Diagram
1
23
CSI/CSI
SR/SR
(NOTE 1)
DEVICE
SELECT
DECODE
CONTROL
LOGIC
(NOTE 1)
13
CS2
24
12
2
11
14
VDD
VSS
MODE
CLOCK
CLEAR
RESET CLOCK
ENABLE
3
5
4
6
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
THREE-
STATE
OUTPUT
DRIVERS
7
8
8-BIT
DATA
REGISTER
9
10
15
17
19
21
MODE 0
CSI
MODE 1
CSI
16
18
20
22
P1
P23
SR
SR
NOTE:
1. Polarity depends on mode.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM FOR CDP1852
A CLEAR control is provided for resetting the port’s register
(DO0-DO7 = 0) and service request flip-flop (input mode:
SR/ SR = 1 and output mode: SR/SR = 0).
The CDP1852 is functionally identical to the CDP1852C.
The CDP1852 has a recommended operating voltage range
of 4 to 10.5 volts, and the CDP1852C has a recommended
operating voltage range of 4 to 6.5 volts.
The CDP1852 and CDP1852C are supplied in 24-lead,
hermetic, dual-in-line ceramic packages (D suffix), in 24-lead
dual-in-line plastic packages (E suffix). The CDP1852C is
also available in chip form (H suffix).
2
CDP1852, CDP1852C
Logic Diagram
13
1
CS2
SR/SR
23
CS1/CS1
S
D
R
Q
2
MODE
VSS
SERVICE
REQUEST
LATCH
CL
14
CLEAR
11
3
CLOCK
VDD
p
DO0
4
p
TG
n
DI0
n
p
VSS
TG
n
DO1
6
5
DI1
DI7
DO7
21
22
FIGURE 3. CDP1852 LOGIC DIAGRAM
o
o
Static Electrical Specifications At T = -40 C to +85 C, Unless Otherwise Specified
A
CONDITIONS
LIMITS
CDP1852
CDP1852C
V
V
V
DD
(NOTE1)
(NOTE1)
O
IN
PARAMETER
(V)
(V)
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
µA
Quiescent Device Current
I
-
0, 5
5
-
-
-
10
100
-
-
-
50
DD
-
0, 10
0, 5
10
5
-
1.6
3
-
-
-
µA
Output Low Drive
(Sink) Current
I
0.4
0.5
4.6
9.5
-
3.2
6
1.6
3.2
-
mA
mA
mA
mA
V
OL
0, 10
0, 5
10
5
-
-
-
-
Output High Drive
(Source) Current
I
-1.15
-3
-2.3
-6
0
-
-1.15
-2.3
-
-
OH
0, 10
0, 5
10
5
-
-
-
-
-
0
-
Output Voltage Low-Level
(Note 2)
V
-
0.1
0.1
0.1
-
OL
-
0, 10
10
-
0
V
3
CDP1852, CDP1852C
o
o
Static Electrical Specifications At T = -40 C to +85 C, Unless Otherwise Specified (Continued)
A
CONDITIONS
LIMITS
CDP1852
CDP1852C
V
V
V
DD
(NOTE1)
(NOTE1)
O
IN
PARAMETER
(V)
(V)
0, 5
0, 10
-
(V)
MIN
4.9
9.9
-
TYP
MAX
MIN
TYP
MAX
UNITS
Output Voltage High Level
(Note 2)
V
-
-
5
5
10
-
-
-
4.9
5
-
-
-
V
V
V
OH
10
5
-
-
Input Low Voltage
Input High Voltage
Input Leakage Current
V
0.5,
4.5
1.5
-
1.5
IL
0.5,
9.5
-
-
-
10
5
-
3.5
7
-
-
-
3
-
-
3.5
-
-
-
-
-
-
-
V
V
V
V
0.5,
4.5
lH
0.5,
9.5
10
-
I
-
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
5
10
5
-
-
-
-
-
-
-
-
-
±1
±2
-
-
-
-
-
-
-
-
-
±1
-
µA
µA
µA
µA
µA
µA
pF
pF
lN
-
-
-
-
Three-State Output Leakage
Current
I
0, 5
±1
-
±1
-
OUT
0, 10
10
5
-
±2
-
Operating Current (Note 3)
I
-
-
-
-
130
550
5
300
800
7.5
7.5
150
300
-
DD1
10
-
-
5
-
Input Capacitance
Output Capacitance
NOTES:
C
7.5
-
IN
C
-
-
5
OUT
o
1. Typical values are for T = 25 C and nominal V
.
A
DD
2. I = I = 1µA
OL
OH
3. Operating current is measured at 2MHz in an CDP1802 system with open outputs and a program of 6N55, 6NAA, 6N55, 6NAA,....
o
o
Dynamic Electrical Specifications At T = -40 C to +85 C, V = ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD
IL
DD
L
and 1 TTL Load
LIMITS
V
(NOTE 1)
DD
PARAMETER
MODE 0 - INPUT PORT (See Figure 4)
Minimum Select Pulse Width
(V)
MIN
TYP
MAX
UNITS
t
5
10
5
-
-
-
-
-
-
180
90
90
45
80
40
360
180
180
90
ns
ns
ns
ns
ns
ns
SW
Minimum Write Pulse Width
Minimum Clear Pulse Width
t
WW
CLR
10
5
t
160
80
10
4
CDP1852, CDP1852C
o
o
Dynamic Electrical Specifications At T = -40 C to +85 C, V = ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD
IL
DD
L
and 1 TTL Load (Continued)
LIMITS
V
(NOTE 1)
DD
PARAMETER
(V)
MIN
TYP
MAX
0
UNITS
Minimum Data Setup Time
Minimum Data Hold Time
t
5
-
-
-10
-5
ns
ns
ns
ns
ns
ns
DS
10
5
0
t
-
75
150
75
DH
10
5
-
35
Data Out Hold Time (Note 2)
t
30
15
185
100
370
200
DOH
10
Propagation Delay Times, t
, t
PLH PHL
Select to Data Out (Note 2)
t
t
t
5
10
5
30
15
-
185
100
170
85
370
200
340
170
220
110
240
120
ns
ns
ns
ns
ns
ns
ns
ns
SDO
RSR
CSR
Clear to SR
10
5
-
Clock to SR
-
110
55
10
5
-
Select to SR
t
-
120
60
SSR
10
-
NOTES:
1. Typical values are for T = 25 C and nominal V
o
.
DD
A
2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1.
Input Port Mode 0 - Typical Operation
General Operation
When the mode control is tied to VSS, the CDP1852 put drivers place the DATA from the peripheral device on the
becomes an input port. In this mode, the peripheral device DATA BUS. When the CDP1802 selected the CDP1852, it
places data into the CDP1852 with a strobe pulse and the also selected and addressed the memory via one of the 16
CDP1852 signals the microprocessor that data is ready to be internal address registers selected by an internal “X” regis-
transferred on the strobe’s trailing edge via the SR output ter. The data from the CDP1852 is therefore entered into the
line. The CDP1802 then issues an input instruction that memory [Bus → M(R(X))]. The data is also transferred to the
enables the CDP1852 to place the information from the D register (accumulator) in the microprocessor (Bus → D).
peripheral device on the data bus to be entered into a mem- When the CDP1802’s execute cycle is completed, the
ory location and the accumulator of the microprocessor.
CDP1852 is deselected by the NX line returning low and its
data output pins are three-stated. The SR output returns
high.
Detailed Operation (See Figure 5)
The STROBE from the peripheral device places DATA into
the 8-bit register of the CDP1852 when it goes high and
latches the DATA on its trailing edge. The SR output is set
low on the strobe’s trailing edge. This output is connected to
a flag line of the CDP1802 microprocessor and software poll-
ing will determine that the flag line has gone low and periph-
eral data is ready to be transferred. The CDP1802 then
issues an input instruction that places an NX line high. With
the MRD line also high, the CDP1852 is selected and its out-
5
CDP1852, CDP1852C
CS1 - CS2
(NOTE 1)
tSW
CLOCK
tWW
tDH
DATA IN
tDOH
tDS
tSDO
HIGH
DATA BUS
IMPEDANCE
tSSR
SR
tCSR
tRSR
CLEAR
tCLR
NOTE 1. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.
MODE 0 TRUTH TABLE
SERVICE REQUEST TRUTH TABLE
CLOCK
† CS1-CS2
CLEAR
DATA OUT EQUALS
High Impedance
0
CLOCK
CS1 or CS2
or CLEAR
X
0
0
1
0
1
1
1
X
0
1
X
SR/SR
0
SR/SR
1
Data Latch
Data In
† CS1 • CS2: CS1 = 1, CS2 = 1
FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY
CDP1802
CDP1852
CS2
NX
CLOCK
D1
STROBE
ADDRESS
LINES
MRD
EFX
CS1
SR
DATA FROM
PERIPHERAL
VSS
MODE
D0
DATA BUS
STROBE
PERIPHERAL DEVICE
PERIPHERAL
DATA
PLACES DATA IN CDP1852
AND CDP1852 SIGNALS
CDP1802 THAT DATA IS READY
SR/SR
NX
CDP1802 SELECTS
CDP1852 AND DATA
IS TRANSFERRED
MRD
TO MEMORY AND
THE MICROPROCESSOR
DATA BUS
VALID
THREE - STATE
FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
6
CDP1852, CDP1852C
o
o
Dynamic Electrical Specifications At T = -40 C to +85 C, V = ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD
IL
DD
L
and 1 TTL Load
LIMITS
V
(NOTE 1)
DD
PARAMETER
MODE 1- OUTPUT PORT (See Figure 6)
Minimum Clock Pulse Width
(V)
MIN
TYP
MAX
UNITS
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
130
65
130
65
60
30
-10
-5
260
130
260
130
120
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
Minimum Write Pulse Width
Minimum Clear Pulse Width
Minimum Data Setup Time
Minimum Data Hold Time
t
WW
10
5
t
CLR
10
5
t
DS
10
5
0
t
75
35
-10
-5
150
75
0
DH
10
5
Minimum Select-After-Clock Hold Time
t
SH
10
0
Propagation Delay Times, t
Clear to Data Out
, t
PLH PHL
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
140
70
280
140
440
220
200
100
240
120
240
120
240
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RDO
Write to Data Out
Data In to Data Out
Clear to SR
t
220
110
100
50
WDO
10
5
t
DDO
10
5
t
120
60
RSR
CSR
10
5
Clock to SR
t
120
60
10
5
Select to SR
t
120
60
SSR
10
NOTE:
o
1. Typical values are for T = 25 C and nominal V
.
A
DD
Output Port Mode 1 - Typical Operation
General Operation
Detailed Operation (See Figure 7)
Connecting the mode control to VDD configures the The CDP1802 issues an output instruction. The NX line goes
CDP1852 as an output port. The output drivers are always
on in this mode, so any data in the 8-bit register will be
present at the data-out lines when the CDP1852 is selected.
The N line and MRD connections between the CDP1852
and CDP1802 remain the same as in the input mode
configuration, but now the clock input of the CDP1852 is tied
to the TPB output of the CDP1802 and the SR output of the
CDP1852 will be used to signal the peripheral device that
valid data is present on its input lines. The microprocessor
issues an output instruction, and data from the memory is
strobed into the CDP1852 with the TPB pulse. When the
CDP1852 is deselected, the SR output goes high to signal
the peripheral device.
high and the MRD line goes low. The memory is accessed
M(R(X)) → BUS and places data on the DATA BUS. This
data are strobed into the 8-bit register of the CDP1852 when
TPB goes high and latched on the TPB’s trailing edge. The
valid data thus appears on the CDP1852 output lines. When
the CDP1802 output instruction cycle is complete, the NX
line goes low and the SR output goes high. SR will remain
high until the trailing edge of the next TPB pulse, when it will
return low.
7
CDP1852, CDP1852C
tWW (NOTE 2)
CS1 CS2
(NOTE 1)
tSH
tDH
tDS
CLOCK
tCLK
DATA IN
tDDO
tRDO
DATA OUT
SR
tWDO
tSSR
tRSR
tCLR
tCSR
CLEAR
NOTES
1. CS1 • CS2 is the overlap of CS1 = 0 and CS2 = 1.
2. Write is the overlap of CS1 • CS2 and CLOCK.
MODE 1 TRUTH TABLE
SERVICE REQUEST TRUTH TABLE
CS1
or
CS2
CLOCK
or
CLEAR
CLOCK
† CS1-CS2
CLEAR
DATA OUT EQUALS
0
0
X
1
X
X
0
1
0
1
1
X
0
Data Latch
Data Latch
Data In
SR/SR
1
SR/SR
0
† CS1 • CS2 : CS1 = 0, CS2 = 1
FIGURE 6. MODE 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY
CDP1802
CDP1852
CS2
NX
CS1
MRD
TPB
ADDRESS
LINES
DATA OUT TO
PERIPHERAL DEVICE
CLOCK
MODE
DATA
OUT
SIGNAL THAT INDICATES
DATA IS READY
SR
VDD
DATA IN
DATA BUS
NX
TPB
CDP1852 IS SELECTED
AND DATA IS
STROBED INTO IT’S
REGISTER WITH TPB
MRD
VALID
DATA
DATA BUS
DATA TO
PERIPHERAL
DEVICE
DATA IS OUTPUTTED
FROM THE CDP1852
AND THE PERIPHERAL
DEVICE IS SIGNALED
SR/SR
FIGURE 7. OUTPUT PORT MODE 1 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
8
CDP1852, CDP1852C
Application Information
In a CDP1800 series microprocessor-based system where This condition forces SR low and sets the internal SR latch
MRD is used to distinguish between INP and OUT (see Figure 3). In a small system with unique N codes for
instructions, an lNP instruction is assumed to occur at the inputs and outputs, this situation does not arise. Using the
beginning of every I/O cycle because MRD starts high. CDP1853 N-bit decoder or equivalent logic to decode the N
Therefore, at the start of an OUT instruction, which uses the lines after TPA prevents dual selection in larger systems
same 3-bit N code as that used for selection of an input port, (see Figure 9 and Figure 10).
the input device is selected for a short time (see Figure 8).
MRD
N0
N1
N2
SELECT
SR
6D
65
FIGURE 8. EXECUTION OF A “65” OUTPUT INSTRUCTION SHOWING MOMENTARY SELECTION OF INPUT PORT “D”
4
OUT 0
2
5
6
N0
N1
N2
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
1 OF 8
DECODER
7
3
12
11
10
9
14
EN
13
CE
TPA
TPB
CE
1
CLOCK A
(TPA)
Qn
EN
(NOTE 1)
15
CLOCK B
(TPB)
OUTPUT
FIGURE 9. CDP1853 TIMING WAVEFORMS
FIGURE10. CDP1853 FUNCTIONAL DIAGRAM
NOTE:
1. Output enabled when EN = HIGH. Internal signal shown for ref-
erence only (See Figure 1).
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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