CDP1823CD3 [INTERSIL]
High-Reliability CMOS 128-Word x 8-Bit Static RAM; 高可靠性的CMOS 128字×8位的静态RAM
| 型号： | CDP1823CD3 |
| 厂家： | 
Intersil |
| 描述： | High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| 文件： | 总6页 (文件大小：31K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1823C/3
High-Reliability CMOS
128-Word x 8-Bit Static RAM
March 1997
Features
Description
• For Applications in Aerospace, Military, and Critical
Industrial Equipment
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static
random access memory. It is compatible with the CDP1802,
CDP1804, CDP1805, and CDP1806 microprocessors, and
will interface directly without additional components. The
CDP1823C has a recommended operating voltage range of
4V to 6.5V.
• Compatible with CDP1800-Series Microprocessors at
Maximum Speed
• Interfaces with CDP1800-Series Microprocessors
without Additional Components
The CDP1823C memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip
select inputs are provided to simplify memory system
expansion. In order to enable the CDP1823C, the chip select
inputs CS2, CS3, and CS5 require a low input signal, and
the chip select inputs CS1 and CS4 require a high input
signal.
• Fast Access Time
o
• At V
= 5V, +25 C . . . . . . . . . . . . . . . . . . . . . . . . 275ns
DD
• Single Voltage Supply
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory
System Expansion
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V
DD
The MRD signal enables all 8 output drivers when in the low
• Memory Retention for Standby Battery Voltage Down state and should be in a high state during a write cycle.
o
to 2V at 25 C
After valid data appear at the output, the address inputs may
• Latch-Up-Free Transient Radiation Tolerance
Ordering Information
PART NUMBER
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or t
(access time) after address changes.
AA
PACKAGE TEMP. RANGE
(5V)
PKG. NO.
o
o
SBDIP
-55 C to +125 C CDP1823CD3
D24.6
Pinout
CDP1823C/3
(SBDIP)
TOP VIEW
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CS1
1
2
3
4
5
6
7
8
9
24
V
DD
23 A0
22 A1
21 A2
20 A3
19 A4
18 A5
17 A6
16 MWR
15 MRD
14 CS5
13 CS4
CS2 10
CS3 11
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2982.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-31
CDP1823C/3
OPERATIONAL MODES
FUNCTION
MRD
MWR
CS1
CS2
CS3
CS4
CS5
BUS TERMINAL STATE
Storage State of Addressed Word
Input High Impedance
Read
Write
0
1
1
X
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
Standby
High Impedance
Not Selected
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
1
High Impedance
X
NOTE:
1. Logic 1 = High, Logic 0 = Low, X = Don’t Care.
6-32
CDP1823C/3
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1823C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Maximum Operating Temperature Range (T ) . . . .-55 C to +125 C
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
SBDIP Package. . . . . . . . . . . . . . . . . .
60
17
SS
o
o
A
o
o
+0.5V Maximum Storage Temperature Range (T ) . . .-65 C to +150 C
DD
STG
o
Maximum Lead Temperature (During Soldering) . . . . . . . . . +265 C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150 C
o
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating
A
conditions should be selected so that operation is always within the following ranges:
LIMITS
PARAMETER
MIN
MAX
UNITS
Supply Voltage Range
4
6.5
V
V
Recommended Input Voltage Range
V
V
DD
SS
Static Electrical Specifications
V
= 5V ±5%
DD
CONDITIONS
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
V
V
DD
O
IN
PARAMETER
Quiescent Device Current (Note 1)
Output Low (Sink) Current (Note 1)
Output High (Source) Current (Note 1)
Output Voltage Low-Level
Output Voltage High-Level
Input Low Voltage
(V)
(V)
0, 5
0, 5
0, 5
0, 5
0, 5
-
(V)
5
5
5
5
5
5
5
5
5
5
-
MIN
MAX
270
MIN
MAX
1000
-
UNITS
I
-
-
2.7
-
-
1.5
-
µA
mA
mA
V
DD
OL
OH
I
0.4
-
-1.3
0.1
-
I
4.6
-0.7
0.1
-
V
-
-
-
OL
V
-
V
- 0.1
V - 0.1
DD
V
OH
DD
V
V
0.5, 4.5
-
0.3 V
-
-
0.3 V
DD
V
IL
DD
Input High Voltage
0.5, 4.5
-
0.7 V
0.7 V
DD
-
V
IH
DD
Input Leakage Current (Note 1)
Operating Current (Note 1)
Three-State Output Leakage Current
Input Capacitance
I
I
I
-
0, 5
0, 5
0, 5
-
-
-
-
-
-
±2.6
5
-
-
-
-
-
±10
10
µA
mA
µA
pF
pF
IN
-
DD1
OUT
0, 5
±2.6
7.5
15
±10
7.5
15
C
C
-
-
IN
Output Capacitance
-
-
OUT
NOTE:
1. Limits designate 100% testing, all other limits are designer’s parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications t , t = 10ns, C = 50pF
R
F
L
LIMITS
o
o
o
+25 C, -55 C
+125 C
V
DD
PARAMETER
SYMBOL
(V)
MIN
MAX
MIN
MAX
UNITS
ns
Read Cycle
t
5
360
-
505
-
RC
Access Time from Address Change (Note 1)
Access Time from Chip Select
t
5
-
-
360
360
-
-
505
505
ns
AA
AC
t
5
ns
6-33
CDP1823C/3
Read Cycle Dynamic Electrical Specifications t , t = 10ns, C = 50pF (Continued)
R
F
L
LIMITS
o
o
o
+25 C, -55 C
+125 C
V
DD
PARAMETER
Access Time from MRD (Note 1)
Data Hold Time After Read
NOTE:
SYMBOL
(V)
MIN
-
MAX
MIN
-
MAX
UNITS
ns
t
5
310
-
435
-
AM
t
5
50
70
ns
DH
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
t
RC
t
AA
ADDRESS
MRD
t
AM
(NOTE 1)
CS2, CS3, CS5
CS1, CS4
(NOTE 1)
t
AC
t
DH
90%
10%
VALID DATA
HIGH IMPEDANCE
NOTES:
1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output.
2. MWR is high during read operation. Timing measurement reference is 0.5V
.
DD
FIGURE 1. READ CYCLE TIMING DIAGRAM
Write Cycle Dynamic Electrical Specifications t , t = 10ns, C = 50pF
R
F
L
LIMITS
o
o
o
+25 C, -55 C
+125 C
V
(NOTE 2)
(NOTE 2)
DD
PARAMETER
SYMBOL
(V)
MIN
MAX
MIN
MAX
UNITS
ns
Write Cycle
t
5
280
70
-
-
-
-
-
400
100
100
200
100
-
-
-
-
-
WC
Address Setup Time (Note 1)
Address Hold Time
t
5
ns
AS
t
5
70
ns
AH
Write Pulse Width (Note 1)
Data to MWR Setup Time (Note 1)
t
5
140
70
ns
WW
t
5
ns
DS
6-34
CDP1823C/3
Write Cycle Dynamic Electrical Specifications t , t = 10ns, C = 50pF (Continued)
R
F
L
LIMITS
o
o
o
+25 C, -55 C
+125 C
V
(NOTE 2)
(NOTE 2)
DD
PARAMETER
Data Hold Time from MWR (Note 1)
Chip Select Setup
SYMBOL
(V)
MIN
MAX
MIN
70
MAX
UNITS
ns
t
5
50
-
-
-
-
DH
t
5
210
300
ns
CS
NOTES:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
2. Minimum timing to allow the indicated function to occur.
t
WC
t
AS
ADDRESS
t
AH
CS1, CS4
t
CS
CS2, CS3, CS5
t
WW
MWR
t
t
DS
DH
BUS 0-7
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING WAVEFORMS
Data Retention Specifications
TEST
CONDITIONS
LIMITS
o
o
o
+25 C, -55 C
+125 C
V
V
DD
DR
PARAMETER
SYMBOL
(V)
(V)
MIN
MAX
MIN
MAX
UNITS
Minimum Data Retention Voltage
(Note 1)
V
-
-
-
2
-
2.5
V
DR
Data Retention Quiescent Current
Chip Deselect to Data Retention Time
Recovery to Normal Operation Time
NOTE:
I
2
-
-
-
100
-
400
µA
ns
ns
DD
t
5
5
450
450
-
-
650
650
-
-
CDR
t
-
RC
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
6-35
CDP1823C/3
DATA RETENTION
MODE
V
DD
0.95 V
0.95 V
DD
DD
V
DR
t
t
t
t
RC
CDR
f
r
CS
V
V
IH
IH
V
V
IL
IL
FIGURE 3. LOW V
DATA RETENTION WAVEFORMS
DD
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
R
A0
A1
A2
A3
A4
A5
A6
01
A15
3
4
R
5
A14
6
R
7
A13
8
9
A12
A11
A10
A7
A8
A9
10
11
12
R = 10kΩ ±20%
PACKAGE
TEMPERATURE
DURATION
V
DD
o
D
125 C
160 Hrs
7V
0
1.6
2.2
5.0
6.6 7.2
10.0
V
DD
01
0
V
DD
0
A0
A1
V
DD
0
NOTE:
1. A1 - A11 are division by 2 based on A0.
FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
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and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6-36
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