CDP1824 [INTERSIL]
32-Word x 8-Bit Static RAM; 32字×8位的静态RAM
| 型号： | CDP1824 |
| 厂家： | 
Intersil |
| 描述： | 32-Word x 8-Bit Static RAM |
| 文件： | 总6页 (文件大小：29K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1824,
CDP1824C
March 1997
32-Word x 8-Bit Static RAM
Features
Description
• Fast Access Time
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
- V
- V
= 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
= 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
DD
DD
• No Precharge or Clock Required
The CDP1824 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Ordering Information
5V
10V
PACKAGE
TEMPERATURE RANGE
PKG. NO.
E18.3
o
o
CDP1824CE
CDP1824CEX
CDP1824CD
CDP1824E
PDIP
Burn-In
SBDIP
-40 C to +85 C
CDP1824EX
CDP1824D
E18.3
D18.3
o
o
-40 C to +85 C
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
OPERATIONAL MODES
FUNCTION
CS MRD MWR
DATA PINS STATUS
MA4
MA3
1
2
3
4
5
6
7
8
9
18 V
DD
READ
0
0
X
Output: High/LowDependent
on Data
17 MWR
16 MRD
15 CS
MA2
WRITE
0
1
1
0
Input: Output Disabled
MA1
Not
Selected
X
X
Output Disabled:
High-Impedance State
MA0
14 BUS 0
13 BUS 1
12 BUS 2
11 BUS 3
BUS 7
BUS 6
BUS 5
Standby
0
1
1
Output Disabled:
High-Impedance State
Logic 1 = High Logic 0 = Low X = Don’t Care
V
10
BUS 4
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1103.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-37
CDP1824, CDP1824C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
SS
SBDIP Package. . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
75
75
20
N/A
o
o
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
STG
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
DD
Lead Temperature (During Soldering)
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (T )
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
A
o
o
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
Recommended Operating Conditions At T = Full Package Temperature Range.For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
CONDITION
LIMITS
CDP1824D
CDP1824CD
PARAMETER
Supply Voltage Range
V
(V)
MIN
MAX
MIN
MAX
UNITS
DD
-
4
10.5
4
6.5
V
V
Recommended Input Voltage Range
Input Signal Rise or Fall Time (Note 1)
-
V
V
V
V
SS
-
DD
5
SS
-
DD
5
5
µs
µs
t , t
10
-
2
-
-
R
F
NOTE:
1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode.
o
o
Static Electrical Specifications At T = -40 C to +85 C, Except as Noted:
A
CONDITIONS
LIMITS
CDP1824
CDP1824C
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
(V)
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
µA
µA
mA
mA
mA
mA
V
Quiescent Device
Current
I
-
-
5
-
25
250
2.2
4.5
-1.1
-2.2
0
50
500
-
-
100
200
DD
-
-
10
5
-
1.8
3.6
-0.9
-1.8
-
-
-
-
Output Low (Sink)
Current
I
0.4
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
1.8
2.2
-
OL
0.5
10
5
-
-
-
-
Output High (Source)
Current
I
4.6
-
-0.9
-1.1
-
OH
9.5
10
5
-
-
-
-
Output Voltage
Low-Level
V
-
0.1
0.1
-
-
0
0.1
OL
-
10
5
-
0
-
-
-
V
Output Voltage
High-Level
V
-
-
4.9
9.9
-
5
4.9
5
-
V
OH
10
5
10
-
-
-
-
-
V
Input Low Voltage
Input High Voltage
Input Leakage Current
V
0.5, 4.5
1.9
1.5
3
-
-
1.5
V
IL
IH
IN
-
10
5
-
-
-
-
-
-
V
V
0.5, 9.5
1.9
-
3.5
7
-
-
3.5
-
V
-
10
5
-
-
-
-
-
-
-
-
-
V
I
Any
Input
0, 5
0, 10
0, 5
0, 10
-
± 0.1
± 0.1
4
± 1
± 1
8
± 0.1
± 1
-
µA
µA
mA
mA
10
5
-
-
4
-
Operating Current
(Note 2)
I
-
-
-
8
-
DD1
10
-
8
16
6-38
CDP1824, CDP1824C
o
o
Static Electrical Specifications At T = -40 C to +85 C, Except as Noted: (Continued)
A
CONDITIONS
LIMITS
CDP1824
CDP1824C
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
0, 5
0, 10
-
(V)
0, 5
0, 10
-
(V)
MIN
TYP
MAX
±2.0
±2.0
7.5
MIN
TYP
MAX
± 2
-
UNITS
µA
Three-State Output
Leakage Current
I
5
-
-
-
-
± 0.2
± 0.2
5
-
-
-
-
± 0.2
OUT
10
-
-
µA
Input Capacitance
Output Capacitance
NOTES:
C
5
7.5
15
pF
IN
C
-
-
-
10
15
10
pF
OUT
o
1. Typical values are for T = +25 C and nominal V
A
.
DD
2. Outputs open circuited; Cycle time = 1µs.
o
o
Dynamic Electrical Specifications at T = -40 C to +85 C, V ±5%, Input t , t = 10ns, C = 50pF, R = 200kΩ; See Figure 1
A
DD
R
F
L
L
LIMITS
TEST
CONDITIONS
CDP1824D, CDP1824E
CDP1824CD, CDP1824CE
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
PARAMETER
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DD
READ OPERATION
Access Time From
Address Change
t
5
-
-
-
-
-
-
400
200
300
150
300
150
710
320
710
320
710
320
-
-
-
-
-
-
400
710
ns
ns
ns
ns
ns
ns
AA
10
5
-
300
-
-
710
-
Access Time From
Chip Select
t
DOA
10
5
Output Active From MRD
t
300
-
710
-
AM
10
NOTES:
1. Time required by a limit device to allow for the indicated function.
2. Time required by a typical device to allow for the indicated function. Typical values are for T = +25 C and nominal V
o
.
DD
A
t
AM
(NOTE 1)
MRD
MA
t
AA
CS
(NOTE 1)
t
DOA
DATA OUT
HIGH IMPEDANCE
NOTES:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAMS
6-39
CDP1824, CDP1824C
o
o
Dynamic Electrical Specifications at T = -40 C to +85 C, V ±5%, Input t , t = 10ns, C = 50pF, R = 200kΩ; See Figure 2
A
DD
R
F
L
L
LIMITS
TEST
CONDITIONS
CDP1824D, CDP1824E
CDP1824CD, CDP1824CE
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
PARAMETER
WRITE OPERATION
Write Pulse Width
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DD
t
5
390
180
390
180
70
200
150
100
50
-
-
-
-
-
-
-
-
-
-
390
200
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRW
10
5
-
390
-
-
100
-
Data Setup Time
Data Hold Time
Chip Select Setup Time
Address Setup Time
NOTES:
t
DS
DH
10
5
t
40
70
-
40
-
10
5
35
20
t
425
215
640
390
210
110
500
300
425
-
210
-
CS
10
5
t
640
-
500
-
AS
10
1. Time required by a limit device to allow for the indicated function.
o
2. Time required by a typical device to allow for the indicated function. Typical values are for T = +25 C and nominal V
A
.
DD
MA
t
AS
CS
t
CS
t
WRW
MWR
BUS
t
t
DH
DS
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
DATA RETENTION
MODE
0.95 V
0.95 V
DD
DD
V
DD
V
DR
t
t
RC
t
t
CDR
R
F
(NOTE 1)
(NOTE 1)
V
V
IH
IH
CS
V
V
IL
IL
NOTE: t , t > 1µs.
R
F
FIGURE 3. LOW V
DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
DD
6-40
CDP1824, CDP1824C
o
o
Data Retention Specifications at T = -40 C to +85 C; See Figure 3
A
TEST CONDITIONS
LIMITS
CDP1824
MIN MAX
CDP1824C
V
(V)
DD
PARAMETER
Data Retention Voltage
SYMBOL
MIN
MAX
UNITS
V
V
-
2.5
-
-
10
-
2.5
-
40
-
DR
Data Retention Quiescent Current
I
V
V
= 2.5V
= 2.5V
-
-
600
-
µA
ns
DD
DR
Chip Deselect to Data Retention
Time
t
5
600
300
600
300
CDR
DR
10
5
-
-
ns
Recovery to Normal Operation Time
t
V
= 2.5V
-
600
-
-
ns
RC
DR
10
-
-
ns
MA4
MA3
2
1
3
4
5
MA2
MA1
MA0
32 X 8-BIT
ARRAY
ADDRESS
DECODER
SENSE
AMPL
16
17
15
MRD
MWR
CS
I/O BUFFERS
6
7
8
10 11 12 13 14
V
= 18
= 9
DD
V
SS
BUS BUS BUS BUS BUS BUS BUS BUS
7
6
5
4
3
2
1
0
FIGURE 4. FUNCTIONAL DIAGRAM
CPU/ROM SYSTEM
ADDRESS
RAM SYSTEM
MA0-MA7
MA0-MA7
MA0-MA7
MRD
TPA
TPA
MRD
MWR
MRD
MWR
RAM
CDP1824
ROM
CPU
CDP1802
CE0
CS
BUS0-BUS7
BUS0-BUS7
BUS0-BUS7
DATA
FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)
6-41
CDP1824, CDP1824C
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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6-42
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