ADC0804LCWM [INTERSIL]
8-Bit, Microprocessor- Compatible, A/D Converters; 8位，微处理器兼容， A / D转换器
| 型号： | ADC0804LCWM |
| 厂家： | 
Intersil |
| 描述： | 8-Bit, Microprocessor- Compatible, A/D Converters |
| 文件： | 总16页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
August 1997
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing The ADC0802 family are CMOS 8-Bit, successive-approxi-
Logic Required
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
Ordering Information
o
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ERROR
EXTERNAL CONDITIONS
/2 = 2.500V (No Adjustments)
TEMP. RANGE ( C)
PACKAGE
20 Ld PDIP
PKG. NO
E20.3
F20.3
1
± / LSB
V
V
0 to 70
2
REF
REF
DC
3
± / LSB
-40 to 85
-55 to 125
0 to 70
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
4
±1 LSB
F20.3
1
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
± / LSB
/2 Adjusted for Correct Full Scale
Reading
E20.3
F20.3
2
3
± / LSB
-40 to 85
-40 to 85
-55 to 125
0 to 70
20 Ld CERDIP
20 Ld SOIC
4
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
M20.3
F20.3
20 Ld CERDIP
20 Ld PDIP
ADC0804LCN
ADC0804LCD
ADC0804LCWM
V
/2 = 2.500V
DC
(No Adjustments)
E20.3
F20.3
REF
-40 to 85
-40 to 85
20 Ld CERDIP
20 Ld SOIC
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
1
20
CS
V+
+5V
10K
150pF
TOP VIEW
2
19
4
RD
CLK R
3
WR
CLK IN
5
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
V+ OR V
REF
20
19
18
CS
RD
INTR
DB
7
CLK R
DB
DB
6
WR
ANY
µPROCESSOR
0 (LSB)
DB
DB
DB
DB
DB
DB
5
4
3
2
1
0
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
17 DB
16 DB
15 DB
14 DB
CLK IN
INTR
1
6
7
V
(+)
(-)
IN
DIFF
INPUTS
2
V
IN
V
(+)
(-)
8
IN
3
AGND
/2
9
V
IN
V
V
/2
4
REF
DGND
REF
10
13
12
DB
DB
AGND
/2
5
V
REF
6
DGND 10
11 DB
7 (MSB)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number 3094.1
6-5
ADC0802, ADC0803, ADC0804
Functional Diagram
2
READ
RD
“1” = RESET SHIFT REGISTER
“0” = BUSY AND RESET STATE
1
CS
SET
Q
RESET
3
WR
INPUT PROTECTION
FOR ALL LOGIC INPUTS
CLK R
19
CLK
INPUT
TO INTERNAL
CIRCUITS
CLK A
CLKS
G1
RESET
D
CLK IN
BV = 30V
CLK
GEN
DFF1
4
Q
CLK OSC
START F/F
10
DGND
START
CONVERSION
CLK B
MSB
D
20
9
V+
(V
)
REF
LADDER
AND
DECODER
SUCCESSIVE
8-BIT
SHIFT
APPROX.
REGISTER
AND LATCH
REGISTER
IF RESET = “0”
INTR F/F
V
/2
R
REF
RESET
Q
DAC
LSB
AGND
V
8
OUT
CLK A
V+
D
DFF2
Q
COMP
-
+
6
7
+
∑
V
(+)
(-)
IN
Q
5
-
XFER
THREE-STATE
OUTPUT LATCHES
SET
G2
V
IN
MSB
LSB
INTR
CONV. COMPL.
8 X 1/f
11 12 13 14 15 16 17 18
DIGITAL OUTPUTS
THREE-STATE CONTROL
“1” = OUTPUT ENABLE
6-6
ADC0802, ADC0803, ADC0804
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Voltage at Any Input . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V +0.3V)
Thermal Resistance (Typical, Note 1)
θ
( C/W)
125
80
θ
( C/W)
JA
JC
+
PDIP Package . . . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
N/A
20
N/A
Operating Conditions
120
Temperature Range
ADC0802/03LD. . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
ADC0802/03/04LCD . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
ADC0802/03/04LCN . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
o
o
o
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
o
o
o
o
o
o
o
o
o
o
ADC0803/04LCWM . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications (Notes 1, 7)
PARAMETER
TEST CONDITIONS
MIN
= 640kHz, Unless Otherwise Specified
CLK
TYP
MAX
UNITS
o
CONVERTER SPECIFICATIONS V+ = 5V, T = 25 C and f
A
Total Unadjusted Error
1
ADC0802
ADC0803
V
V
/2 = 2.500V
-
-
-
-
± /
LSB
LSB
REF
REF
2
2
1
/2 Adjusted for Correct Full
± /
Scale Reading
ADC0804
V
/2 = 2.500V
-
-
±1
LSB
kΩ
REF
V
/2 Input Resistance
Input Resistance at Pin 9
(Note 2)
1.0
1.3
-
REF
Analog Input Voltage Range
DC Common-Mode Rejection
Power Supply Sensitivity
GND-0.05
-
(V+) + 0.05
1
V
1
Over Analog Input Voltage Range
-
-
± /
± /
LSB
LSB
16
8
1
1
V+ = 5V ±10% Over Allowed Input
± /
16
± /
8
Voltage Range
o
o
CONVERTER SPECIFICATIONS V+ = 5V, 0 C to 70 C and f
= 640kHz, Unless Otherwise Specified
CLK
Total Unadjusted Error
1
ADC0802
ADC0803
V
V
/2 = 2.500V
-
-
-
-
± /
LSB
LSB
REF
REF
2
2
1
/2 Adjusted for Correct Full
± /
Scale Reading
ADC0804
V
/2 = 2.500V
-
-
±1
LSB
kΩ
REF
V
/2 Input Resistance
Input Resistance at Pin 9
(Note 2)
1.0
1.3
-
REF
Analog Input Voltage Range
DC Common-Mode Rejection
Power Supply Sensitivity
GND-0.05
-
(V+) + 0.05
1
V
1
Over Analog Input Voltage Range
-
-
± /
± /
LSB
LSB
8
4
1
1
V+ = 5V ±10% Over Allowed Input
± /
± /
16
8
Voltage Range
o
o
CONVERTER SPECIFICATIONS V+ = 5V, -25 C to 85 C and f
= 640kHz, Unless Otherwise Specified
CLK
Total Unadjusted Error
3
ADC0802
ADC0803
V
V
/2 = 2.500V
-
-
-
-
± /
LSB
LSB
REF
REF
4
4
3
/2 Adjusted for Correct Full
± /
Scale Reading
ADC0804
V
/2 = 2.500V
-
-
±1
LSB
kΩ
REF
V
/2 Input Resistance
Input Resistance at Pin 9
(Note 2)
1.0
1.3
-
REF
Analog Input Voltage Range
DC Common-Mode Rejection
Power Supply Sensitivity
GND-0.05
-
(V+) + 0.05
1
V
1
Over Analog Input Voltage Range
-
-
± /
± /
LSB
LSB
8
4
1
1
V+ = 5V ±10% Over Allowed Input
± /
± /
16
8
Voltage Range
6-7
ADC0802, ADC0803, ADC0804
Electrical Specifications (Notes 1, 7) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
o
o
CONVERTER SPECIFICATIONS V+ = 5V, -55 C to 125 C and f
= 640kHz, Unless Otherwise Specified
CLK
Total Unadjusted Error
ADC0802
ADC0803
V
V
/2 = 2.500V
-
-
-
-
±1
±1
LSB
LSB
REF
REF
/2 Adjusted for Correct Full
Scale Reading
V
/2 Input Resistance
Input Resistance at Pin 9
(Note 2)
1.0
1.3
-
kΩ
V
REF
Analog Input Voltage Range
DC Common-Mode Rejection
Power Supply Sensitivity
GND-0.05
-
(V+) + 0.05
1
1
Over Analog Input Voltage Range
-
-
± /
± /
LSB
LSB
8
4
1
1
V+ = 5V ±10% Over Allowed Input
± /
± /
8
4
Voltage Range
o
AC TIMING SPECIFICATIONS V+ = 5V, and T = 25 C, Unless Otherwise Specified
A
Clock Frequency, f
V+ = 6V (Note 3)
V+ = 5V
100
100
62
640
640
-
1280
800
73
kHz
kHz
CLK
Clock Periods per Conversion
(Note 4), t
Clocks/Conv
CONV
Conversion Rate In Free-Running INTR tied to WR with CS = 0V,
-
100
-
-
-
8888
-
Conv/s
ns
Mode, CR
f
= 640kHz
CLK
CS = 0V (Note 5)
Width of WR Input (Start Pulse
Width), t
W(WR)I
Access Time (Delay from Falling C = 100pF (Use Bus Driver IC for
135
200
ns
L
Edge of RD to Output Data Valid), Larger C
L)
t
ACC
Three-State Control (Delay from
Rising Edge of RD to Hl-Z State), (See Three-State Test Circuits)
, t
C
= 10pF, R = 10K
-
125
250
ns
L
L
t
1H 0H
Delay from Falling Edge of WR to
Reset of INTR, t , t
-
-
-
300
450
ns
pF
pF
WI RI
Input Capacitance of Logic
Control Inputs, C
5
-
-
IN
Three-State Output Capacitance
(Data Buffers), C
5
OUT
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and T
CONTROL INPUTS (Note 6)
to T
, Unless Otherwise Specified
MIN
MAX
Logic “1“ Input Voltage (Except
Pin 4 CLK IN), V
V+ = 5.25V
2.0
-
-
V+
0.8
3.5
2.1
V
V
V
V
INH
Logic “0“ Input Voltage (Except
Pin 4 CLK IN), V
V+ = 4.75V
-
INL
CLK IN (Pin 4) Positive Going
Threshold Voltage, V+
2.7
1.5
3.1
1.8
CLK
CLK IN (Pin 4) Negative Going
Threshold Voltage, V-
CLK
CLK IN (Pin 4) Hysteresis, V
0.6
-
1.3
2.0
1
V
H
Logic “1” Input Current
(All Inputs), I
INHI
V
V
= 5V
= 0V
0.005
µΑ
lN
lN
Logic “0” Input Current
(All Inputs), I
-1
-
-0.005
1.3
-
µA
INLO
o
Supply Current (Includes Ladder
Current), I+
f
= 640kHz,T = 25 C
2.5
mA
CLK
A
and CS = Hl
DATA OUTPUTS AND INTR
Logic “0” Output Voltage, V
OL
l
= 1.6mA, V+ = 4.75V
-
-
0.4
V
O
6-8
ADC0802, ADC0803, ADC0804
Electrical Specifications (Notes 1, 7) (Continued)
PARAMETER
TEST CONDITIONS
MIN
2.4
-3
TYP
MAX
UNITS
V
Logic “1” Output Voltage, V
l
= -360µA, V+ = 4.75V
O
-
-
-
-
OH
Three-State Disabled Output
Leakage (All Data Buffers), I
V
= 0V
= 5V
µA
OUT
LO
V
-
-
3
-
µA
OUT
o
Output Short Circuit Current,
V
Short to Gnd T = 25 C
A
4.5
6
mA
OUT
I
SOURCE
o
Output Short Circuit Current,
V
Short to V+ T = 25 C
9.0
16
-
mA
OUT
A
I
SINK
NOTES:
1. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the
DGND, being careful to avoid ground loops.
2. For V
≥ V the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which
IN(+)
IN(-)
will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful,
during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated tem-
peratures, and cause errors for analog inputs near full scale. As long as the analog V does not exceed the supply voltage by more than
IN
50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply volt-
age of 4.950V over temperature variations, initial tolerance and loading.
3. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion
process.
5. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse
width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see
Timing Diagrams).
6. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
7. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span
exists (for example: 0.5V to 4V full scale) the V
input can be adjusted to achieve this. See the Zero Error description in this data sheet.
IN(-)
Timing Waveforms
t = 20ns
r
t
r
2.4V
0.8V
V+
90%
50%
10%
RD
RD
DATA
OUTPUT
CS
t
1H
90%
V
OH
C
10K
L
DATA
OUTPUTS
GND
FIGURE 1A. t
FIGURE 1B. t , C = 10pF
1H
1H
L
t = 20ns
r
V+
V+
t
r
2.4V
90%
50%
RD
10K
10%
0.8V
V+
RD
CS
DATA
t
0H
OUTPUT
C
L
DATA
OUTPUTS
10%
V
OI
FIGURE 1C. t
FIGURE 1D. t , C = 10pF
0H
0H
L
FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS
6-9
ADC0802, ADC0803, ADC0804
Typical Performance Curves
1.8
500
400
300
200
100
o
o
-55 C TO 125 C
1.7
1.6
1.5
1.4
1.3
4.50
4.75
5.00
5.25
5.50
0
200
400
600
800
1000
LOAD CAPACITANCE (pF)
V+ SUPPLY VOLTAGE (V)
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
DATA VALID vs LOAD CAPACITANCE
3.5
3.1
1000
R = 10K
V
T(+)
R = 50K
2.7
2.3
1.9
1.5
o
o
-55 C TO 125 C
V
T(-)
R = 20K
100
4.50
4.75
5.00
5.25
5.50
10
100
1000
V+ SUPPLY VOLTAGE (V)
CLOCK CAPACITOR (pF)
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY VOLTAGE
FIGURE 5. f vs CLOCK CAPACITOR
CLK
16
14
V
= V
= 0V
7
IN(+)
IN(-)
ASSUMES V
= 2mV
OS
6
V+ = 4.5V
THIS SHOWS THE NEED
FOR A ZERO ADJUSTMENT
IF THE SPAN IS REDUCED
12
10
8
5
4
3
6
2
1
0
V+ = 5V
4
2
V+ = 6V
1600 2000
0
0.01
0
400
800
f
1200
(kHz)
0.1
1.0
5
V
/2 (V)
CLK
REF
FIGURE 6. FULL SCALE ERROR vs f
CLK
FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR
6-10
ADC0802, ADC0803, ADC0804
Typical Performance Curves (Continued)
8
1.6
1.5
1.4
1.3
1.2
V+ = 5V
f
= 640kHz
V+ = 5.5V
CLK
7
DATA OUTPUT
BUFFERS
6
5
4
3
2
I
SOURCE
= 2.4V
V
OUT
V+ = 5.0V
-I
V
SINK
OUT
1.1
1.0
V+ = 4.5V
100
= 0.4V
0
-50
-25
25
50
75
100
125
-50
-25
0
25
T AMBIENT TEMPERATURE ( C)
A
50
75
125
o
o
T
AMBIENT TEMPERATURE ( C)
A
FIGURE 8. OUTPUT CURRENT vs TEMPERATURE
FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE
Timing Diagrams
CS
WR
t
WI
“BUSY”
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
t
W(WR)I
DATA IS VALID IN
OUTPUT LATCHES
“NOT BUSY”
1 TO 8 x 1/f
INTERNAL T
CLK
C
(LAST DATA READ)
INTR
INTR
ASSERTED
(LAST DATA NOT READ)
1
t
VI
/
f
CLK
2
FIGURE 10A. START CONVERSION
INTR RESET
INTR
CS
t
RI
RD
THREE-STATE
(HI-Z)
VALID
DATA
VALID
DATA
DATA
OUTPUTS
t
ACC
t
, t
1H 0H
FIGURE 10B. OUTPUT ENABLE AND RESET INTR
6-11
ADC0802, ADC0803, ADC0804
+1 LSB
1
3
5
4
1
+ / LSB
2
D + 1
D
5 6
0
QUANTIZATION ERROR
*
3 4
1
D - 1
- / LSB
2
2
6
1 2
-1 LSB
A - 1
A + 1
A - 1
ANALOG INPUT (V )
IN
A
A + 1
A
ANALOG INPUT (V
)
IN
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D
+1 LSB
1
5
D + 1
D
6
3
6
3
QUANTIZATION
ERROR
0
*
4
1
D - 1
2
4
2
-1 LSB
A - 1
A + 1
A - 1
A
A + 1
A
ANALOG INPUT (V
)
ANALOG INPUT (V
ERROR PLOT
)
IN
IN
TRANSFER FUNCTION
1
FIGURE 11B. ACCURACY = ± / LSB
2
FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER
constant negative slope and the abrupt upside steps are always
1 LSB in magnitude, unless the device has missing codes.
Understanding A/D Error Specs
A perfect A/D transfer characteristic (staircase wave-form) is
shown in Figure 11A. The horizontal scale is analog input volt-
age and the particular points labeled are in steps of 1 LSB
Detailed Description
The functional diagram of the ADC0802 series of A/D
converters operates on the successive approximation princi-
ple (see Application Notes AN016 and AN020 for a more
detailed description of this principle). Analog switches are
closed sequentially by successive-approximation logic until
(19.53mV with 2.5V tied to the V
/2 pin). The digital output
REF
codes which correspond to these inputs are shown as D-1, D,
and D+1. For the perfect A/D, not only will center-value (A - 1,
A, A + 1, . . .) analog inputs produce the correct output digital
codes, but also each riser (the transitions between adjacent
the analog differential input voltage [V
- V ] matches
1
lN(+)
lN(-)
output codes) will be located ± / LSB away from each center-
2
a voltage derived from a tapped resistor string across the
reference voltage. The most significant bit is tested first and
after 8 comparisons (64 clock cycles), an 8-bit binary code
(1111 1111 = full scale) is transferred to an output latch.
value. As shown, the risers are ideal and have no width. Correct
digital output codes will be provided for a range of analog input
1
voltages which extend ± / LSB from the ideal center-values.
2
Each tread (the range of analog input voltage which provides
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set
high. As long as the CS input and WR input remain low, the
A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a low-
to-high transition. After the requisite number of clock pulses to
complete the conversion, the INTR pin will make a high-to-low
transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion. A RD
operation (with CS low) will clear the INTR line high again.
the same digital output code) is therefore 1 LSB wide.
The error curve of Figure 11B shows the worst case transfer
function for the ADC0802. Here the specification guarantees
that if we apply an analog input equal to the LSB analog volt-
age center-value, the A/D will produce the correct digital code.
Next to each transfer function is shown the corresponding error
plot. Notice that the error includes the quantization uncertainty of
the A/D. For example, the error at point 1 of Figure 11A is
1
1
+ / LSB because the digital code appeared / LSB in advance
2
2
of the center-value of the tread. The error plots always have a
6-12
ADC0802, ADC0803, ADC0804
The device may be operated in the free-running mode by con- to automatically subtract a fixed voltage value from the input
necting INTR to the WR input with CS = 0. To ensure start-up reading (tare correction). This is also useful in 4mA - 20mA cur-
under all possible conditions, an external WR pulse is rent loop conversion. In addition, common-mode noise can be
required during the first power-up cycle. A conversion-in-pro- reduced by use of the differential input.
cess can be interrupted by issuing a second start command.
1
The time interval between sampling V
IN(+)
and V is 4 /
lN(-) 2
Digital Operation
clock periods. The maximum error voltage due to this slight
time difference between the input voltage samples is given by:
The converter is started by having CS and WR simultaneously
low. This sets the start flip-flop (F/F) and the resulting “1” level
resets the 8-bit shift register, resets the Interrupt (INTR) F/F
and inputs a “1” to the D flip-flop, DFF1, which is at the input
end of the 8-bit shift register. Internal clock signals then trans-
fer this “1” to the Q output of DFF1. The AND gate, G1, com-
bines this “1” output with a clock signal to provide a reset
signal to the start F/F. If the set signal is no longer present
(either WR or CS is a “1”), the start F/F is reset and the 8-bit
shift register then can have the “1” clocked in, which starts the
conversion process. If the set signal were to still be present,
this reset pulse would have no effect (both outputs of the start
F/F would be at a “1” level) and the 8-bit shift register would
continue to be held in the reset mode. This allows for asyn-
chronous or wide CS and WR signals.
4.5
------------
∆V (MAX) = (V
)(2πf )
CM
E
PEAK
f
CLK
where:
∆V is the error voltage due to sampling delay,
E
V
f
is the peak value of the common-mode voltage,
PEAK
is the common-mode frequency.
CM
For example, with a 60Hz common-mode frequency, f
,
CM
1
and a 640kHz A/D clock, f
, keeping this error to / LSB
CLK
4
(~5mV) would allow a common-mode voltage, V
by:
, given
PEAK
∆V
E(MAX)(f
)
CLK
V
= -------------------------------------------------- ,
PEAK
(2πf
)(4.5)
CM
After the “1” is clocked through the 8-bit shift register (which
completes the SAR operation) it appears as the input to
DFF2. As soon as this “1” is output from the shift register, the
AND gate, G2, causes the new digital word to transfer to the
Three-State output latches. When DFF2 is subsequently
clocked, the Q output makes a high-to-low transition which
causes the INTR F/F to set. An inverting buffer then supplies
the INTR output signal.
or
V
–3
3
(5 × 10 )(640 × 10 )
----------------------------------------------------------
(6.28)(60)(4.5)
=
1.9V.
PEAK
The allowed range of analog input voltage usually places
more severe restrictions on input common-mode voltage
levels than this.
An analog input voltage with a reduced span and a relatively
large zero offset can be easily handled by making use of the
differential input (see Reference Voltage Span Adjust).
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the three-
state output latches will be enabled to provide the 8-bit digital
outputs.
Analog Input Current
The internal switching action causes displacement currents to
flow at the analog inputs. The voltage on the on-chip capaci-
tance to ground is switched through the analog differential
input voltage, resulting in proportional currents entering the
Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
TTL logic voltage levels. These signals are essentially equiva-
lent to the standard A/D Start and Output Enable control sig-
nals, and are active low to allow an easy interface to
microprocessor control busses. For non-microprocessor
based applications, the CS input (pin 1) can be grounded and
the standard A/D Start function obtained by an active low
pulse at the WR input (pin 3). The Output Enable function is
achieved by an active low pulse at the RD input (pin 2).
V
input and leaving the V input. These current tran-
IN(+)
IN(-)
sients occur at the leading edge of the internal clocks. They
rapidly decay and do not inherently cause errors as the on-
chip comparator is strobed at the end of the clock perIod.
Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resistances
of the analog signal sources. This charge pumping action is
Analog Operation
The analog comparisons are performed by a capacitive
charge summing circuit. Three capacitors (with precise
ratioed values) share a common node with the input to an
auto-zeroed comparator. The input capacitor is switched
worse for continuous conversions with the V
input voltage
IN(+)
at full scale. For a 640kHz clock frequency with the V
IN(+)
input at 5V, this DC current is at a maximum of approximately
5µA. Therefore, bypass capacitors should not be used at
between V
and V , while two ratioed reference capaci-
lN(+)
lN(-)
the analog inputs or the V
/2 pin for high resistance
REF
tors are switched between taps on the reference voltage
divider string. The net charge corresponds to the weighted dif-
ference between the input and the current total value set by
the successive approximation register. A correction is made to
offset the comparison by / LSB (see Figure 11A).
2
sources (>1kΩ). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to mini-
mize capacitor size, the effects of the voltage drop across this
input resistance, due to the average value of the input current,
can be compensated by a full scale adjustment while the
given source resistor and input bypass capacitor are both in
place. This is possible because the average value of the input
current is a precise linear function of the differential input
voltage at a constant conversion rate.
1
Analog Differential Voltage Inputs and Common-Mode
Rejection
This A/D gains considerable applications flexibility from the ana-
log differential voltage input. The V
input (pin 7) can be used
lN(-)
6-13
ADC0802, ADC0803, ADC0804
Input Source Resistance
V+
(V
)
REF
Large values of source resistance where an input bypass
capacitor is not used will not cause errors since the input
currents settle out prior to the comparison time. If a low-
pass filter is required in the system, use a low-value series
resistor (≤1kΩ) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance
applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs
will minimize EMI due to the series lead inductance of a long
wire. A 100Ω series resistor can be used to isolate this
capacitor (both the R and C are placed outside the feedback
loop) from the output of an op amp, if used.
20
R
9
V
/2
REF
DIGITAL
CIRCUITS
Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize stray signal pickup (EMI).
Both EMI and undesired digital-clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 5kΩ. Larger values of
source resistance can cause undesired signal pickup. Input
bypass capacitors, placed from the analog inputs to ground,
will eliminate this pickup but can create analog scale errors as
these capacitors will average the transient input switching cur-
rents of the A/D (see Analog Input Current). This scale error
depends on both a large source resistance and the use of an
input bypass capacitor. This error can be compensated by a
full scale adjustment of the A/D (see Full Scale Adjustment)
with the source resistance and input bypass capacitor in
place, and the desired conversion rate.
ANALOG
CIRCUITS
R
DECODE
8
10
AGND
DGND
FIGURE 12. THE V
DESIGN ON THE IC
REFERENCE
Reference Voltage Span Adjust
V
REF
(5V)
For maximum application flexibility, these A/Ds have been
designed to accommodate a 5V, 2.5V or an adjusted voltage
reference. This has been achieved in the design of the IC as
shown in Figure 12.
ICL7611
5V
300
0.1µF
-
“SPAN”/2
TO V
TO V
/2
REF
IN(-)
FS
ADJ.
+
1
Notice that the reference voltage for the IC is either / of the
2
voltage which is applied to the V+ supply pin, or is equal to
the voltage which is externally forced at the V
/2 pin. This
REF
allows for a pseudo-ratiometric voltage reference using, for
the V+ supply, a 5V reference voltage. Alternatively, a volt-
ZERO SHIFT VOLTAGE
age less than 2.5V can be applied to the V
/2 input. The
REF
/2 input is 2 to allow this factor of 2
internal gain to the V
REF
reduction in the reference voltage.
FIGURE 13. OFFSETTING THE ZERO OF THE ADC0802 AND
PERFORMING AN INPUT RANGE (SPAN)
ADJUSTMENT
Such an adjusted reference voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from 0.5V to
3.5V, instead of 0V to 5V, the span would be 3V. With 0.5V
5V
(V
)
REF
applied to the V
voltage can be made equal to / of the 3V span or 1.5V. The
pin to absorb the offset, the reference
lN(-)
1
2
R
A/D now will encode the V
signal from 0.5V to 3.5V with
lN(+)
the 0.5V input corresponding to zero and the 3.5V input corre-
sponding to full scale. The full 8 bits of resolution are therefore
applied over this reduced analog input voltage range. The req-
uisite connections are shown in Figure 13. For expanded
scale inputs, the circuits of Figures 14 and 15 can be used.
2R
20
6
7
V
± 10V
V
V+
IN
IN(+)
+
10µF
ADC0802-
ADC0804
2R
V
IN(-)
FIGURE 14. HANDLING ±10V ANALOG INPUT RANGE
6-14
ADC0802, ADC0803, ADC0804
Full Scale Adjust
5V
(V
)
REF
The full scale adjustment can be made by applying a
1
differential input voltage which is 1 / LSB down from the
2
R
desired analog full scale voltage range and then adjusting
the magnitude of the V
/2 input (pin 9) for a digital output
code which is just changing from 1111 1110 to 1111 1111.
REF
R
20
6
7
V
±5V
V
V+
IN
IN(+)
+
When offsetting the zero and using a span-adjusted V
voltage, the full scale adjustment is made by inputting V
/2
REF
10µF
ADC0802-
ADC0804
MlN
to the V
input of the A/D and applying a voltage to the
IN(-)
V
input which is given by:
IN(+)
V
IN(-)
(V
– V
)
MIN
MAX
-----------------------------------------
,
V
f
= V
– 1.5
MAX
IN(+) SADJ
256
where:
FIGURE 15. HANDLING ±5V ANALOG INPUT RANGE
V
= the high end of the analog input range,
MAX
and
Reference Accuracy Requirements
The converter can be operated in a pseudo-ratiometric
mode or an absolute mode. In ratiometric converter applica-
tions, the magnitude of the reference voltage is a factor in
both the output of the source transducer and the output of
the A/D converter and therefore cancels out in the final digi-
tal output code. In absolute conversion applicatIons, both the
initial value and the temperature stability of the reference
voltage are important accuracy factors in the operation of the
V
= the low end (the offset zero) of the analog range.
MIN
(Both are ground referenced.)
Clocking Option
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
A/D converter. For V
/2 voltages of 2.5V nominal value,
REF
initial errors of ±10mV will cause conversion errors of ±1
LSB due to the gain of 2 of the V /2 input. In reduced
REF
span applications, the initial value and the stability of the
/2 input voltage become even more important. For
CLK R
19
V
REF
1
1.1 RC
example, if the span is reduced to 2.5V, the analog input LSB
voltage value is correspondingly reduced from 20mV (5V
f
ADC0802-
ADC0804
CLK
R
R
10kΩ
span) to 10mV and 1 LSB at the V
REF
/2 input becomes
CLK IN
C
5mV. As can be seen, this reduces the allowed initial toler-
ance of the reference voltage and requires correspondingly
less absolute change with temperature variations. Note that
spans smaller than 2.5V place even tighter requirements on
the initial accuracy and stability of the reference source.
4
CLK
In general, the reference voltage will require an initial
adjustment. Errors due to an improper value of reference
voltage appear as full scale errors in the A/D transfer func-
tion. IC voltage regulators may be used for references if the
ambient temperature changes are not excessive.
FIGURE 16. SELF-CLOCKING THE A/D
Heavy capacitive or DC loading of the CLK R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50pF, such as driving up to 7 A/D converter
clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the CLK R pin (do not use a standard TTL buffer).
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
, is not ground, a
lN(MlN)
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by bias-
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in progress is not completed. The data from the
previous conversion remain in this latch.
ing the A/D V
input at this V value (see Applications
IN(-)
lN(MlN)
section). This utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
IN(+)
input and applying a small magnitude
input. Zero error is the difference
IN(-)
Continuous Conversions
between the actual DC input voltage which is necessary to
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-
up cycle to insure circuit operation. See Figure 17 for details.
just cause an output digital code transition from 0000 0000 to
1
1
0000 0001 and the ideal / LSB value ( / LSB = 9.8mV for
2
2
V
/2 = 2.500V).
REF
6-15
ADC0802, ADC0803, ADC0804
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup; therefore, shielded
leads may be necessary in many applications.
10K
5V (V
)
REF
ADC0802 - ADC0804
150pF
A single-point analog ground should be used which is separate
from the logic ground points. The power supply bypass capaci-
tor and the self-clockIng capacitor (if used) should both be
1
2
3
4
5
6
7
8
9
CS
V+ 20
+
RD
CLK R
19
18
17
16
15
14
10µF
DB
DB
DB
DB
DB
WR
0
1
2
3
4
LSB
returned to digital ground. Any V
/2 bypass capacitors, ana-
REF
N.O.
CLK IN
INTR
log input filter capacitors, or input signal shielding should be
returned to the analog ground point. A test for proper grounding
START
V
V
(+)
(-)
is to measure the zero error of the A/D converter. Zero errors in
IN
IN
DATA
ANALOG
INPUTS
1
OUTPUTS
excess of
/ LSB can usually be traced to improper board
4
layout and wiring (see Zero Error for measurement). Further
information can be found in Application Note AN018.
AGND
/2
DB 13
5
V
DB 12
6
REF
MSB
10 DGND
DB 11
7
Testing the A/D Converter
There are many degrees of complexity associated with testing
an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 18.
FIGURE 17. FREE-RUNNING CONNECTION
Driving the Data Bus
For ease of testing, the V
with 2.560V and a V+ supply voltage of 5.12V should be
used. This provides an LSB value of 20mV.
/2 (pin 9) should be supplied
This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuItry, which is tied to the data
bus, will add to the total capacitive loading, even in three-
state (high-impedance mode). Back plane busing also
greatly adds to the stray capacitance of the data bus.
REF
If a full scale adjustment is to be made, an analog input volt-
1
age of 5.090V (5.120 - 1 / LSB) should be applied to the
2
V
V
pin with the V pin grounded. The value of the
/2 input voltage should be adjusted until the digital out-
IN(+)
REF
IN(-)
There are some alternatives available to the designer to han-
dle this problem. Basically, the capacitive loading of the data
bus slows down the response time, even though DC specifi-
cations are still met. For systems operating with a relatively
slow CPU clock frequency, more time is available in which to
establish proper logic levels on the bus and therefore higher
capacitive loads can be driven (see Typical Performance
Curves).
put code is just changing from 1111 1110 to 1111 1111. This
value of V /2 should then be used for all the tests.
REF
The digital-output LED display can be decoded by dividing the 8
bits into 2 hex characters, one with the 4 most-significant bits
(MS) and one with the 4 least-significant bits (LS). The output is
then interpreted as a sum of fractions times the full scale voltage:
MS LS
16 256
V
=
-------- + --------- (5.12)V .
OUT
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock-extending circuits (6800).
10kΩ
Finally, if time is short and capacitive loading is high,
external bus drivers must be used. These can be three-state
buffers (low power Schottky is recommended, such as the
74LS240 series) or special higher-drive-current products
which are designed as bus drivers. High-current bipolar bus
drivers with PNP inputs are recommended.
150pF
5.120V
10µF
TANTALUM
1
2
3
20
19
18
17
16
15
14
13
12
11
+
LSB
N.O.
4
5
START
(+)
ADC0802-
ADC0804
Power Supplies
V
6
IN
0.1µF
5V
Noise spikes on the V+ supply line can cause conversion
errors as the comparator will respond to this noise. A
low-inductance tantalum filter capacitor should be used
close to the converter V+ pin, and values of 1µF or greater
are recommended. If an unregulated voltage is available in
the system, a separate 5V voltage regulator for the converter
(and other analog circuitry) will greatly reduce digital noise
on the V+ supply. An lCL7663 can be used to regulate such
a supply from an input as low as 5.2V.
7
AGND
8
2.560V
/2
9
V
REF
MSB
10
0.1µF
1.3kΩ
LEDs
(8)
(8)
DGND
FIGURE 18. BASIC TESTER FOR THE A/D
For example, for an output LED display of 1011 0110, the
MS character is hex B (decimal 11) and the LS character is
hex (and decimal) 6, so:
Wiring and Hook-Up Precautions
Standard digital wire-wrap sockets are not satisfactory for
breadboarding with this A/D converter. Sockets on PC
boards can be used. All logic signal wires and leads should
be grouped and kept as far away as possible from the analog
11
------ + --------- (5.12) = 3.64V.
16 256
6
V
=
OUT
6-16
ADC0802, ADC0803, ADC0804
Figures 19 and 20 show more sophisticated test circuits.
Interfacing the Z-80 and 8085
The Z-80 and 8085 control buses are slightly different from
that of the 8080. General RD and WR strobes are provided
and separate memory request, MREQ, and I/O request,
IORQ, signals have to be combined with the generalized
strobes to provide the appropriate signals. An advantage of
operating the A/D in I/O space with the Z-80 is that the CPU
will automatically insert one wait state (the RD and WR
strobes are extended one clock period) to allow more time
for the I/O devices to respond. Logic to map the A/D in I/O
space is shown in Figure 22. By using MREQ in place of
IORQ, a memory-mapped configuration results.
V
8-BIT
A/D UNDER
TEST
ANALOG OUTPUT
10-BIT
DAC
R
R
“B”
ANALOG
INPUTS
-
+
“C”
A1
R
R
100R
100X ANALOG
ERROR VOLTAGE
-
Additional I/O advantages exist as software DMA routines are
available and use can be made of the output data transfer
which exists on the upper 8 address lines (A8 to A15) during
I/O input instructions. For example, MUX channel selection for
the A/D can be accomplished with this operating mode.
+
“A”
A2
FIGURE 19. A/D TESTER WITH ANALOG ERROR OUTPUT. THIS
CIRCUIT CAN BE USED TO GENERATE “ERROR
PLOTS” OF FIGURE 11.
The 8085 also provides a generalized RD and WR strobe, with
an IO/M line to distinguish I/O and memory requests. The cir-
cuit of Figure 22 can again be used, with IO/M in place of IORQ
for a memory-mapped interface, and an extra inverter (or the
logic equivalent) to provide IO/M for an I/O-mapped connection.
DIGITAL
INPUTS
DIGITAL
OUTPUTS
V
ANALOG
10-BIT
DAC
A/D UNDER
TEST
Interfacing 6800 Microprocessor Derivatives (6502, etc.)
The control bus for the 6800 microprocessor derivatives does
not use the RD and WR strobe signals. Instead it employs a
single R/W line and additional timing, if needed, can be derived
from the φ2 clock. All I/O devices are memory-mapped in the
6800 system, and a special signal, VMA, indicates that the cur-
rent address is valid. Figure 23 shows an interface schematic
FIGURE 20. BASIC “DIGITAL” A/D TESTER
Typical Applications
Interfacing 8080/85 or Z-80 Microprocessors
This converter has been designed to directly interface with
8080/85 or Z-80 Microprocessors. The three-state output
capability of the A/D eliminates the need for a peripheral
interface device, although address decoding is still required
to generate the appropriate CS for the converter. The A/D
can be mapped into memory space (using standard mem-
ory-address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an I/O device by using the
I/OR and I/OW strobes and decoding the address bits A0 →
A7 (or address bits A8 → A15, since they will contain the
same 8-bit address information) to obtain the CS input.
Using the I/O space provides 256 additional addresses and
may allow a simpler 8-bit address decoder, but the data can
only be input to the accumulator. To make use of the addi-
tional memory reference instructions, the A/D should be
mapped into memory space. See AN020 for more discus-
sion of memory-mapped vs I/O-mapped interfaces. An
example of an A/D in I/O space is shown in Figure 21.
where the A/D is memory-mapped in the 6800 system. For sim-
1
plicity, the CS decoding is shown using / DM8092. Note that
2
in many 6800 systems, an already decoded 4/5 line is brought
out to the common bus at pin 21. This can be tied directly to the
CS pin of the A/D, provided that no other devices are
addressed at HEX ADDR: 4XXX or 5XXX.
In Figure 24 the ADC0802 series is interfaced to the MC6800
microprocessor through (the arbitrarily chosen) Port B of the
MC6820 or MC6821 Peripheral Interface Adapter (PlA). Here
the CS pin of the A/D is grounded since the PlA is already
memory-mapped in the MC6800 system and no CS decoding
is necessary. Also notice that the A/D output data lines are con-
nected to the microprocessor bus under program control
through the PlA and therefore the A/D RD pin can be grounded.
Application Notes
AnswerFAX
The standard control-bus signals of the 8080 (CS, RD and
WR) can be directly wired to the digital control inputs of the
A/D, since the bus timing requirements, to allow both starting
the converter, and outputting the data onto the data bus, are
met. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100pF.
NOTE #
DESCRIPTION
DOC. #
AN016 “Selecting A/D Converters”
9016
AN018 “Do’s and Don’ts of Applying A/D
Converters”
9018
AN020 “A Cookbook Approach to High Speed
Data Acquisition and Microprocessor
Interfacing”
9020
9030
It is useful to note that in systems where the A/D converter is
1 of 8 or fewer I/O-mapped devices, no address-decoding
circuitry is necessary. Each of the 8 address bits (A0 to A7)
can be directly used as CS inputs, one for each I/O device.
AN030 “The ICL7104 - A Binary Output A/D
Converter for Microprocessors”
6-17
ADC0802, ADC0803, ADC0804
INT (14)
I/O WR (27) (NOTE)
I/O RD (25) (NOTE)
10K
ADC0802 - ADC0804
+
10µF
1
2
3
4
5
6
7
8
9
CS
V+ 20
5V
RD
CLK R
19
18
17
16
15
14
LSB
DB
DB
DB
DB
DB
WR
DB (13) (NOTE)
0
0
1
2
3
4
CLK IN
INTR
DB (16) (NOTE)
1
DB (11) (NOTE)
2
V
V
(+)
(-)
DB (9) (NOTE)
3
IN
IN
ANALOG
INPUTS
DB (5) (NOTE)
4
AGND
/2
DB 13
5
DB (18) (NOTE)
5
150pF
V
DB 12
6
REF
DB (20) (NOTE)
6
MSB
10 DGND
DB 11
7
DB (7) (NOTE)
7
5V
V+
OUT
B
T
T
T
T
T
T
AD (36)
15
5
4
3
2
1
0
5
4
3
2
1
0
B
B
B
B
B
AD (39)
14
8131
BUS
COMPARATOR
AD (38)
13
AD (37)
12
AD (40)
11
AD (1)
10
NOTE: Pin numbers for 8228 System Controller: Others are 8080A.
FIGURE 21. ADC0802 TO 8080A CPU INTERFACE
6-18
ADC0802, ADC0803, ADC0804
IRQ (4)† [D]††
R/W (34) [6]
10µF
10K
+
ADC0802 - ADC0804
CS
1
V+ 20
A B C
5V (8) 1 2 3
RD
2
3
4
5
6
7
8
9
CLK R
19
18
17
16
15
14
LSB
DB
DB
DB
DB
DB
WR
D
D
D
D
D
D
D
D
(33) [31]
(32) [29]
(31) [K]
(30) [H]
(29) [32]
(28) [30]
(27) [L]
(26) [J]
0
1
2
3
4
0
1
2
3
4
5
6
7
CLK IN
INTR
RD
RD
ANALOG
INPUTS
2
V
V
(+)
(-)
IN
IN
IORQ
WR
ADC0802-
ADC0804
AGND
/2
DB 13
5
V
DB 12
6
REF
150pF
MSB
10 DGND
DB 11
7
WR
3
1
2
3
4
74C32
A
A
A
A
(22) [34]
(23) [N]
(24) [M]
(25) [33]
12
13
14
15
6
1
/
DM8092
2
5
VMA (5) [F]
† Numbers in parentheses refer to MC6800 CPU Pinout.
†† Numbers or letters in brackets refer to standard MC6800 System Common Bus Code.
FIGURE 22. MAPPING THE A/D AS AN
I/O DEVICE FOR USE
FIGURE 23. ADC0802 TO MC6800 CPU INTERFACE
WITH THE Z-80 CPU
18
CB
CB
1
19
2
10K
ADC0802 - ADC0804
MC6820
(MCS6520)
1
2
3
4
5
6
7
8
9
CS
V+ 20
5V
RD
CLK R
PIA
19
18
17
16
15
14
10
11
12
13
14
15
16
17
LSB
DB
DB
DB
DB
DB
PB
WR
0
1
2
3
4
0
1
2
3
4
5
PB
PB
PB
PB
PB
CLK IN
INTR
V
V
(+)
(-)
IN
IN
ANALOG
INPUTS
AGND
/2
DB 13
5
V
DB 12
6
PB
REF
150pF
6
7
MSB
10 DGND
DB 11
7
PB
FIGURE 24. ADC0802 TO MC6820 PIA INTERFACE
6-19
ADC0802, ADC0803, ADC0804
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
(101 mils x 93 mils) x 525µm x 25µm
Type: Nitride over Silox
Nitride Thickness: 8kÅ
Silox Thickness: 7kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
Metallization Mask Layout
ADC0802, ADC0803, ADC0804
AGND
V
(-)
V
(+)
IN
INTR
CLK IN
IN
WR
V
/2
REF
RD
CS
DGND
DB
7 (MSB)
DB
DB
6
5
V+ OR V
V+ OR V
REF
REF
CLK R
DB
DB
DB
DB
DB
0
4
3
2
1
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6-20
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