ADC0804S030 [NXP]
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz; 单8位的ADC，高达30 MHz ， 40 MHz或50 MHz的
| 型号： | ADC0804S030 |
| 厂家： | 
NXP |
| 描述： | Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz |
| 文件： | 总19页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC0804S030/040/050
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Rev. 02 — 14 August 2008
Product data sheet
1. General description
The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. It converts the analog
input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal can also be used.
The device requires an external source to drive its reference ladder. If the application
requires that the reference is driven via internal sources, NXP recommends you use one
of the ADC1003S030/040/050 family.
2. Features
I 8-bit resolution
I Sampling rate up to 50 MHz
I DC sampling allowed
I One clock cycle conversion only
I High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits
at 4.43 MHz full-scale input at fclk = 40 MHz)
I No missing codes guaranteed
I In-Range (IR) CMOS output
I TTL and CMOS levels compatible digital inputs
I 3 V to 5 V CMOS digital outputs
I Low-level AC clock input signal allowed
I External reference voltage regulator
I Power dissipation only 175 mW (typical)
I Low analog input capacitance, no buffer amplifier required
I No sample-and-hold circuit required
3. Applications
I Video data digitizing
I Radar
I Transient signal analysis
I Σ∆ modulators
I Medical imaging
I Barcode scanner
I Global Positioning System (GPS) receiver
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
I Cellular base stations
4. Quick reference data
Table 1.
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C;
typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and
amb = 25 °C; unless otherwise specified.
Quick reference data
V
T
Symbol
Parameter
Conditions
Min
4.75
4.75
3.0
-
Typ
5.0
5.0
3.3
18
Max
5.25
5.25
5.25
24
Unit
V
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
V
V
mA
mA
mA
ICCD
-
16
21
ICCO
fclk = 40 MHz;
ramp input
-
1
2
INL
integral non-linearity
fclk = 40 MHz
ramp input
-
-
±0.2
±0.5
LSB
DNL
differential non-linearity fclk = 40 MHz
ramp input
±0.12 ±0.22 LSB
fclk(max)
maximum clock
frequency
ADC0804S030TS
30
40
50
-
-
-
MHz
MHz
MHz
mW
ADC0804S040TS
ADC0804S050TS
-
-
-
-
Ptot
total power dissipation fclk = 40 MHz;
ramp input
175
247
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Sampling
frequency
(MHz)
Description
Version
ADC0804S030TS
ADC0804S040TS
ADC0804S050TS
SSOP28
SSOP28
SSOP28
plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 30
SOT341-1 40
SOT341-1 50
plastic shrink small outline package; 28 leads;
body width 5.3 mm
plastic shrink small outline package; 28 leads;
body width 5.3 mm
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
2 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
6. Block diagram
V
3
V
CCD2
CCA
CLK
1
OE
10
11
2
CLOCK DRIVER
TC
RT
9
25 D7
24 D6
23 D5
22 D4
21 D3
20 D2
19 D1
18 D0
MSB
R
lad
VI
8
7
ANALOG - TO - DIGITAL
CONVERTER
CMOS
OUTPUTS
analog
voltage input
LATCHES
data outputs
RM
LSB
CCO
13
RB
6
V
IR
output
26
28
ADC0804S030
IN-RANGE LATCH
CMOS OUTPUT
V
CCD1
4
12
14
27
AGND
DGND2
OGND
DGND1
014aaa550
analog ground
digital ground
output ground
digital ground
Fig 1. Block diagram
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
3 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
7. Pinning information
7.1 Pinning
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
TC
V
CCD1
DGND1
IR
3
V
CCA
4
AGND
D7
5
n.c.
RB
RM
VI
D6
6
D5
7
D4
ADC0804S
030TS
8
D3
9
RT
OE
D2
10
11
12
13
14
D1
V
D0
CCD2
DGND2
n.c.
n.c.
n.c.
V
CCO
OGND
014aaa551
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Symbol
CLK
TC
Pin description
Pin
1
Description
clock input
2
two’s complement input (active LOW)
analog supply voltage (5 V)
analog ground
VCCA
AGND
n.c.
3
4
5
not connected
RB
6
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
RM
7
VI
8
RT
9
reference voltage TOP input
output enable input (CMOS level input, active LOW)
digital supply voltage 2 (5 V)
digital ground 2
OE
10
11
12
13
14
15
16
17
18
19
VCCD2
DGND2
VCCO
OGND
n.c.
supply voltage for output stages (3 V to 5 V)
output ground
not connected
n.c.
not connected
n.c.
not connected
D0
data output; bit 0 (Least Significant Bit (LSB))
data output; bit 1
D1
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
4 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 3.
Pin description …continued
Symbol
D2
Pin
20
21
22
23
24
25
26
27
28
Description
data output; bit 2
D3
data output; bit 3
D4
data output; bit 4
D5
data output; bit 5
D6
data output; bit 6
D7
data output; bit 7 (Most Significant Bit (MSB))
in-range data output
digital ground 1
IR
DGND1
VCCD1
digital supply voltage 1 (5 V)
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCCA
Parameter
Conditions
Min
−0.3
−0.3
−0.3
−1.0
−1.0
−1.0
−0.3
-
Max
+7.0
+7.0
+7.0
+1.0
+4.0
+4.0
+7.0
VCCD
Unit
V
[1]
[1]
[1]
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
VCCD
V
VCCO
V
∆VCC
VCCA − VCCD
VCCD − VCCO
VCCA − VCCO
V
V
V
VI
input voltage
referenced to AGND
V
Vi(clk)(p-p)
peak-to-peak clock input referenced to DGND
voltage
V
IO
output current
-
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−40
-
+150
+85
150
[1] The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that
the supply voltage differences ∆VCC are respected.
9. Thermal characteristics
Table 5.
Thermal characteristics
Parameter
Symbol
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction in free air
to ambient
110
K/W
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
5 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
10. Characteristics
Table 6.
Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
V
CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
CCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VCCA
analog supply voltage
digital supply voltage
output supply voltage
4.75
5.0
5.0
3.3
-
5.25
5.25
5.25
+0.20
+2.25
+2.25
24
V
VCCD
4.75
V
VCCO
3.0
V
∆VCC
supply voltage
difference
V
V
V
CCA − VCCD
CCA − VCCO
CCD − VCCO
−0.20
V
−0.20
-
V
−0.20
-
V
ICCA
ICCD
ICCO
Ptot
analog supply current
digital supply current
output supply current
-
-
-
-
18
16
1
mA
mA
mA
mW
21
fclk = 40 MHz; ramp input
2
total power dissipation fclk = 40 MHz; ramp input
175
247
Inputs
Clock input CLK (referenced to DGND)[1]
VIL
VIH
LOW-level input voltage
0
2
-
-
0.8
V
V
HIGH-level input
voltage
VCCD
IIL
IIH
Zi
LOW-level input current Vclk = 0.8 V
HIGH-level input current Vclk = 2 V
−1
-
-
+1
10
-
µA
µA
kΩ
pF
2
2
2
input impedance
input capacitance
fclk = 40 MHz
-
Ci
-
-
OE and TC (referenced to DGND); see Table 8
VIL
VIH
LOW-level input voltage
0
2
-
-
0.8
V
V
HIGH-level input
voltage
VCCD
IIL
LOW-level input current VIL = 0.8 V
HIGH-level input current VIH = 2.0 V
−1
-
-
-
µA
µA
IIH
-
1
VI (analog input voltage referenced to AGND)
IIL
IIH
Zi
LOW-level input current VI = VRB = 1.3 V
HIGH-level input current VI = VRT = 3.67 V
-
-
-
-
0
-
-
-
-
µA
µA
kΩ
pF
35
8
input impedance
input capacitance
fi = 4.43 MHz
Ci
5
Reference voltages for the resistor ladder; see Table 7
VRB
VRT
voltage on pin RB
voltage on pin RT
1.2
3.2
1.3
2.45
V
V
3.67
VCCA − 0.8
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
6 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6.
Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
V
CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
CCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vref(dif)
differential reference
voltage
V
RT − VRB
2.0
2.37
3.0
V
Iref
reference current
ladder resistance
VRT − VRB = 2.37 V
-
-
-
9.7
-
-
-
mA
Ω
Rlad
245
456
TCRlad
ladder resistor
mΩ/K
temperature coefficient
[2]
Voffset
offset voltage
BOTTOM;
RT − VRB = 2.37 V
-
175
-
mV
V
[2]
[3]
TOP; VRT − VRB = 2.37 V
-
175
-
mV
V
Vi(a)(p-p)
peak-to-peak analog
input voltage
1.7
2.02
2.55
Digital outputs D7 to D0 and IR (referenced to OGND)
VOL
VOH
Io
LOW-level output
voltage
IOL = 1 mA
0
-
-
-
0.5
V
HIGH-level output
voltage
IOH = − 1 mA
V
CCO − 0.5
VCCO
+20
V
output current
in 3-state mode;
−20
µA
0.5 V < VO < VCCO
Switching characteristics; Clock input CLK; see Figure 4[1]
fclk(max)
maximum clock
frequency
ADC0804S030TS
ADC0804S040TS
ADC0804S050TS
30
40
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
50
tw(clk)H
tw(clk)L
HIGH clock pulse width full effective bandwidth
LOW clock pulse width full effective bandwidth
8.5
5.5
ns
Analog signal processing
Linearity
INL
integral non-linearity
fclk = 40 MHz; ramp input
-
-
-
±0.2
±0.5
±0.22
-
LSB
LSB
LSB
DNL
Eoffset
differential non-linearity fclk = 40 MHz; ramp input
±0.12
±0.25
offset error
middle code; VRB = 1.3 V;
RT = 3.67 V
V
[4]
[5]
EG
gain error
from device to device;
RB = 1.3 V; VRT = 3.67 V
-
±0.1
-
%
V
Bandwidth (fclk = 40 MHz)
B
bandwidth
full-scale sine wave
-
-
-
15
-
-
-
MHz
MHz
MHz
75 % full-scale sine wave
20
small signal at mid-scale;
350
VI = ±10 LSB at code 512
[6]
ts(LH)
ts(HL)
LOW to HIGH settling
time
full-scale square wave; see
Figure 6
-
-
1.5
1.5
3.0
3.0
ns
ns
HIGH to LOW settling
time
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
7 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6.
Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
V
CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
CCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Harmonics (fclk = 40 MHz); see Figure 7 and 8
α1H
α2H
α3H
THD
first harmonic level
second harmonic level fi = 4.43 MHz
third harmonic level fi = 4.43 MHz
total harmonic distortion fi = 4.43 MHz
fi = 4.43 MHz
-
-
-
-
-
0
dB
dB
dB
dB
−75
−72
−65
−65
−65
-
Signal-to-noise ratio; see Figure 7 and 8[7]
S/N
signal-to-noise ratio
full scale;
46
49
-
dB
without harmonics;
fclk = 40 MHz; fi = 4.43 MHz
Effective number of bits[7]
ENOB
effective number of bits ADC0804S030TS (fclk = 30 MHz)
fi = 4.43 MHz
-
-
7.8
7.8
-
-
bits
bits
fi = 7.5 MHz
ADC0804S040TS (fclk = 40 MHz)
fi = 4.43 MHz
-
-
-
-
7.8
7.8
7.8
7.4
-
-
-
-
bits
bits
bits
bits
fi = 7.5 MHz
fi = 10 MHz
fi = 15 MHz
ADC0804S050TS (fclk = 50 MHz)
fi = 4.43 MHz
-
-
-
-
7.8
7.8
7.8
7.3
-
-
-
-
bits
bits
bits
bits
fi = 7.5 MHz
fi = 10 MHz
fi = 15 MHz
Two-tone intermodulation[8]
αIM
intermodulation
suppression
fclk = 40 MHz
-
-
−69
-
-
dB
Bit error rate
BER
bit error rate
fclk = 40 MHz;
10−13
times/
fi = 4.43 MHz; VI = ±16 LSB
at code 512
samples
Differential gain[9]
Gdif
differential gain
fclk = 40 MHz;
-
0.8
-
%
PAL modulated ramp
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
8 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6.
Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
V
CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
CCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Differential phase[9]
ϕdif differential phase
Parameter
Conditions
Min
Typ
Max
Unit
fclk = 40 MHz;
-
0.4
-
deg
PAL modulated ramp
Timing (fclk = 40 MHz; Ci = 15 pF); see Figure 4[10]
td(s)
th(o)
td(o)
sampling delay time
output hold time
-
3
-
ns
ns
ns
ns
pF
4
-
-
-
output delay time
VCCO = 4.75 V
VCCO = 3.15 V
10
12
-
13
15
15
-
CL
load capacitance
-
3-state output delay times; see Figure 5
tdZH
tdZL
tdHZ
tdLZ
float to active HIGH
delay time
-
-
-
-
5.5
12
19
12
8.5
15
24
15
ns
ns
ns
ns
float to active LOW
delay time
active HIGH to float
delay time
active LOW to float
delay time
[1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns.
[2] Analog input voltages producing code 0 up to and including code 255:
a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(VRB) at Tamb = 25 °C.
b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal
to code 255 at Tamb = 25 °C.
[3] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3.
VRT – VRB
a) The current flowing into the resistor ladder is I =
and the full-scale input range at the converter, to cover code 0
----------------------------------------
R
OB + RL + ROT
RL
to 255 is VI = RL × IL
=
× (V + VRB) = 0.852 × (VRT – VRB)
----------------------------------------
RT
ROB + RL + ROT
RL
b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio
----------------------------------------
ROB + RL + ROT
will be kept reasonably constant from device to device. Consequently, the variation of the output codes at a given input voltage
depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are
connected in parallel and fed with the same reference source, the matching between each of them is optimized.
(V1023 – V0) – V
[4] EG
=
i(p – p) × 100
--------------------------------------------------------
Vi(p – p)
[5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 0.5 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
9 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
[7] Effective bits are obtained via a Fast Fourier transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
SIgnal-to-Noise-And-Distortion (SINAD) ratio: SINAD = ENOB × 6.02 + 1.76 dB.
[8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have
the same amplitude and the total amplitude of both signals provides full-scale to the converter.
[9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog
converter.
[10] Output data acquisition: the output data is available after the maximum delay time of td(0). For 50 MHz version NXP recommend the
lowest possible output load.
RT
R
OT
code 255
R
L
R
L
R
L
I
RM
L
R
lad
R
L
code 0
R
OB
RB
014aaa555
Fig 3. Explanation of Table 6 Table note 3
11. Additional information relating to Table 6
Table 7.
Code
Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V,
RT = 3.67 V)
V
Vi(a)(p-p) IR
Binary outputs D7 to D0
Two’s complement
outputs D7 to D0
(V)
Underflow
< 1.475
0
1
1
↓
1
1
0
0000 0000
0000 0000
0000 0001
↓
10 0000 00
10 0000 00
10 0000 01
↓
0
1.475
1
-
↓
-
254
-
1111 1110
1111 1111
1111 1111
01 1111 10
01 1111 11
01 1111 11
255
3.495
> 3.495
Overflow
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
10 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 8.
Mode selection
TC
X
OE
1
D7 to D0
IR
high impedance
high impedance
active
0
0
active; two’s complement
active; binary
1
0
active
sample N
sample N + 1
w(clk)L
sample N + 2
t
t
w(clk)H
V
CCO
CLK
50 %
0 V
sample N + 2
sample N
sample N + 1
VI
t
t
h(o)
d(s)
V
CCO
DATA
D0 to D7
DATA
N − 2
DATA
N − 1
DATA
N + 1
DATA
N
50 %
0 V
t
d(o)
014aaa556
Fig 4. Timing diagram
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
11 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
V
CCD
OE
50 %
t
t
dZH
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
S1
TEST
V
CCD
t
V
V
dLZ
CCD
CCD
3.3 kΩ
t
dZL
ADC0804S030
S1
15 pF
t
DGND
DGND
dHZ
OE
t
dZH
014aaa552
frequency on pin OE = 100 kHz
Fig 5. Timing diagram and test conditions of 3-state output delay time
t
t
s(HL)
s(LH)
code 255
VI
50 %
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
0.5 ns
0.5 ns
014aaa400
Fig 6. Analog input settling time diagram
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
12 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
014aaa328
+20
amplitude
(dB)
−20
−60
−100
−140
0
5.00
10.0
15.0
20.0
f (MHz)
Effective bits: 7.84; THD = −71.8 dB.
Harmonic levels (dB): 2nd = −83.19; 3rd = −78.09; 4th = −78.72; 5th = −78.33; 6th = −77.55.
Fig 7. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz)
014aaa329
+20
amplitude
(dB)
−20
−60
−100
−140
0
5.0
10.0
15.0
20.0
25.0
f (MHz)
Effective bits: 7.79; THD = −62.96 dB.
Harmonic levels (dB): 2nd = −71.38; 3rd = −71.54; 4th = −74.14; 5th = −65.15; 6th = −77.16.
Fig 8. Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz)
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
13 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
V
CCA
V
CCO
D7 to D0
IR
VI
OGND
AGND
014aaa557
014aaa526
Fig 9. CMOS data and in-range outputs
Fig 10. Analog inputs
V
CCA
RT
V
CCO
R
R
R
L
L
L
OE
TC
RM
RB
R
L
OGND
AGND
014aaa553
014aaa331
Fig 11. OE and TC input
Fig 12. RB, RM and RT
V
CCD
1.5 V
CLK
DGND
014aaa399
Fig 13. CLK input
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
14 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
12. Application information
V
CLK
TC
CCD1
1
28
(3)
100 nF
DGND1
IR
2
27
26
25
24
V
CCA
AGND
n.c.
3
(3)
100 nF
D7
4
D6
5
(1)
RB
D5
6
23
(1)
RM
D4
100 nF
7
22
21
100 nF
ADC0804S030
VI
D3
8
AGND
(1)
AGND
RT
D2
9
20
19
18
17
16
15
OE
D1
100 nF
10
11
12
13
14
V
D0
CCD2
AGND
(3)
100 nF
100 nF
DGND2
n.c.
n.c.
V
CCO
(3)
(2)
n.c.
OGND
014aaa554
The analog and digital supplies should be separated and well decoupled
A user manual is available that describes the demonstration board that uses the version ADC0804S030/040/050/ family with an
application environment.
(1) RB, RM and RT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in order to prevent noise influence.
(3) Decoupling capacitor for supplies; must be placed close to the device.
Fig 14. Application diagram
12.1 Alternative parts
The following alternative parts are also available:
Table 9.
Alternative parts
Type number
ADC1004S030
ADC1004S040
ADC1004S050
ADC1003S030
Description
Sampling frequency
30 MHz
[1]
[1]
[1]
[1]
Single 10 bits ADC
Single 10 bits ADC
Single 10 bits ADC
Single 10 bits ADC
40 MHz
50 MHz
30 MHz, with internal reference
regulator
[1]
[1]
[1]
ADC1003S040
ADC1003S050
Single 10 bits ADC
Single 10 bits ADC
Single 10 bits ADC
40 MHz, with internal reference
regulator
50 MHz, with internal reference
regulator
ADC1005S060
60 MHz
[1] Pin to pin compatible
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
15 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
13. Package outline
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
D
E
A
X
v
c
H
M
A
y
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.1
0.7
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT341-1
MO-150
Fig 15. SOT341-1 (SSOP28)
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
16 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
14. Revision history
Table 10. Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
ADC0804S030_040_050_2 20080814
Product data sheet
-
ADC0804S030_040_050_1
Modifications:
• Paragraph added to Section 1.
• Corrections to descriptions of rows RB and RM in Table 3.
• Corrections to Table 6.
• Corrections to Figure 9, 10 and 12.
ADC0804S030_040_050_1 20080616
Product data sheet
-
-
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
17 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
18 of 19
ADC0804S030/040/050
NXP Semiconductors
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
17. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional information relating to Table 6 . . . 10
Application information. . . . . . . . . . . . . . . . . . 15
Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
12.1
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 August 2008
Document identifier: ADC0804S030_040_050_2
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