PBL38640/2SH [INTEL]
SLIC, Bipolar, PDSO24, PLASTIC, SSOP-24;
| 型号： | PBL38640/2SH |
| 厂家： | 
INTEL |
| 描述： | SLIC, Bipolar, PDSO24, PLASTIC, SSOP-24 电信 光电二极管 电信集成电路 |
| 文件： | 总51页 (文件大小：2007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 2.0, Apr. 2005
FlexiSLICTM
Subscriber Line Interface Circuit
PBL 38640/2, Version 2
Wireline Communications
N e v e r s t o p t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, FlexiSLIC™, VDSLite™ are trademarks of Infineon
Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation, Linux®
of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
The information in this document is subject to change without notice.
Edition 2005-04-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
FlexiSLIC
Revision History:
Previous Version:
2005-04-14
DS1
Rev. 2.0
Page
all
Subjects (major changes since last revision)
Package P-DSO-24-1 changed to P-/PG-DSO-24-8
Package type abbreviation SOIC changed to PDSO
Package P-LCC-28-2 changed to P-/PG-LCC-28-3
Package P-SSOP-24-1 changed to P-/PG-SSOP-24-1
all
all
all
Page 17
Table 5: Thermal resistance for 24-pin PDSO changed from 80.2 °C/W to
50.3 °C/W
Page 30
Page 31
Page 36
Figure 9: SLIC/codec circuitry changed
Table 6: values of RR, RT, RRX, RTX, RB changed, RFB removed
Figure 11 changed
FlexiSLIC
PBL 38640/2
Table of Contents
Page
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
1.2
1.3
1.4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Characterictics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Design Supporting Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1
4.2
5
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Two-Wire Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Two-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Four-Wire to Two-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Four-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Longitudinal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitors CTC and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC - DC Separation Capacitor, CHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
High-pass Transmit Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitor CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
6
Battery Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CODEC Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Programmable Overhead Voltage (POV) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Analog Temperature Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
6.2
6.3
7
Loop Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Loop Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ground Key Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ring Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.1
7.2
7.3
8
Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Open Circuit (C3, C2, C1 = 0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ringing (C3, C2, C1 = 0, 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Tip Open State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Active Polarity Reversal State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
9.2
9.3
9.4
9.5
Data Sheet
4
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Table of Contents
Page
10
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Overvoltage Protection - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1
10.2
11
12
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
24-pin SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
24-pin PDSO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
28-pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.1
13.2
13.3
Data Sheet
5
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
List of Figures
Page
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view) . 11
Overhead Level, VTRO, Two-Wire Port. . . . . . . . . . . . . . . . . . . . . . . . . 27
Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance. . . . . 28
Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE. . . . . 28
Overhead Level, VTXO, Four-Wire Transmit Port . . . . . . . . . . . . . . . . . 28
Frequency Response, Insertion Loss, Gain Tracking . . . . . . . . . . . . . 29
TIPX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application Example of PBL 38640/2 with SICOFI®4 Codec . . . . . . . . 30
Simplified AC Model of PBL 38640/2. . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Codec Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Battery Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programmable Overhead Voltage (POV). RL= 600 Ω or Infinite . . . . . 43
P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package). . . . . . . . . 48
P-/PG-DSO-24-8 (Plastic Dual Small Outline Package) . . . . . . . . . . . 49
P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package) . . . . . . . . . . 50
Data Sheet
6
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
List of Tables
Page
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SLIC Operating States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Feeding Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Battery Overhead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal Bias Current of RSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Sheet
7
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Subscriber Line Interface Circuit
Version 2
1
Overview
1.1
Features
• 24-pin SSOP package
• High and low battery with automatic switching
• 65 mW on-hook power dissipation in active state
• On-hook transmission
P-/PG-SSOP-24-1
• Long loop battery feed tracks Vbat for maximum line
voltage
• Selectable transmit gain (1x or 0.5 x)
• No power-up sequence
• 43 V open loop voltage @ -48 V battery feed
• Close tolerance current feeding
• Constant loop voltage for line leakage < 5 mA
(RLeak ~ > 10 kΩ @ -48 V)
P-/PG-DSO-24-8
• Full longitudinal current capability during
on-hook state
• Longitudinal balance > 60 dB
• Analog overtemperature protection permits transmis-
sion while the protection circuits is active
• Line voltage measurement
• Polarity reversal
• Ground key detector
• Tip open state with ring ground detector
• Programmable signal headroom
• -40 oC to +85 oC ambient temperature range
P-/PG-LCC-28-3
Type
Package
PBL 38640/2 SH
PBL 38640/2 SO
PBL 38640/2 QN
P-/PG-SSOP-24-1
P-/PG-DSO-24-8
P-/PG-LCC-28-3
Data Sheet
8
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Overview
1.2
Typical Applications
• Basic functionality Central Office Line card
• Digital Loop Carriers (DLC)
1.3
Description
The PBL 38640/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX, Terminal adapters and other telecommunications equipment. The
PBL 38640/2 SLIC has been optimized for low total line interface cost and for a high
degree of flexibility in different applications.
The PBL 38640/2 SLIC emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with short loop current limiting adjustable to maximum 45 mA. In the
current limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30 kΩ.
A second lower battery voltage may be connected to the device to reduce short loop
power dissipation. The SLIC automatically switches between the two battery supply
voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring-trip detection functions. The
PBL 38640/2 is compatible with both loop and ground start signalling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with
a programmable CODEC/filter, for example SiCoFi PEB 2466. The programmable two-
wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 38640/2 SLIC package options are 24-pin SSOP, 24-pin PDSO or 28-pin
PLCC.
Data Sheet
9
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Overview
1.4
Block Diagram
VCC
AGND
DT
DR
Ring Trip
Comparator
Ring Relay
Driver
RRLY
C1
C2
C3
Input
Decoder
and
Ground Key
Detector
Control
TIPX
HP
DET
Line Feed
Controller
and
POV
PSG
Longitudinal
Signal
Two-wire
Interface
PLC
Suppression
LP
RINGX
Off - Hook
Detector
PLD
REF
RSN
VF signal
Transmission
VTX
BGND
VBAT
PTG
VBAT2
bl_sch_40
Figure 1
Block Diagram
Data Sheet
10
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Pin Configuration
2
Pin Configuration
PTG 1
RRLY 2
HP 3
24 VTX
23 AGND
22 RSN
21 REF
20 PLC
4
3
2
1 28 27 26
RINGX 4
BGND 5
TIPX 6
RINGX
BGND
TIPX
5
6
7
8
9
25 NC
24 REF
PLC
23
22
24-pin PDSO 19 POV
and
28-pin PLCC
VBAT
VBAT2
POV
24- pin SSOP
VBAT 7
18 PLD
17 VCC
16 DET
15 C1
21 PLD
20 VCC
19 NC
VBAT2
8
PSG 10
NC 11
PSG 9
LP 10
DT 11
DR 12
12 13 14 15 16 17 18
14 C2
13 C3
pinout_40
Figure 2
Table 1
Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view)
Pin Definition and Functions
PDSO
SSOP
Pin No.
PLCC
Name
Pin
Type
Function
Pin No.
1
1
PTG
–
Programmable transmit gain. Left open
transmit gain = 0.0 dB, connected to AGND
transmit gain = -6.02 dB.
2
3
2
3
RRLY
HP
O
–
Ring relay driver output. The relay coil may
be connected to maximum +14 V.
Connection for high pass filter capacitor, CHP.
Other end of CHP connects to TIPX.
Data Sheet
11
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Name
Pin
Type
Function
Pin No.
4
5
RINGX
–
The RINGX pin connects to the ring lead of
the two-wire interface via over voltage
protection components and ring relay (and
optional test relay).
5
6
6
7
BGND
TIPX
–
–
Battery ground, should be tied together with
AGND.
The TIPX pin connects to the tip lead of the
two-wire interface via over voltage protection
components and ring relay (and optional test
relay).
7
8
9
8
VBAT
VBAT2
PSG
–
–
–
Battery supply voltage. Negative with respect
to GND.
An optional second (2) Battery Voltage
connects to this pin via an external diode.
9
10
Programmable saturation guard. The
resistive part of the DC feed characteristics is
programmed by a resistor connected from
this pin to VBAT
.
10
11
12
13
LP
DT
–
I
Connection for low pass filter capacitor, CLP.
Other end of CLP connects to VBAT
.
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
12
14
DR
I
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
13
14
15
15
16
17
C3
C2
C1
I
I
I
C1, C2, C3 are digital inputs (positive logic,
internal pull-up), which control the SLIC
operating states. Refer to Table 2 for details.
Data Sheet
12
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Name
Pin
Type
Function
Pin No.
16
18
DET
O
Detector output. Active low when indicating
loop or ring-trip detection, active high when
indicating ground key detection.
17
18
20
21
VCC
PLD
–
–
+5 V power supply.
Programmable loop detector threshold. The
loop detection threshold os programmed by a
resistor connected from this pin to AGND.
19
22
POV
PLC
–
Programmable overhead voltage. If pin is left
open: The overhead voltage is internally set
to min 2.7 V in off- hook and min 1.1 V in on-
hook. If a resistor is connected between this
pin and AGND: The overhead voltage can be
set to higher values.
Programmable line current, the constant
current part of the DC feed characteristic is
programmed by a resistor connected from
this pin to AGND.
20
23
–
21
22
24
26
REF
RSN
–
–
A reference, 49.9 kΩ, resistor should be
connected from this pin to AGND.
Receive summing node. 200 times the AC
current flowing into this pin equals the
metallic (transversal) AC current flowing from
RINGX to TIPX. Programming networks for
two-wire impedance and receive gain
connect to the receive node. A resistor should
be connected from this pin to AGND.
23
27
AGND
–
Analog ground, should be tied together with
BGND.
Data Sheet
13
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Name
Pin
Type
Function
Pin No.
24
28
VTX
O
Transmit vf output. The AC voltage difference
between TIPX and RINGX, the AC metallic
voltage, is reproduced as an unbalanced
GND referenced signal at VTX with a gain of
one (or one half, see pin PTG). The two-wire
impedance programming network connects
between VTX and RSN.
-
4, 11,19, NC
25
–
Not Connected.
Table 2
State
SLIC Operating States
C3
C2
C1
SLIC Operating Active Detector
State
(DET Response)
0
1
2
0
0
0
Open circuit
No active detector
(DET is set high)
0
0
1
Ringing
Active
Ring-trip detector
(DET active low)
0
1
0
Loop detector
(DET active low)
3
4
0
1
1
0
1
0
Active
Tip open
Line voltage measurement1)
Loop detector
(DET active low)
5
6
7
1
1
1
0
1
1
1
0
1
Active
Ground key detector
(DET active high)
Loop detector
(DET active low)
Ground key detector
(DET active high)
Active reverse
Active reverse
1) Previous state must be active - loop or ground key detector.
Data Sheet
14
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
3
Electrical Characteristics
Table 3
Absolute Maximum Ratings
Parameter
Symbol
Min.
Values
Typ.
Unit Note/Test
Condition
Max.
Temperature, Humidity
Storage temperature range TStg
-55
-40
–
–
150
110
°C
°C
–
–
Operating temperature
TAmb
range
Operating junction
temperature range1)
TJ
-40
–
140
°C
–
Power Supply (-40 °C ≤ TAmb ≤ +85 °C)
VCC with respect to A/BGND VCC
-0.4
VBAT
–
–
6.5
0.4
V
V
–
–
V
BAT2 with respect to
A/BGND
BAT with respect to
A/BGND, continuous
VBAT2
VBAT
VBAT
V
-75
-80
–
–
0.4
0.4
V
V
–
–
V
BAT with respect to
A/BGND, 10 ms
Power Dissipation
Continuous power
dissipation
PD
–
–
1.5
0.3
W
V
TAmb
≤
+85 °C
Ground
Voltage between AGND and VG
-0.3
–
–
–
–
BGND
Relay Driver
Ring relay supply voltage
–
BGND V
+14
–
Ring Trip Comparator
Input voltage
Input current
VDT, VDR VBAT
IDT, IDR -5
–
–
AGND V
–
–
5
mA
Digital Inputs, Outputs (C1, C2, C3, DET)
Input voltage
Output voltage
VID
VOD
-0.4
-0.4
–
–
VCC
VCC
V
V
–
–
Data Sheet
15
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 3
Absolute Maximum Ratings (cont’d)
Symbol Values
Typ.
TIPX and RINGX Terminals (-40 °C ≤ TAmb ≤ +85 °C, VBAT = -50 V)
Parameter
Unit Note/Test
Condition
Min.
-100
Max.
TIPX or RINGX current
ITIPX
,
–
100
mA
–
–
IRINGX
TIPX or RINGX voltage,
continuous (referenced to
AGND)2)
TIPX or RINGX2)
VTA, VRA -80
–
2
V
VTA, VRA VBAT
–
5
V
pulse <
- 10
10 ms,
tRep > 10 s
TIPX or RINGX2)
TIP or RING2)3)
VTA, VRA VBAT
–
–
10
15
V
V
pulse < 1 µs,
tRep > 10 s
- 25
VTA, VRA VBAT
pulse <
- 35
250 ns,
tRep > 10 s
1) The circuit includes thermal protection. Operation above max. junction temperature may degrade device
reliability.
2) With the diodes DVB and DVB2 included, see Figure 9.
3) RF1 and RF2 > 20 Ω is also required. Pulse is supplied to RING and TIP outside RF1 and RF2.
Attention: Stresses above those values listed here may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these
values may cause irreversible damage to the integrated circuit.
Table 4
Operating Range
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note/Test
Condition
Ambient temperature
VCC with respect to AGND
TAmb
VCC
VBAT
-40
4.75 –
-58
–
85
5.25 V
-8
°C
–
–
–
VBAT with respect to AGND
–
V
AGND with respect to BGND VG
-100 –
100 mV –
Data Sheet
16
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
3.1
Characterictics
The specification is made with following setup: -40 °C ≤ TAmb ≤ +85 °C, PTG = open (see
pin description), VCC = +5 V ± 5%, VBAT = -58 V to -40 V, VBAT2 = -32 V, RLC = 32.4 kΩ,
IL = 27 mA, RL = 600 Ω, RF1 = RF2 = 0, RREF = 49.9 kΩ, CHP = 47 nF, CLP = 0.15 µF,
RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ, ROV = infinite.
Current definition: current is positive if flowing into a pin unless stated otherwise.
Table 5
Characteristics
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Two-Wire Port
Overhead level1),
VTRO
2.7
1.1
–
–
–
–
VPeak
VPeak
–
18 mA ≤ ILDC
On-Hook,
Active, 1% THD
ROV = infinite
I
LDC ≤ 5 mA
see Figure 3
Input impedance2)
ZTRX
–
ZT/
–
Ω
–
200
Longitudinal impedance ZLOT
ZLOR
Longitudinal current limit ILOT
ILOR
,
–
20
35
–
Ω/wire 0 < f < 100 Hz
,
28
–
mArms/ Active
wire
Data Sheet
17
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Longitudinal to metallic BLM
balance (IEEE standard
455-1985), ZTRX = 736 Ω
63
60
60
55
59
55
55
55
66
66
66
66
66
66
66
66
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
Normal polarity
–
dB
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
–
–
dB
dB
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
0.2 kHz ≤ f ≤
1.0 kHz
Reverse polarity
TAMB 0-70 oC
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Data Sheet
18
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Longitudinal to metallic BLME
balance
63
60
60
55
59
55
55
55
66
66
66
66
66
66
66
66
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
BLME = 20 × log|ELO/VTR|,
TAMB 0-70 oC
see Figure 4
–
dB
1.0 kHz < f <
3.4 kHz
Normal polarity
Reverse polarity
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
–
–
dB
dB
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Data Sheet
19
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Longitudinal to four-wire BLFE
balance
63
60
60
55
59
55
55
55
40
66
66
66
66
66
66
66
66
50
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
BLFE = 20 × log|ELO/VTX|,
TAMB 0-70 oC
see Figure 4
–
dB
1.0 kHz < f <
3.4 kHz
Normal polarity
Reverse polarity
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
–
–
dB
dB
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
–
dB
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Metallic to longitudinal
balance
BMLE
0.2 kHz < f <
3.4 kHz
BMLE = 20 × log|VTR/VLO|,
ERX = 0 V, see Figure 5
Four-wire to longitudinal BFLE
balance
BFLE = 20 × log|ERX/VLO|,
see Figure 5
40
50
–
dB
0.2 kHz < f <
3.4 kHz
Data Sheet
20
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Two-wire return loss3)
r
30
35
–
–
–
dB
dB
0.2 kHz < f <
1.0 kHz
1.0 kHz < f <
3.4 kHz
Active, IL < 5 mA
Active, IL < 5 mA
Z
TRX + ZL
------------------------
r = 20 × log
Z
TRX – ZL
20
22
TIPX idle voltage
RINGX idle voltage
VTI
VRI
–
–
-1.3
V
V
VBAT+ –
3.0
–
–
VBAT+ –
V
V
Tip open,
IL < 5 mA
Active, IL < 5 mA
3.0
Open loop voltage
VTR
VBAT+ –
4.3
Four-Wire Transmit Port (VTX)
Overhead level4),
Load imp. > 20 kΩ
1% THD
VTXO
2.7
1.1
–
–
–
–
VPeak
VPeak
IL > 18 mA
On-Hook, IL ≤
5 mA
see Figure 6
Output offset voltage
Output impedance
∆VTX
ZTX
-100
–
–
15
100
50
mV
Ω
–
0.2 kHz < f <
3.4 kHz
Four-Wire Receive Port (receive summing node = RSN)
RSN DC voltage
RSN impedance
VRSNdc
1.15 1.25 1.35
V
Ω
IRSN = -55 µA
0.2 kHz < f <
3.4 kHz
–
8
20
RSN current (IRSN ) to
metallic loop current (IL)
gain
αRSN
–
200
–
ratio
0.3 kHz < f <
3.4 kHz
Frequency Response
Two-wire to four-wire,
relative to 0 dBm,
1.0 kHz, ERX = 0 V, see
Figure 7
g2-4
-0.20 –
-1.0
0.10 dB
0.1 dB
0.3 kHz < f <
3.4 kHz
–
f = 8 kHz, 12 kHz,
16 kHz
Data Sheet
21
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Four-wire to two-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V, see
Figure 7
g4-2
-0.2
–
0.1
dB
0.3 kHz < f <
3.4 kHz
-1.0
-2.0
-0.2
–
–
–
0
0
0.1
dB
dB
dB
f = 8 kHz, 12 kHz
f = 16 kHz
0.3 kHz < f <
3.4 kHz
Four-wire to four-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V, see
Figure 7
g4-4
Insertion Loss
Two-wire to four-wire5), G2-4
G2-4 = 20 × log|VTX/VTR|
0 dBm, 1.0 kHz
-0.2
–
0.2
dB
PTG = Open
see Figure 7
-6.22 -6.02 -5.82 dB
PTG = AGND
ERX = 0 V
Four-wire to two-wire6), G4-2
G4-2 = 20 × log|VTR/VRX|,
EL = 0 V, see Figure 7
-0.2
–
0.2
dB
0 dBm, 1.0 kHz
Gain Tracking
Two-wire to four-wire7),
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1
-0.2
-0.1
-0.2
–
–
–
–
0.1
0.2
0.1
0.2
dB
dB
dB
dB
-40 dBm to
+3 dBm
-55 dBm to -
40 dBm
-40 dBm to
+3 dBm
-55 dBm to -
40 dBm
Four-wire to two-wire,
Ref. -10 dBm, 1.0 kHz,
see Figure 7
Noise
Idle channel noise at
two-wire port8) (TIPX-
RINGX) or four-wire
(VTX) output
–
–
–
–
12
dBrnC C-message
weighting
dBmp Psophometrical
weighting
-78
Data Sheet
22
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Harmonic Distortion
Two-wire to four-wire,
–
–
-67
-67
-50
-50
dB
dB
0 dBm
0.3 kHz < f <
3.4 kHz
see Figure 7
Four-wire to two-wire
Battery Feed Characteristics
Loop current in the
current limited region,
reference A, B & C
see Figure 13
IL
0.92 × IL
IL
1.08 × mA
IL
18 mA ≤ IL ≤ 45 mA
Tip open state TIPX
ILeak
–
–
-100 µA
S = closed;
R = 7 kΩ9)
current
see Figure 8
Tip open state RINGX
ILRTo
–
–
–
IL
–
–
–
mA
mA
V
RLRTo = 0 Ω,
VBat = -48 V
RLRTo = 2.5 kΩ,
VBat = -48 V
current
see Figure 8
17
Tip open state RINGX
voltage
see Figure 8
VRTo
VBat
+6
ILRTo < 23 mA
Tip voltage (ground
–
-4
-2.2
-2.4
–
V
Active state,
Tip lead open (S
open),
start)
see Figure 8
Ring lead to
ground through
150 Ω
Tip voltage (ground
start)
see Figure 8
–
-6
–
V
Active state,
Tip lead to -48 V
through 7 kΩ (S
closed),
Ring lead to
ground through
150 Ω
Open circuit loop current ILOC
-100
0
100
µA
RL = 0 Ω
Data Sheet
23
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Loop Detector
Programmable
threshold,
ILTh
0.85 × ILTh
ILTh
1.15 × mA
ILTh
ILTh = 500/RLD
RLD in kΩ,
7 mA ≤ ILTh
Tip open state
–
0.85 × ILTh
ILTh
1.15 × mA
ILTh
ILTh = 500/RLD
Ground Key Detector
Ground key detector
threshold
–
10
16
22
mA
(ILTIPX and ILRINGX
current difference
to trigger ground
key detector)
Line Voltage Measurement
Pulse width10)
Ring Trip Comparator
tLVM
–
5.5
0
–
µs/V
Offset voltage
∆VDTDR -20
20
mV
Source
resistance,
RS = 0 Ω
Input bias current
Input common mode
range
IB
-200 -20
200
-1
nA
V
IB=(IDT +IDR)/2
VDT, VDR VBAT
–
+1
Ring Relay Driver
Saturation voltage
Off state leakage current ILK
VOL
–
–
0.2
–
0.5
10
V
µA
IOL = 50 mA
VOH = 12 V
Digital Inputs (C1, C2, C3)
Input low voltage
Input high voltage
Input low current
Input high current
VIL
VIH
IIL
0
2.5
–
–
–
–
–
0.5
VCC
-50
50
V
V
µA
µA
–
–
VIL = 0.5 V
VIH = 2.5 V
IIH
–
Data Sheet
24
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Detector Output (DET)
Output low voltage
Internal pull-up resistor
to VCC
VOL
–
–
–
15
0.7
–
V
kΩ
IOL = 0.5 mA
–
Power Dissipation (VBAT -48 V, VBAT2 = -32 V)
Power Dissipation
P1
–
10
15
85
mW
mW
Open circuit (C1,
C2, C3 = 0)
Active (On-hook)
Long current =
0 mA
Power Dissipation
P2
–
65
Power Dissipation
Power Dissipation
P3
P4
–
–
730
360
–
–
mW
mW
Active (Off-hook)
RL = 300 Ω
Active (Off-hook)
RL = 800 Ω
Power Supply Currents (VBAT = -48 V)
VCC current
VBAT current
VCC current
ICC
IBAT
ICC
–
1.2
2.0
mA
mA
mA
Open circuit (C1,
C2, C3 = 0)
Open circuit (C1,
C2, C3 = 0)
Active, On-hook,
Long current =
0 mA
-0.1
–
-0.05 –
2.8
4.0
VBAT current
IBAT
-1.5
-1.0
–
mA
Active, On-hook,
Long current =
0 mA
Power Supply Rejection Ratios
VCC to 2- or 4-wire port
30
40
36
42
60
45
–
–
–
dB
dB
dB
Active, f = 1 kHz,
Vn = 100 mV
Active, f = 1 kHz,
Vn = 100 mV
Active, f = 1 kHz,
Vn = 100 mV
VBAT2 to 2- or 4-wire port
VBAT to 2- or 4-wire port
Data Sheet
25
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Temperature Guard
Junction threshold
temperature
TJG
–
145
–
°C
–
Thermal Resistance
24-pin SSOP
Rth, jp
Rth, jA
–
–
55
66.9
–
–
°C/W
°C/W
–
P-/PG-SSOP-24-
1,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
24-pin PDSO
28-pin PLCC
Rth, jp
Rth, jA
–
–
43
50.3
–
–
°C/W
°C/W
–
P-/PG-DSO-24-8,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
Rth, jp
Rth, jA
–
–
39
50.4
–
–
°C/W
°C/W
–
P-/PG-LCC-28-3,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
1) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the two-wire port with the signal source at the four-wire receive port.
Data Sheet
26
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
2) The two-wire impedance is programmable by selection of external component values according to:
Z
Z
TRX = ZT/(|G2-4S × αRSN|) where:
TRX = impedance between the TIPX and RINGX terminals
ZT = programming network between the VTX and RSN terminals
G2-4S = transmit gain, nominally = 1 (or 0.5, see pin PTG)
αRSN = receive current gain, nominally 200 (current defined as positive flowing into the receive summing node,
RSN, and when flowing from ring to tip).
3) Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating
impedance programming resistance, for example by dividing RT into two equal halves and connecting a
capacitor from the common point to ground.
4) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the four-wire transmit port, (VTX) with the signal source at the two-wire port. Note that the gain
from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5, see pin PTG).
5) Pin PTG = Open sets transmit gain to nom. 0.0 dB.
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistor RF (see Figure 9) impacts the insertion loss as explained in Chapter 5. The
specified insertion loss is valid for RF = 0.
6) The specified insertion loss tolerance does not include errors caused by external components.
7) The level is specified at the two-wire port.
8) The two-wire idle noise is specified with the port terminated in 600 Ω (RL), and with the four-wire receive port
grounded (ERX = 0; see Figure 7). The four-wire idle noise at VTX is specified with the two-wire port terminated
in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX.
The four-wire receive port is grounded (ERX = 0).
9) If | VBat + 2 V | ≤ | VBExt |, where VBat is the voltage at VBAT, the current ILeak is limited to ~ 5 mA,
10)Previous state must be active - loop or ground key detector.
C
TIPX
VTX
V TRO
ILDC
R L
PBL 38640
RT
E RX
RINGX
RSN
R RX
Fig3_40
Figure 3
Overhead Level, VTRO, Two-Wire Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
Data Sheet
27
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
TIPX
VTX
E LO
C
R LT
R LR
V TR
PBL 38640
RT
V TX
RINGX
RSN
R RX
Fig4_40
Figure 4
Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
TIPX
VTX
C
R LT
R LR
V TR
PBL 38640
R T
E RX
V LO
RINGX
RSN
R RX
Fig5_40
Figure 5
Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
C
TIPX
VTX
RL
I LDC
PBL 38640
RT
V TXO
E L
RINGX
RSN
R RX
Fig6_40
Figure 6
Overhead Level, VTXO, Four-Wire Transmit Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
Data Sheet
28
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Electrical Characteristics
C
TIPX
VTX
RL
V TR
I LDC
PBL 38640
RT
V TX
E RX
E L
RINGX
RSN
R RX
Fig7_40
Figure 7
Frequency Response, Insertion Loss, Gain Tracking
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
S
R
TIPX
V
BExt
PBL 38640
R
LRTO
RINGX
Fig8_40
Figure 8
TIPX Voltage
Data Sheet
29
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Application Schematic
4
Application Schematic
sch_40
Figure 9
Application Example of PBL 38640/2 with SICOFI®4 Codec
Data Sheet
30
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Application Schematic
4.1
Recommended Components
Resistors
Table 6
Resistor
RSG
RLD
ROV
RLC
RREF
RR
RT
RRX
RTX
RB
R1
R2
Value
Tolerance Specification
0 Ω
–
1/10 W
1/10 W
–
49.9 kΩ
User programmable
32.4 kΩ
49.9 kΩ
22.7 kΩ
51 kΩ
51 kΩ
3.6 kΩ
6.2 kΩ
604 kΩ
1%
–
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
5%
1%
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
2 W
604 kΩ
249 kΩ
280 kΩ
330 Ω
R3
R4
RRT
RF1, RF2
Line resistor, 40 Ω
–
Table 7
Capacitors
Capacitor Value
Tolerance Specification
CVB
CVB2
CTC
CRC
CHP
CVCC
CLP
100 nF
150 nF
2.2 nF
2.2 nF
47 nF
100 nF
150 nF
100 nF
220 nF
10%
10%
10%
10%
10%
10%
10%
10%
10%
100 V
100 V
100 V
100 V
100 V
10 V
100 V
10 V
100 V
CTX
CGG
Data Sheet
31
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Application Schematic
Table 7
Capacitors (cont’d)
Capacitor Value
Tolerance Specification
C1
C2
330 nF
330 nF
10%
10%
63 V
63 V
Table 8
Diode
DVB
DVB2
DBB
Diodes
Value
1N4448
1N4448
1N4448
1N44481)
Tolerance Specification
DHP
1) It is required to connect DHP between terminals HP and ground if CHP > 47 nF
OVP
Secondary protection (Bournes TISP PBL2). The ground terminals of the secondary
protection should be connected to the common ground on the Printed Board Assembly
with a track as short and wide as possible, preferably to a ground plane.
4.2
Design Supporting Tools
The following supporting tools are available for the PBL 38640/2:
• Test board TB208 for PLCC package
• Test board TB208SSOP for SSOP package
• Pspice model for PBL 38640/2
Data Sheet
32
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Transmission
5
Transmission
5.1
General
A simplified AC model of the transmission circuit is shown in Figure 10.
TIP
RF
TIPX
HP
IL
ZL
EL
+
_
VTR
ZTR
VTX
RHP
G2-4S
VTX
IL
ZT
RING RF
RINGX
IL/αRSN
RSN
ZRX
PBL 38640
VRX
ac_sch_40
Figure 10
Simplified AC Model of PBL 38640/2
Circuit analysis from the AC model in Figure 10 yields following equations:
VTX
VTR = --------------- + IL × 2RF
G2 – 4S
[1]
IL
VTX VRX
------------ = --------- + ---------
[2]
[3]
α RSN
ZT ZRX
VTR = EL – IL × ZL
Data Sheet
33
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Transmission
where:
VTX
Is the ground referenced version of the AC metallic voltage between the
TIPX and RINGX terminals.
VTR
EL
IL
Is the AC metallic voltage between TIP and RING.
Is the line open circuit AC metallic voltage.
Is the AC metallic current.
RF
Is a fuse resistor.
G2-4S
Is the programmable SLIC two-wire to four-wire gain (transmit
direction)1).
ZL
Is the line impedance.
ZRX
ZT
VRX
αRSN
Controls four- to two-wire gain.
Determines the SLIC TIPX to RINGX impedance at voice frequencies.
Is the analog ground referenced receive signal.
Is the receive summing node current to metallic loop current gain.
αRSN = 200
1) The SLIC two-wire to four-wire gain, G2-4S, is user programmable between two fixed values. See Table 5.
5.2
Two-Wire Impedance
To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the
fuse resistor RF, let VRX = 0.
From Equation [1] and Equation [2]:
ZT
ZTR = ----------------------------------- + 2 RF
αRSN × G2 – 4S
[4]
[5]
Thus with ZTR, G2-4S, αRSN and RF known:
ZT = αRSN × G2 – 4S × (ZTR – 2RF)
5.3
Two-Wire to Four-Wire Gain
From Equation [1] and Equation [2] with VRX = 0:
ZT ⁄ αRSN
----------------------------------------------------
ZT
VTX
---------
G2 – 4
=
=
[6]
VTR
----------------------------------- + 2 RF
αRSN × G2 – 4S
Data Sheet
34
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Transmission
5.4
Four-Wire to Two-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
ZT
ZL
VTR
G4 – 2 = --------- = –
VRX
1
--------- --------------- ----------------------------------------------------------------
×
×
[7]
G2 – 4S
ZRX
ZT
----------------------------------- + ZL + 2RF
αRSN × G2 – 4S
For applications where
ZT
----------------------------------- + 2 RF = ZL
α RSN × G2 – 4S
[8]
[9]
the expression for G4-2 simplifies to:
ZT
1
-------------------------
G4 – 2 = –
×
---------
ZRX
2 × G2 – 4S
5.5
Four-Wire to Four-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
ZT
ZL + 2RF
VTX
G4 – 4 = --------- = –
VRX
--------- ----------------------------------------------------------------
×
[10]
ZRX
ZT
----------------------------------- + ZL + 2RF
αRSN × G2 – 4S
5.6
Hybrid Function
The hybrid function can easily be implemented utilizing the uncommitted amplifier in
conventional non software programmable codec/filters. Please, refer to Figure 11. Via
impedance ZB a current proportional to VRX is injected into the summing node of the
combination codec/filter amplifier. As can be seen from the expression for the four-wire
to four-wire gain, G4-4, a voltage proportional to VRX is returned to VTX. This voltage is
converted by RTX to a current flowing into the same summing node. These currents can
be cancelled by letting:
VTX VRX
--------- + --------- = 0
(EL = 0)
RTX ZB
[11]
Data Sheet
35
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Transmission
The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the
balance network ZB can be calculated from:
ZT
----------------------------------- + ZL + 2RF
α RSN × G2 – 4S
VRX
ZRX
×
---------
--------- ----------------------------------------------------------------
ZB = –RTX
×
= RTX
×
[12]
VTX
ZT
ZL + 2RF
When selecting the RTX resistance value, make sure the load resistance on the VTX
terminal is at least 20 kΩ.
If calculation of the ZB formula above yields a balance network containing an inductor,
please contact Infineon‘s support group for assistance.
The PBL 38640/2 SLIC may also be used together with programmable CODEC/filters.
The programmable CODEC/filter allows for system controller adjustment of hybrid
balance to accomodate different line impedances without change of hardware. In
addition, the transmit and receive gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets for design information.
RFB
RTX
VTX
VT
ZT
ZR
ZB
PBL 38640
Codec/Filter
ZRX
VRX
RSN
Hybrid_40
Figure 11
Hybrid Function
Data Sheet
36
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Transmission
5.7
Longitudinal Impedance
A feedback loop within the SLIC counteracts longitudinal voltages at the two-wire port by
injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will
appear as longitudinal currents and the TIPX and RINGX terminals will experience very
small longitudinal voltage excursions, leaving metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per wire, ZLOT and ZLOR, appears as typically 20 Ω to
longitudinal disturbances. It should be noted that longitudinal currents may exceed the
DC loop current without disturbing the VF transmission.
5.8
Capacitors CTC and CRC
The capacitors designated CTC and CRC in Figure 9, connected between TIPX and
ground as well as between RINGX and ground, can be used for RFI filtering. The
recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be
used, but care must be taken to prevent degradation of either longitudinal balance or
return loss. CTC and CRC contribute to a metallic impedance of 1/(π × f × CTC) =
1/(π × f × CRC), a TIPX to ground impedance of 1/(2π × f × CTC) and a RINGX to ground
impedance of 1/(2π × f × CRC).
5.9
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected between terminals HP and TIPX provides the
separation of the AC and DC signals, such that only AC signals are forwarded to the VTX
terminal. CHP positions the low end frequency response break point of the AC feedback
loop in the SLIC. A CHP value of 150 nF will position the low end frequency response
3 dB break point of the AC loop at 1.8 Hz (f3dB) according to f3dB = 1/(2π × RHP × CHP)
where RHP = 600 kΩ (see Table 9).
5.10
High-pass Transmit Filter
The capacitor CTX in Figure 9 connected between the VTX output and the CODEC/filter
forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a
high-pass RC filter. It is recommended to position the 3 dB break point of this filter
between 30 and 80 Hz to get a faster response for the DC steps that may occur at DTMF
signalling.
5.11
Capacitor CLP
The capacitor CLP, which connects between the terminals LP and VBAT, positions the
high end frequency break point of the low pass filter in the DC feedback loop (battery
feed controlling loop) of the SLIC. CLP together with CHP and ZT(see Chapter 5.2) forms
the total two-wire output impedance of the SLIC. The choice of these programmable
Data Sheet
37
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
components have an influence on the power supply rejection ratio (PSRR) from VBAT to
the two-wire side at sub audio frequencies.At these frequencies CLP also influences the
transversal to longitudinal balance in the SLIC. Table 9 suggests a suitable value for
CLP. The typical value of the transversal to longitudinal balance at 200 Hz is given in the
table below, for the chosen value of CLP.
Table 9
Symbol
RFeed
RSG
CLP
Feeding Setup
Value
2 x 400
Unit
Ω
2 x 50
0
150
-46
2 x 200
60.4
100
2 x 800
301
22
147
47
-43
kΩ
nF
dB
-46
-36
T-L bal. @
200 Hz
CHP
47
150
150
150
nF
6
Battery Feed
The PBL 38640/2 SLIC emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with adjustable current limitation. In the current limited region the loop
current has a slight slope corresponding to 2x30 Ω, see Figure 13 reference B.
The open loop voltage measured between the TIPX and RINGX terminals tracks the
battery voltage VBAT. The signalling headroom, or overhead voltage VTRO, is
programmable with a resistor ROV connected between terminal POV on the SLIC and
ground. Please refer to Chapter 6.2. The battery voltage overhead,VOH, depends on the
programmed signal overhead voltage VTRO. VOH defines the TIP and RING voltage at
open loop conditions according to
VTR(at IL = 0 mA) = |VBAT| - VOH
Refer to Table 10 for the typical value of VOH and VOHvirt. The overhead voltage is
changed when line corrent is approaching open loop conditions. To ensure maximum
open loop voltage, even with a leaking telephone line, this occurs at a line current of
approximately 6 mA. When the overhead voltage has changed, the line voltage is kept
nearly constant with a steep slope corresponding to 2x25 Ω (reference G in Figure 13).
The virtual battery overhead, VOHvirt , is defined as the difference between the battery
voltage and the crossing point of all possible resistive feeding slopes, see Figure 13
reference J. The virtual battery overhead is a theoretical constant needed to be able to
calculate the feeding characteristics.
Data Sheet
38
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
Table 10
Symbol
VOH
Battery Overhead
Value (typ)
3.0 + VTRO
Unit
V
V
Specification
–
–
VOHvirt
4.9 + VTRO
The resistive loop feed (reference D in Figure 13) is programmed by connecting a
resistor, RSG , between terminals PSG and VBAT according to the equation:
R
SG + 2×104
RFeed = ------------------------------- + 2 R F
[13]
200
where RFeed is in Ω for RSG and RF in Ω.
The current limit (reference C in Figure 13) is adjusted by connecting a resistor, RLC,
between terminal PLC and ground according to the equation:
1000
ILProg = ----------- – 4.0
[14]
RLC
where RLC is in kΩ for ILProg in mA.
A second lower battery voltage may be connected to the device at terminal VBAT2 to
reduce short loop power dissipation.
The SLIC automatically switches between the two battery supply voltages without need
for external control. the silent battery switching occurs when the line voltage passes the
value |VB2| - 40 × IL - (VOHvirt - 1.3), if IL > 6 mA.
For correct functionality it is important to connect the terminal VBAT2 to the second power
supply via the diode DVB2, see Figure 9. An optional diode DBB connected between
terminal VB and the VB2 power supply, see Figure 9, will make sure that the SLIC
continues to work on the second battery even if the first battery voltage disappears. If a
second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and CVB2, DBB
and DVB2 are removed.
6.1
CODEC Receive Interface
The PBL 38640/2 SLIC has got a receive interface at the four- wire side which makes it
possible to reduce the number of capacitors in the applications and to fit both single and
dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output
via the resistor RRX, is DC biased with +1.25 V. This makes it possible to compensate for
currents floating due to DC voltage differences between RSN and the CODEC output
without using any capacitors. This is done by connecting a resistor RR between the RSN
Data Sheet
39
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
terminal and ground. With current directions defined as in Figure 13, current summation
gives:
1.25 – VCODEC
1.25
1.25
RR
– IRSN = IRT + IRRX + IRR = --------- + -------------------------------------- + ---------
[15]
[16]
RT
RRX
where VCODEC is the reference voltage of the CODEC at the receive output.
From this equation the resistor RR can be calculated as
1.25
RR = -------------------------------------------------------------------------------
1.25 – VCODEC
1.25
RT
– IRSN – --------- – --------------------------------------
RRX
For the value on IRSN, see Table 11.
If RSN is DC decoupled from the CODEC output, then RRX can be considered to be
infinite.
The resistor RR has no influence in the AC transmission.
Table 11
Symbol
IRSN
Internal Bias Current of RSN
Value (typ)
-55
Unit
µA
VTX
RT
DC-GND
CODEC
I
IRT
RRX
IRSN
IRX
_
+
RSN
IRR
+1.25
UREFcodec
RR
codecIF
Figure 12
Codec Receive Interface
Data Sheet
40
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
A
B
C
A
B
C
D
D
E
G
H
F
F
J
batfeed40
VTR [V]
Figure 13
Battery Feed Characteristics
A
VBat – VOHvirt – RFeed × (ILProg + 4×10–3)
IL(VTR = 0V) = ILProg + --------------------------------------------------------------------------------------------------------------
60×103
B
C
R
Feed = 2x30 kΩ
103
--------- – 4 ×10–3
I
LConst(typ) = ILProg
=
RLC
VTR = |VBAT| - VOHvirt - RFeed x (ILProg + 4x10-3)
Data Sheet
41
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
D
R
SG + 2×104
RFeed = ------------------------------- + 2 R F
200
E
F
G
H
J
IL = 6 mA
Apparent battery VBat (@ IL = 0) = |VBAT| - VOHvirt - (RFeed x 4x10-3)
R
V
Feed = 2x25 Ω
TROpen = |VBAT| - VOH
Virtual battery VBatVirt (@ IL = 4 mA) = |VBAT| - VOHvirt
Data Sheet
42
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Battery Feed
6.2
Programmable Overhead Voltage (POV)
With the POV function the overhead voltage can be increased. If the POV pin is left open
the overhead voltage is internally set to 3.2 VPeak in off-hook and 1.3 VPeak on-hook.. If a
resistor ROV is connected between the POV pin and AGND, the overhead voltage can be
set to higher values, typical values can be seen in Figure 14. The ROV and
corresponding VTRO (signal headroom) are typical values for THD < 1% and the signal
frequency 1000 Hz.
Observe that the four-wire output terminal VTX cannot handle more than 3.2 VPeak. So if
the two- to four-wire gain is 0 dB, 3.2 VPeak is maximum also for the two-wire side. Signal
levels between 3.2 and 6.4 VPeak on the two-wire side can be handled with the PTG
shorted so that the gain G2-4S becomes -6.02 dB. Please note that:
• ZT
• RR
• G4 - 4
has to be recalculated if the PTG is shorted.
Please note that the maximum signal current at the two-wire side can not be higher than
9 mA.
How to use POV:
1. Decide what overhead voltage (VTRO) is needed. The POV function is only needed if
the overhead voltage exceeds 3.2 VPeak
.
2. In Figure 14 the corresponding ROV for the decided VTRO can be found.
If the overhead voltage exceeds 3.2 VPeak, the G2-4S gain has to be changed to -6.02 dB
by connecting pin PTG to AGND. Please note, that the 2-wire impedance, RR and the
4-wire to 4-wire gain has to be recalculated.
7
6
5
4
off-hook
on-hook
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
Rov (Kohm)
POV
Figure 14
Programmable Overhead Voltage (POV). RL= 600 Ω or Infinite
Data Sheet
43
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Loop Monitoring Functions
6.3
Analog Temperature Guard
The widely varying environmental conditions in which SLICs operate may lead to the
chip temperature limitations being exceeded. The PBL 38640/2 SLIC reduces the DC
line current when the chip temperature reaches approximately 145 oC and increases line
current again automatically when the temperature drops. Accordingly transmission is not
lost under high ambient temperature conditions.
The detector output, DET, is forced to a logic low level when the temperature guard is
active.
7
Loop Monitoring Functions
The loop current, ground key and ring-trip detectors report their status through a
common output, DET. The particular detector to be connected to the detector pin, DET,
is selected via the three bit control interface C1, C2 and C3. Please refer to Chapter 9
for a description of the control interface.
7.1
Loop Current Detector
The loop current detector indicates that the telephone is off-hook and that DC current is
flowing in the loop by setting the output pin DET to a logic low level when selected. The
loop current detector threshold value, ILTh, where the loop current detector changes
state, is programmable with the RLD resistor. RLD connects between pin PLD and ground
and is calculated according to:
500
RLD = ---------
[17]
ILth
The loop current detector is internally filtered and is not influenced by the AC signal at
the two-wire side.
7.2
Ground Key Detector
The ground key detector indicates when the ground key is pressed (active) by setting the
output pin DET to a logical high level when selected. The ground key detector circuit
senses the difference in TIPX and RINGX currents. When the current at the RINGX side
exceeds the current at the TIPX side with the threshold value the detector is triggered.
For threshold current values, please refer to the datasheet.
7.3
Ring Trip Detector
Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced
superimposed on VB or GND. The unbalanced ringing source may be applied to either
Data Sheet
44
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Relay Driver
the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC
ring relay driver connects the ringing source to tip and ring.
The ring trip function is based on a polarity change at the comparator input when the line
goes off-hook. In the on-hook state no DC current flows through the loop and the voltage
at comparator input DT is more positive than the voltage at input DR. When the line goes
off-hook, while the ring relay is energized, DC current flows and the comparator input
voltage reverses polarity.
Figure 9 gives an example of a ring trip detector network. This network is applicable
when the ring voltage is superimposed on VB and is injected on the ring lead of the two-
wire port. The DC voltage across sense resistor RRT is monitored by the ring trip
comparator input DT and DR via the network R1,R2 ,R3 ,R4 ,C1 and C2.
When the line is on-hook (no DC current), DT is more positive than DR and the DET
output will report logic level high, that is the detector is not tripped. When the line goes
off-hook, while ringing, a DC current will flow through the loop including sense resistor
RRT and will cause input DT to become more negative than input DR. This changes
output DET to logic level low, that is tripped detector conditions. The system controller
(or line card processor) responds by de-energizing the ring relay, that is ring trip.
Complete filtering of the 20 Hz AC component at terminal DT and DR is not necessary.
A toggling DET output can be examined by a software routine to determine the duty
cycle. When the DET output is at logic level low for more than half the time, off-hook
conditions is indicated.
8
Relay Driver
The PBL 38640/2 SLIC incorporates a ring relay driver designed as open collector (npn),
with a current sinking capability of 50 mA. The drive transistor emitter is connected to
BGND. The relay driver has an internal zener diode clamp for inductive kick back
voltages.
9
Control Inputs
The SLIC has three digital control inputs, C1, C2 and C3 (see Table 2). A decoder in the
SLIC interprets the control input condition and sets up the commanded operating state.
C1, C2 and C3 are internally pulled up.
9.1
Open Circuit (C3, C2, C1 = 0, 0, 0)
In the Open Circuit state, the TIPX and RINGX line drive amplifiers as well as other circuit
blocks are powered down. This causes the SLIC to present a high impedance to the line.
Power dissipation is at a minimum and no detectors are active. DET output is set high.
Data Sheet
45
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Overvoltage Protection
9.2
Ringing (C3, C2, C1 = 0, 0, 1)
The ring relay driver and the ring trip detector are activated and the ring trip detector is
indicating off-hook with a logic low level at the detector output. The SLIC is in the active
normal state.
9.3
Active States
TIPX is the terminal closest to ground and sources loop current while RINGX is the more
negative terminal and sinks loop current. VF signal transmission is normal. The loop
current or ground key detector is activated. The loop current detector is indicating off
hook with a logic low level and the ground key detector is indicating active ground key
with a logic high level present at the detector output.
In PBL 38640/2 SLIC a line voltage measurement feature is available in the active state,
which may be used for line length estimations or for line test purposes. The line voltage
is presented on the detector output as a pulse at logic high level with a pulsewidth of
5.5 µs/V. To start the line voltage measurement this mode has to be entered fron the
active state with the loop or ground key detector active. The pulse presented at the DET
output proportional to the line voltage starts when entering the line voltage measuring
mode.
9.4
Tip Open State
Tip open state is used for ground start signalling. In this state the SLICs present a high
impedance to the line on the TIPX pin and the programmed DC characteristics, with the
longitudinal current compensation (see Chapter 5.7) not active, to the line on the RINGX
pin. The loop current detector is active.
9.5
Active Polarity Reversal State
TIPX and RINGX polarity is reversed from the active state: RINGX is the terminal closest
to ground and sources loop current while TIPX is the more negative terminal and sinks
current. VF signal transmission is normal. The loop current or the ground key detector is
activated. The loop current detector is indicating off hook with a logic low level and the
ground key detector is indicating active ground key with a logic high level present at the
detector output.
10
Overvoltage Protection
10.1
Overvoltage Protection - General
The SLIC must be protected against foreign voltages on the telephone line.
Overvoltages can result from lightning, AC power contact, induction and other causes.
Data Sheet
46
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Power-Up Sequence
Refer to Table 3, TIPX and RINGX terminals, for maximum continuous and transient
voltages that may be applied to the SLIC.
10.2
Secondary Protection
The circuit shown in Figure 9 utilizes series resistors (RF1, RF2) together with a
programmable overvoltage protector (OVP, for example Bournes TISP PBL2) as
secondary protection.
The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The
protector gate references the protection (clamping) voltage to the negative supply
voltage (that is the battery voltage, VB). As the protection voltage will track the negative
supply voltage the overvoltage stress on the SLIC is minimized.
Positive overvoltages are clamped to ground by a diode. Negative overvoltages are
initially clamped close to the SLIC negative supply rail voltage and the protector will
crowbar into a low voltage on-state condition, by firing an internal thyristor.
A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high
enough current to quickly turn on the thyristor in the protector. CGG should be placed
close to the overvoltage protection device. Without the capacitor even the low
inductance in the track to the VB supply will limit the current and delay the activation of
the thyristor clamp.
The fuse resistors RF serve the dual purposes of being non-destructive energy
dissipators when transients are clamped, and of being fuses when the line is exposed to
a power cross. If a PTC is choosen for RF, note that it is important to always use PTC’s
in series with resistors not sensitive to temperature, as the PTC will act as a capacitance
for fast transients and therefore will not protect the SLIC.
11
Power-Up Sequence
No special power-up sequence is necessary, except that ground has to be present
before all other power supply voltages.
12
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout is essential for proper function. The
components connected to the RSN input should be placed in close proximity to that pin,
such that no interference is injected into the receive summing node (RSN). Ground plane
surrounding the RSN pin is advisable.
Analog Ground (AGND) should be connected to Battery Ground (BGND) on the PCB, in
one point. The capacitors for the battery should be connected with short wide leads of
the same length.
Data Sheet
47
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Package Outlines
13
Package Outlines
The SLIC is provided in three different packages: 24-pin SSOP, 24-pin PDSO and 28-pin
PLCC.
13.1
24-pin SSOP Package
1)
±0.1
5.3
B
+0.05
-0.06
0.15
0.65
C
0.1
±0.2
+0.08 2)
0.9
0.3
-0.05
M
0.15
A C 24x
M
0.2
B 24x
+0.1
-0.05
7.8
24
13
1
12
1)
A
±0.13
8.2
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
GPS01027
Figure 15
P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
48
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Package Outlines
13.2
24-pin PDSO Package
0.35 x 45˚
1)
7.6-0.2
+0.09
0.23
0.4 +0.8
1.27
0.1
2)
0.35 +0.15
0.2 24x
±0.3
10.3
24
13
1
12
1)
15.6 -0.4
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
gps05144
Figure 16
P-/PG-DSO-24-8 (Plastic Dual Small Outline Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
49
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38640/2
Package Outlines
13.3
28-pin PLCC Package
1)
±0.08
11.51
±0.07
1.27 x 45˚
0.73
1.27
±0.5
10.4
0.1
C
±0.13
12.45
7.62
±0.1
0.43
M
0.18
C A-B D 28x
D
A
B
Index Marking
1.45 x 45˚
28
11.51
1
±0.08
1)
±0.13
12.45
1) Does not include mold protrusion of 0.25 max. per side
GPL01023
Figure 17
P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
50
Rev. 2.0, 2005-04-14
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