AN87C196KDF8 [INTEL]
16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER; 16位高性能CHMOS单片机
| 型号： | AN87C196KDF8 |
| 厂家： | 
INTEL |
| 描述： | 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER |
| 文件： | 总21页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
87C196KD
16-BIT HIGH PERFORMANCE CHMOS
MICROCONTROLLER
Automotive
b
a
40 C to 125 C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Full Duplex Serial Port
§
§
Y
Y
Y
Y
Y
Y
32 Kbytes of On-Chip EPROM
232 Byte Register File
High Speed I/O Subsystem
16-Bit Timer
768 Bytes of Additional RAM
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.75 ms 16 x 16 Multiply (16 MHz)
3.0 ms 32/16 Divide (16 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16-Bit Software Timers
8- or 10-Bit 8-Channel A/D Converter
with Sample/Hold
Y
Y
HOLD/HLDA Bus Protocol
OTP One-Time Programmable and
QROM Versions
Y
Y
Available in 12 MHz and 16 MHz
Versions
16-Bit Watchdog Timer
Dynamically Configurable 8-Bit or
16-Bit Buswidth
16 MHz Operation
The 87C196KD 16-bit microcontroller is a high-performance member of the MCS 96 microcontroller family.
É
The 87C196KD is an enhanced 8XC196KC device with 1000 bytes RAM, 16 MHz operation and 32 Kbytes of
on-chip EPROM. Intel’s CHMOS process provides a high-performance processor along with low power con-
sumption.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
NOTICE:
This datasheet contains information on products in full production. Specifications within this datasheet
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
MCS 96 is a registered trademark of Intel Corporation.
É
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
January 1995
Order Number: 272168-002
AUTOMOTIVE 87C196KD
272168–1
Figure 1. 87C196KD Block Diagram
272168–2
Figure 2. The 87C196KD Family Nomenclature
87C196KD Enhanced Feature Set over the 87C196KC
1. The 87C196KD has twice the RAM and twice the EPROM of the 87C196KC.
2. The vertical windowing scheme has been extended to allow all 1000 bytes of register RAM to be windowed
into the lower register file.
3. A CLKOUT disable bit has been added to the IOC3 SFR. This can be used to reduce noise in systems not
requiring the CLKOUT signal.
2
AUTOMOTIVE 87C196KD
PACKAGING
PLCC
Description
PLCC
Description
AD6/P3.6
AD7/P3.7
PLCC
Description
9
8
ACH7/P0.7
ACH6/P0.6
ACH2/P0.2
ACH0/P0.0
ACH1/P0.1
ACH3/P0.3
NMI
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
P1.6/HLDA
P1.5/BREQ
HSO.1
7
AD8/P4.0
AD9/P4.1
6
HSO.0
5
AD10/P4.2
AD11/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
AD15/P4.7
T2CLK/P2.3
READY
HSO.5/HSI.3
HSO.4/HSI.2
HSI.1
4
3
2
EA
HSI.0
1
V
V
P1.4/PWM2
P1.3/PWM1
P1.2
CC
68
67
66
65
64
63
62
61
60
59
58
57
56
55
SS
XTAL1
XTAL2
P1.1
P1.0
CLKOUT
BUSWIDTH
INST
T2RST/P2.4
BHE/WRH
WR/WRL
TXD/P2.0
RXD/P2.1
RESET
ALE/ADV
RD
PWM0/P2.5
P2.7/T2CAPTURE
EXTINT/P2.2
AD0/P3.0
AD1/P3.1
AD2/P3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5
V
V
V
V
PP
SS
SS
REF
HSO.3
HSO.2
ANGND
ACH4/P.04
ACH5/P.05
P2.6/T2UP-DN
P1.7/HOLD
Figure 3. 68-Pin PLCC Functional Pin-out
3
AUTOMOTIVE 87C196KD
272168–3
Figure 4. 68-Pin PLCC Package
Table 1. Prefix Identification
PLCC
87C196KD
AN87C196KD*
*OTP Version
4
AUTOMOTIVE 87C196KD
PIN DESCRIPTIONS
Symbol
Name and Function
V
V
V
Main supply voltage (5V).
Digital circuit ground (0V). There are three V pins, all of which must be connected.
CC
SS
SS
Reference voltage for the A/D converter (5V). V
is also the supply voltage to the analog
REF
REF
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
.
V
SS
V
Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to
and a 1 MX resistor to V . If this function is not used V may be tied to V . This pin
is the programming voltage on the EPROM device.
PP
V
SS
CC
PP
CC
XTAL1
Input of the oscillator inverter and of the internal clock generator.
Output of the oscillator inverter.
XTAL2
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET
Reset input to the chip.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to a TTL-low causes accesses to those locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
e
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE
BHE/WRH
e
0 selects the bank of memory that is connected to the high byte of the data bus. A0
selects the bank of memory that is connected to the low byte of the data bus. Thus
0
e
e
1), to the
accesses to a 16-bit wide memory can be to the low byte only (A0
0, BHE
e
0, BHE 0). If the WRH function is
e
e
e
high byte only (A0
1, BHE
0), or both bytes (A0
selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH
is valid only during 16-bit external memory write cycles.
5
AUTOMOTIVE 87C196KD
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
Port 2
8-bit quasi-bidirectional I/O port.
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KD.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus.
HOLD
HLDA
BREQ
Bus Hold input requesting control of the bus.
Bus Hold acknowledge output indicating release of the bus.
Bus Request output activated when the bus controller has a pending external memory
cycle.
6
AUTOMOTIVE 87C196KD
ELECTRICAL CHARACTERISTICS
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 125 C
b
a
§
§
§
§
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
Voltage On Any Pin to V
SS
b
a
Except EA and V ÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V
PP
Voltage from EA or
b a
to V ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 13.0V
SS
V
PP
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.43W
OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Under Bias
Digital Supply Voltage
Min
Max
Units
b
a
T
A
40
125
5.50
5.50
16
C
§
V
V
4.50
4.50
4
V
CC
Analog Supply Voltage
Oscillator Frequency
V
REF
OSC
F
MHz
NOTE:
ANGND and V should be nominally at the same potential.
SS
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol
Description
Input Low Voltage
Min
Max
0.8
a
Units
Test Conditions
b
V
V
V
V
V
0.5
V
V
V
V
IL
a
Input High Voltage (Note 1)
Input High Voltage on XTAL 1, EA
Input High Voltage on RESET
Output Low Voltage
0.2 V
1.0
V
V
V
0.5
0.5
0.5
IH
CC
CC
a
a
0.7 V
IH1
IH2
OL
CC
CC
CC
2.2
e
e
e
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
2.8 mA
7 mA
OL
OL
OL
e a
V
V
Output Low Voltage
0.8
V
I
0.2 mA
OL1
OH
OL
in RESET on P2.5 (Note 2)
b
b
b
e b
e b
e b
Output High Voltage
(Standard Outputs)
V
V
V
0.3
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
CC
OH
OH
OH
0.7
1.5
CC
CC
b
b
b
e b
e b
e b
V
Output High Voltage
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
10 mA
30 mA
60 mA
OH1
CC
CC
CC
OH
OH
OH
(Quasi-bidirectional Outputs)
b
e
b
1.5 V
CC
I
Output High Current
0.8
mA
V
V
OH2
IH
In RESET on P2.0 (Note 2)
NOTES:
1. All pins except RESET, XTAL1 and EA.
2. Violating these specifications in Reset may cause the part to enter test modes.
7
AUTOMOTIVE 87C196KD
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol
Description
Min Typ
Max
Units
mA
mA
mA
mA
mA
mA
mA
X
Test Conditions
k
k
k
k
b
CC
g
I
I
I
I
I
I
I
Input Leakage Current (Std. Inputs)
Input Leakage Current (Port 0)
1 to 0 Transition Current (QBD Pins)
Logical 0 Input Current (QBD Pins)
Active Mode Current in Reset
A/D Converter Reference Current
Idle Mode Current
10
0
0
V
V
V
V
V
0.3V
LI
IN
IN
g
3
V
REF
LI1
TL
b
e
e
650
2.0V
IN
IN
b
70
75
0.45V
IL
e
65
XTAL1
e
16 MHz
e
CC
REF
IDLE
e
V
V
PP
V
5.5V
CC
REF
2
15
5
30
e
e
4.0V
R
RST
Reset Pullup Resistor
6K
65K
10
V
5.0V, V
CC
IN
C
S
Pin Capacitance (Any Pin to V
)
SS
pF
NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
3. Standard Inputs include HSI pins, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
4. Maximum current per pin must be externally limited to the following values if V is held above 0.45V or V is held
OL OH
b
on Output pins: 10 mA
on quasi-bidirectional pins: self limiting
on Standard Output pins: 10 mA
below V
0.7V:
CC
I
I
I
OL
OH
OH
g
5. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
I
I
I
: 29 mA
: 29 mA
: 13 mA
I
I
I
is self limiting
: 26 mA
: 11 mA
: 52 mA
: 13 mA
OL
OH
HSO, P2.0, RXD, RESET
P2.5, P2.7, WR, BHE
AD0–AD15
OL
OH
OH
OL
I
I
: 52 mA
OL
: 13 mA
I
OH
RD, ALE, INST–CLKOUT
I
OH
OL
8
AUTOMOTIVE 87C196KD
e
MAX
c
a
Freq 8.43
I
I
MAX
3.88
e
CC
IDLE
c
a
Freq 2.2
1.65
272168–4
Figure 5. I and I
CC
vs Frequency
IDLE
AC CHARACTERISTICS
For use over specified operating conditions.
e
e
e
16 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The system must meet these specifications to work with the 87C196KD:
Symbol
Description
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
b
75
T
T
T
T
T
T
T
T
T
T
T
T
T
Address Valid to READY Setup
ALE Low to READY Setup
2 T
AVYV
LLYV
YLYH
CLYX
LLYX
AVGV
LLGV
CLGX
AVDV
RLDV
CLDV
RHDZ
RXDX
OSC
b
T
77
OSC
Non READY Time
No upper limit
b
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
ALE Low to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
0
T
30
(Note 1)
(Note 1)
OSC
b
b
T
15
2 T
2 T
40
75
OSC
OSC
OSC
b
b
T
65
OSC
0
b
3 T
55
(Note 2)
(Note 2)
OSC
b
T
T
25
OSC
OSC
b
45
T
OSC
0
NOTES:
1. If max is exceeded, additional wait states will occur.
e
2. If wait states are used, add 2 T
* N, where N
number of wait states.
OSC
9
AUTOMOTIVE 87C196KD
AC CHARACTERISTICS (Continued)
For use over specified operating conditions.
e
e
e
16 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The 87C196KD will meet these specifications:
Symbol Description
Frequency on XTAL
Min
4.0
Max
16
Units
MHz
ns
Notes
(Note 1)
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
XTAL
OSC
1
I/F
62.5
20
250
110
XTAL
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
ns
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
2 T
ns
OSC
b
a
CLKOUT High Period
T
10
T
15
10
ns
OSC
OSC
b
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
5
15
ns
b
a
25
15
ns
4 T
ns
(Note 4)
OSC
b
b
b
b
a
ALE High Period
T
T
T
T
10
T
ns
OSC
OSC
OSC
OSC
OSC
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
15
35
35
AVLL
LLAX
ns
ns
ns
ns
ns
ns
ns
ns
LLRL
0
35
RLCL
RLRH
RHLH
RLAZ
LLWL
CLWL
QVWH
CHWH
WLWH
WHQX
WHLH
WHBX
WHAX
RHBX
RHAX
b
T
5
(Note 4)
(Note 2)
OSC
a
25
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
T
OSC
OSC
5
b
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
T
T
10
30
OSC
0
25
15
b
(Note 4)
(Note 4)
(Note 2)
(Note 3)
(Note 3)
OSC
b
5
ns
ns
ns
ns
ns
ns
ns
ns
b
b
b
b
b
b
b
T
T
T
T
T
T
T
30
25
10
10
30
10
25
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE, INST after WR Rising Edge
AD8–15 HOLD after WR Rising
BHE, INST after RD Rising Edge
AD8–15 HOLD after RD Rising
a
T
15
OSC
NOTES:
1. Testing performed at 4.0 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 T
e
number of wait states.
* N, where N
OSC
10
AUTOMOTIVE 87C196KD
System Bus Timings
272168–5
11
AUTOMOTIVE 87C196KD
READY Timings (One Wait State)
272168–6
Buswidth Timings
272168–7
12
AUTOMOTIVE 87C196KD
HOLD/HLDA Timings
Symbol
Description
Min
Max
Units
ns
Notes
T
T
T
T
T
T
T
T
T
T
HOLD Setup
60
(Note 1)
HVCH
b
b
CLKOUT Low to HLDA Low
15
15
15
15
15
20
15
15
ns
CLHAL
CLBRL
HALAZ
HALBZ
CLHAH
CLBRH
HAHAX
HAHBV
CLLH
CLKOUT Low to BREQ Low
ns
HLDA Low to Address Float
ns
HLDA Low to BHE, INST, RD, WR Weakly Driven
CLKOUT Low to HLDA High
ns
b
b
b
b
15
15
15
10
ns
CLKOUT Low to BREQ High
ns
HLDA High to Address No Longer Float
HLDA High to BHE, INST, RD, WR Valid
CLKOUT Low to ALE High
ns
15
15
ns
b
5
ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Min
Max
Units
e
e
e
Weak Pullups on ADV, RD,
WR, WRL, BHE
50K
250K
V
5.5V, V
0.45V
2.4
CC
CC
IN
Weak Pulldowns on
ALE, INST
e
5.5V, V
10K
50K
V
IN
272168–8
13
AUTOMOTIVE 87C196KD
EXTERNAL CLOCK DRIVE
Symbol
1/T
Parameter
Min
4.0
62.5
22
Max
16.0
250
Units
MHz
ns
Oscillator Frequency
Oscillator Frequency
High Time
XLXL
T
T
T
T
T
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
22
ns
Rise Time
10
10
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272168–9
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and
IL
V
IH
specifications the capacitance will not exceed 20 pF.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272168–10
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
272168–11
port pin is no longer floating when
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loaded V /V level occurs
For timing purposes
a
a
OH OL
e
g
15 mA.
I
/I
OL OH
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
HÐ High
Signals:
LÐ ALE/ADV
BRÐ BREQ
AÐ Address
BÐ BHE
LÐ Low
RÐ RD
VÐ Valid
CÐ CLKOUT
DÐ DATA
GÐ Buswidth
HÐ HOLD
HAÐ HLDA
WÐ WR/WRH/WRL
XÐ XTAL1
XÐ No Longer Valid
ZÐ Floating
YÐ READY
QÐ Data Out
14
AUTOMOTIVE 87C196KD
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
Symbol Parameter
Min
6 T
Max
Units
ns
t
Serial Port Clock Period (BRR 8002H)
T
T
XLXL
OSC
b
a
Serial Port Clock Falling Edge
t
to Rising Edge (BRR 8002H)
4 T
50
50
4 T
2 T
50
50
ns
XLXH
OSC
OSC
e
T
T
Serial Port Clock Period (BRR
8001H)
4 T
ns
ns
XLXL
OSC
b
a
Serial Port Clock Falling Edge
e
2 T
XLXH
OSC
OSC
to Rising Edge (BRR
8001H)
b
b
T
QVXH
T
XHQX
T
XHQV
T
DVXH
T
XHDX
T
XHQZ
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
Last Clock Rising to Output Float
2 T
2 T
50
50
ns
ns
ns
ns
ns
ns
OSC
OSC
a
2 T
50
OSC
a
T
50
OSC
0
1 T
OSC
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE
272168–12
15
AUTOMOTIVE 87C196KD
EPROM SPECIFICATIONS
AC EPROM Programming Characteristics
e
12.50V 0.25V, EA
e a
e
5V,
CC REF
g
Operating Conditions: Load Capacitance
e
150 pF, T
e
25 C 5 C, V , V
§
§
A
12.50V 0.25V
e
g
g
V
SS
, ANGND
0V, V
PP
Symbol
Description
Min
1100
50
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Reset High to First PALE Low
PALE Pulse Width
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
SHLL
LLLH
AVLL
LLAX
PLDV
PHDX
DVPL
PLDX
Address Setup Time
0
Address Hold Time
100
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
50
50
0
Data Hold Time
400
50
(2)
PROG Pulse Width
PLPH
PHLL
LHPL
PHPL
PHIL
ILIH
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
220
220
220
0
240
50
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Valid
ILVH
ILPL
170
220
PHVL
NOTES:
1. Run Time Programming is done with F
e
e
12.50V. For run-time programming over a full operating range, contact the factory.
e a
g
5V 0.50V. T
g
25 C to 5 C and
6.0 MHz to 12.0 MHz, V
§
§
OSC
REF
A
e
2. This specification is for the Word Dump Mode. For programming pulses, use 300 T
V
PP
a
100 ms.
OSC
DC EPROM Programming Characteristics
Symbol
Description
Min
Max
Units
I
V
Supply Current (When Programming)
PP
100
mA
PP
NOTE:
k
while V
CC
V
PP
V
CC
must be within 1V of V
l
4.5V. V must not have a low impedance path to ground of V while
PP SS
CC
4.5V.
16
AUTOMOTIVE 87C196KD
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272168–13
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
272168–14
17
AUTOMOTIVE 87C196KD
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND
AUTO INCREMENT
272168–15
18
AUTOMOTIVE 87C196KD
of V
. V
must be close to V since it supplies
REF REF CC
10-BIT A/D CHARACTERISTICS
both the resistor ladder and the digital section of the
converter.
The speed of the A/D converter in the 10-bit mode
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 6 MHz. The conver-
sion times with the prescaler turned on or off is
A/D CONVERTER SPECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data-
sheet. Testing is performed with V
shown in the table below. The AD TIME register
Ð
has not been characterized for the 10-bit mode.
e
5.12V.
REF
The converter is ratiometric, so the absolute accura-
cy is dependent on the accuracy and stability
Clock Prescaler On
e
Clock Prescaler Off
e
1
IOC2.4
0
IOC2.4
156.5 States
@
89.5 States
@
19.5 ms 16 MHz
29.8 ms 6 MHz
(3)
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
4
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
g
Full Scale Error
3
3
Zero Offset Error
g
a
Non-Linearity
0
4
2
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
1, 2
1
b
b
60
60
V
CC
Power Supply Rejection
1
Input Resistance
DC Input Leakage
750
0
1.2K
3.0
mA
Sample Time: Prescaler On
Prescaler Off
16
8
States
States
Input Capacitance
3
pF
NOTES:
*An ‘‘LSB’’, as used here, has a value of approximately 5 mV.
1. DC to 100 KHz.
2. Multiplexer Break-Before-Make Guaranteed.
3. Typical values are expected for most devices at 25 C.
§
19
AUTOMOTIVE 87C196KD
8-BIT MODE A/D CHARACTERISTICS
Sample Time
20 States
Convert Time
56 States
The 8-bit mode trades off resolution for a faster con-
version time. The AD TIME register must be used
A6H in AD TIME
Ð
9.8 ms 16 MHz
Ð
when performing an 8-bit conversion.
@
@
The following specifications are tested
16 MHz
with OA6H in AD TIME. The actual AD TIME reg-
Ð
Ð
ister is tested with all possible values, to ensure
functionality, but the accuracy of the A/D converter
is not.
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
256
8
256
8
Levels
Bits
g
Absolute Error
0
2
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
g
Full Scale Error
1
2
Zero Offset Error
g
a
Non-Linearity
0
2
1
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.003
0.003
0.003
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
NOTES:
*An ‘‘LSB’’, as used here, has a value of approximately 20 mV.
1. Typical values are expected for most devices at 25 C.
§
4. ONCE Mode Entry. The ONCE mode is entered
on the 87C196KD by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
high by a pullup that is specified at 1.4 mA and
remain at 2.0V. This Pullup must not be overrid-
den or the 87C196KD will enter the ONCE mode.
8XC196KB TO 87C196KD DESIGN
CONSIDERATIONS
1. Memory Map. The 87C196KD has 512 bytes of
RAM/SFRs and 32K of ROM/EPROM. The extra
256 bytes of RAM will reside in locations 100H–
1FFH and the extra 24K of EPROM will reside in
locations 4000H–9FFFH. These locations are
external memory on the 87C196KB.
5. During the bus HOLD state, the 87C196KD weak-
ly holds RD, WR, ALE, BHE and INST in their
inactive states. The 87C196KB only holds ALE in
its inactive state.
2. The CDE pin on the KB has become a V pin on
SS
the KC to support 16 MHz operation.
6. A RESET pulse from the 87C196KD is 16 states
rather than 4 states as on the 87C196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
3. EPROM programming. The 87C196KD has a dif-
ferent programming algorithm to support 32K of
on-board memory. When performing Run-Time
Programming, use the section of code on page
99 of the 80C196KC User’s Guide, Order Num-
ber 270704.
20
AUTOMOTIVE 87C196KD
2. In Mode 0, the serial port does not work if the
e
8XC196KD ERRATA
highest baud rate is selected (SP BAUD
Ð
8001h). Data shifted into the device will not be
correctly read at this baud rate.
1. It is possible for the device to fail to recognize an
interrupt on EXTINIT, for both P2.2 and P0.7, and
NMI. The problem is most likely to occur on P0.7
while the device is operating at low voltage
k
(
perature ( 85 C). There is a window of about
4.7V), high frequency (16 MHz) and high tem-
l
DATASHEET REVISION HISTORY
§
The following are the key differences between this
datasheet and the -005 version:
2 ns near clockout falling during which these in-
terrupts may be missed.
1. The ‘‘preliminary’’ status was dropped and re-
placed with production status (no label).
Trademarks were updated.
21
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