AN87C196LA [INTEL]
CHMOS 16-BIT MICROCONTROLLER; CHMOS 16位微控制器
| 型号： | AN87C196LA |
| 厂家： | 
INTEL |
| 描述： | CHMOS 16-BIT MICROCONTROLLER |
| 文件： | 总21页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT PREVIEW
87C196LA
CHMOS 16-BIT MICROCONTROLLER
Automotive
■ 20 MHz operation†
■ Full-duplex serial I/O port with
dedicated baud-rate generator
■ 24 Kbytes of on-chip OTPROM
■ 768 bytes of on-chip register RAM
■ Register-to-register architecture
■ Enhanced full-duplex, synchronous
serial I/O port (SSIO)
■ Programmable 8- or 16-bit external bus
■ Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
■ Optional clock doubler with
programmable clock output signal
■ SFR register that indicates the source
■ Six-channel/10-bit A/D with sample and
of the last reset
hold
■ Design enhancements for EMI
■ High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
reduction
■ Oscillator failure detection circuitry
■ Watchdog timer (WDT)
■ –40° C to +125° C ambient temperature
■ 52-pin PLCC package
†
16 MHz standard; 20 MHz is speed premium
NOTE
This datasheet contains information on products in the design phase of development.
The specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed
core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a
dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave
transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with
prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture
and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis-
ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock
doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock
speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices
where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O
ports are driven low at reset, avoiding the need for pull-up resistors.
COPYRIGHT © INTEL CORPORATION, 1996
October 1996
Order Number: 272806-001
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel dis-
claims any express or implied warranty, relating to sale and/or use of Intel products including liability or war-
ranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or
other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel liter-
ature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
AUTOMOTIVE — 87C196LA
Port 6
Port 0
Enhanced
SSIO
A/D
Converter
Watchdog
Timer
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
Port 2
Bus Control
Baud-rate
SIO
Bus
Controller
Generator
AD15:0
Peripheral
Transaction
Server
Bus-Control
6 Capture/
Compare
Channels †
Interface Unit
Queue
Interrupt
Controller
EPA
2 Timers
Microcode
Engine
2
Compare-only
Channels
Source (16)
Port 1,6
Memory
Interface
Unit
Register RAM
768 Bytes
ALU
Destination (16)
OTPROM
24 Kbytes
† Two additional capture/compare channels (EPA6 and EPA7) are available as software timers.
They are not connected to package pins.
A3417-01
Figure 1. 87C196LA Block Diagram
PRODUCT PREVIEW
3
87C196LA — AUTOMOTIVE
1.0 NOMENCLATURE OVERVIEW
X
XX
8
X
X
XXXXX XX
A2815-02
Figure 2. Product Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in Options
A
Automotive operating temperature range (–40° C to
125° C ambient) with Intel standard burn-in.
Packaging Options
Program-memory Options
Process Information
Product Family
N
7
PLCC
OTPROM
C
CHMOS
196Lx
no mark
20
8XC196Lx family of products
Device Speed
16 MHz
20 MHz
4
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
2.0 PINOUT
AD14 / P4.6 / PBUS.14
AD13 / P4.5 / PBUS.13
AD12 / P4.4 / PBUS.12
AD11 / P4.3 / PBUS.11
AD10 / P4.2 / PBUS.10
AD9 / P4.1 / PBUS.9
AD8 / P4.0 / PBUS.8
AD7 / P3.7 / PBUS.7
AD6 / P3.6 / PBUS.6
AD5 / P3.5 / PBUS.5
AD4 / P3.4 / PBUS.4
AD3 / P3.3 / PBUS.3
AD2 / P3.2 / PBUS.2
8
9
46
45
44
43
42
41
40
39
38
37
36
35
34
P6.1 / EPA9 / COMP1
P6.0 / EPA8 / COMP0
P1.0 / EPA0 / T2CLK
P1.1 / EPA1
10
11
12
13
14
15
16
17
18
19
20
AN87C196LA
P1.2 / EPA2 / T2DIR
P1.3 / EPA3
V
REF
ANGND
View of component as
mounted on PC board
P0.7 / ACH7 / PMODE.3
P0.6 / ACH6 / PMODE.2
P0.5 / ACH5 / PMODE.1
P0.4 / ACH4 / PMODE.0
P0.3 / ACH3
A3419-01
Figure 3. 87C196LA 52-pin Package
PRODUCT PREVIEW
5
87C196LA — AUTOMOTIVE
Table 2. 87C196LA 52-pin Package Pin Assignments
Pin Name Pin
Pin
1
Name
Name
VSS1
19 AD3 / P3.3 / PBUS.3
20 AD2 / P3.2 / PBUS.2
21 AD1 / P3.1 / PBUS.1
22 AD0 / P3.0 / PBUS.0
23 RESET#
37 P0.6 / ACH6 / PMODE.2
38 P0.7 / ACH7 / PMODE.3
39 ANGND
2
P5.0 / ADV# / ALE
VSS
3
4
VPP
40 VREF
5
P5.3 / RD#
41 P1.3 / EPA3
6
P5.2 / PLLEN / WR# / WRL#
AD15 / P4.7 / PBUS.15
AD14 / P4.6 / PBUS.14
AD13 / P4.5 / PBUS.13
24 EA#
42 P1.2 / EPA2 / T2DIR
43 P1.1 / EPA1
7
25 VSS1
8
26 VCC
44 P1.0 / EPA0 / T2CLK
45 P6.0 / EPA8 / COMP0
46 P6.1 / EPA9 / COMP1
47 P6.4 / SC0
9
27 P2.0 / TXD / PVER
28 P2.1 / RXD / PALE#
29 P2.2 / EXTINT / PROG#
30 P2.4 / AINC#
10 AD12 / P4.4 / PBUS.12
11 AD11 / P4.3 / PBUS.11
12 AD10 / P4.2 / PBUS.10
13 AD9 / P4.1 / PBUS.9
14 AD8 / P4.0 / PBUS.8
15 AD7 / P3.7 / PBUS.7
16 AD6 / P3.6 / PBUS.6
17 AD5 / P3.5 / PBUS.5
18 AD4 / P3.4 / PBUS.4
48 P6.5 / SD0
31 P2.6 / CPVER
49 P6.6 / SC1
32 P2.7 / CLKOUT / PACT#
33 P0.2 / ACH2
50 P6.7 / SD1
51 XTAL2
34 P0.3 / ACH3
52 XTAL1
35 P0.4 / ACH4 / PMODE.0
36 P0.5 / ACH5 / PMODE.1
6
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 3. Pin Assignment Arranged by Functional Categories
Input/Output (Cont’d) Program Control
Name Pin Name
P2.1 / RXD AINC#
Addr & Data
Processor Control
Name
Pin
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Pin
30
31
32
28
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Name
EA#
Pin
24
29
6
AD0
28
29
30
31
32
22
21
20
19
18
17
16
15
14
13
12
11
10
9
AD1
P2.2
P2.4
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.2
P5.3
CPVER
PACT#
EXTINT
PLLEN
RESET#
XTAL1
XTAL2
AD2
AD3
PALE#
23
52
51
AD4
PBUS.0
PBUS.1
PBUS.2
PBUS.3
PBUS.4
PBUS.5
PBUS.6
PBUS.7
PBUS.8
PBUS.9
PBUS.10
PBUS.11
PBUS.12
PBUS.13
PBUS.14
PBUS.15
PMODE.0
PMODE.1
PMODE.2
PMODE.3
PROG#
PVER
AD5
AD6
AD7
Bus Cont & Status
AD8
Name
ADV# / ALE
CLKOUT
RD#
Pin
2
AD9
AD10
AD11
AD12
AD13
AD14
AD15
32
5
WR# / WRL#
6
8
Power & Ground
7
Name
ANGND
VCC
Pin
39
26
4
Input/Output
Name
Pin
33
34
35
36
37
38
8
V
PP
P0.2 / ACH2
P0.3 / ACH3
P0.4 / ACH4
P0.5 / ACH5
P0.6 / ACH6
P0.7 / ACH7
8
7
VREF
VSS
40
3
7
35
36
37
38
29
27
2
VSS1
VSS1
1
6
25
5
P6.0 / EPA8 / COMP0 45
P6.1 / EPA9 / COMP1 46
P1.0 / EPA0 / T2CLK 44
P1.1 / EPA1 43
P1.2 / EPA2 / T2DIR 42
P6.4 / SC0
P6.5 / SD0
P6.6 / SC1
P6.7 / SD1
47
48
49
50
P1.3 / EPA3
P2.0 / TXD
41
27
PRODUCT PREVIEW
7
87C196LA — AUTOMOTIVE
3.0 SIGNALS
Table 4. Signal Descriptions
Description
Name
ACH7:2
Type
I
Analog Channels
These signals are analog inputs to the A/D converter.
The A/D inputs share package pins with port 0. These pins may individually be
used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the
pins to function simultaneously as analog and digital inputs, this is not
recommended because reading port 0 while a conversion is in process can
produce unreliable conversion results.
The ANGND and VREF pins must be connected for the A/D converter and port 0
to function.
ACH7:2 share package pins with the following signals: ACH2/P0.2, ACH3/P0.3,
ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1, ACH6/P0.6/PMODE.2, and
ACH7/P0.7/PMODE.3.
AD15:0
I/O
Address/Data Lines
These pins provide a multiplexed address and data bus. During the address
phase of the bus cycle, address bits 0–15 are presented on the bus and can be
latched using ALE or ADV#. During the data phase, 8- or 16-bit data is
transferred.
AD7:0 share package pins with P3.7:0 and PBUS.7:0; AD15:8 share package
pins with P4.7:0 and PBUS.15:8.
ADV#
O
Address Valid
This active-low output signal is asserted only during external memory
accesses. ADV# indicates that valid address information is available on the
system address/data bus. The signal remains low while a valid bus cycle is in
progress and is returned high as soon as the bus cycle completes.
An external latch can use this signal to demultiplex the address from the
address/data bus. A decoder can also use this signal to generate chip selects
for external memory.
ADV# shares a package pin with P5.0 and ALE.
Auto Increment
AINC#
I
During slave programming, this active-low input enables the auto-increment
feature. (Auto increment allows reading or writing of sequential OTPROM
locations, without requiring address transactions across the programming bus
for each read or write.) AINC# is sampled after each location is programmed or
dumped. If AINC# is asserted, the address is incremented and the next data
word is programmed or dumped.
AINC# shares a package pin with P2.4.
8
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 4. Signal Descriptions (Continued)
Description
Name
Type
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus.
An external latch can use this signal to demultiplex the address from the
address/data bus.
ALE shares a package pin with P5.0 and ADV#.
ANGND
GND Analog Ground
ANGND must be connected for A/D converter and port 0 operation. ANGND
and VSS should be nominally at the same potential.
CLKOUT
O
O
O
I
Output
Output of the internal clock generator. You can select one of three frequencies:
f, f/2, or f/4. CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7 and PACT#.
COMP1:0
CPVER
EA#
Event Processor Array (EPA) Compare Pins
These signals are the outputs of the EPA compare-only channels.
COMP1:0 share package pins with the following signals: COMP0/P6.0/EPA8
and COMP1/P6.1/EPA9.
Cumulative Program Verification
During slave or programming, a high signal indicates that, while a low signal
indicates that an error occurred during the program operation.
CPVER shares a package pin with P2.6 and ONCE#.
External Access
This input determines whether memory accesses to special-purpose and
program memory partitions are directed to internal or external memory. These
accesses are directed to internal memory if EA# is held high and to
externalmemory if EA# is held low. For an access to any other memory location,
the value of EA# is irrelevant.
EA# also controls entry into the programming modes. If EA# is at VPP voltage
(typically +12.5 V) on the rising edge of RESET#, the microcontroller enters a
programming mode.
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.
EPA9:8
EPA3:0
I/O
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
The EPA signals share package pins with the following signals:
EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7:6 do not connect to
package pins. They cannot be used to capture an event, but they can function
as software timers. EPA5:4 are not implemented.
PRODUCT PREVIEW
9
87C196LA — AUTOMOTIVE
Table 4. Signal Descriptions (Continued)
Name
EXTINT
Type
Description
I
External Interrupt
In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending bit. EXTINT is sampled during phase 2. The minimum high time is one
state time.
In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
device to resume normal operation. The interrupt does not need to be enabled.
If the EXTINT interrupt is enabled, the CPU executes the interrupt service
routine. Otherwise, the CPU executes the instruction that immediately follows
the command that invoked the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume
normal operation.
EXTINT shares a package pin with P2.2 and PROG#.
P0.7:2
I
Port 0
This is a high-impedance, input-only port. Port 0 pins should not be left floating.
The port 0 signals share package pins with the A/D inputs. These pins may
individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is
possible for the pins to function simultaneously as analog and digital inputs, this
is not recommended because reading port 0 while a conversion is in process
can produce unreliable conversion results.
ANGND and VREF must be connected for port 0 to function.
P0.3:2 share package pins with ACH3:2 and P0.7:4 share package pins with
ACH7:4 and PMODE.3:0.
P1.3:0
I/O
I/O
Port 1
This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.
Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK,
P1.1/EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3.
P2.7:6
P2.4
P2.2:0
Port 2
This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.
Port 2 shares package pins with the following signals: P2.0/TXD/PVER,
P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#, P2.6/ONCE#/CPVER,
P2.7/OSCOUT/PACT#.
P3.7:0
P4.7:0
I/O
I/O
Port 3
This is a memory-mapped, 8-bit, bidirectional port with programmable open-
drain or complementary output modes. The pins are shared with the multiplexed
address/data bus, which has complementary drivers.
P3.7:0 share package pins with AD7:0 and PBUS.7:0.
Port 4
This is a memory-mapped, 8-bit, bidirectional port with open-drain or
complementary output modes. The pins are shared with the multiplexed
address/data bus, which has complementary drivers.
P4.7:0 share package pins with AD15:8 and PBUS.15:8.
10
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 4. Signal Descriptions (Continued)
Name
Type
Description
P5.3:2
P5.0
I/O
Port 5
This is a memory-mapped, bidirectional port.
Port 5 shares package pins with the following signals: P5.0/ADV#/ALE,
P5.2/WR#/WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not
implemented.
P6.7:4
P6.1:0
O
O
Port 6
This is a standardbidirectional port.
Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0,
P6.1/EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1.
PACT#
Programming Active
During auto programming or slave dump, a low signal indicates that
programming or dumping is in progress, while a high signal indicates that the
operation is complete.
PACT# shares a package pin with P2.7 and OSCOUT.
Programming ALE
PALE#
I
During slave programming, a falling edge causes the device to read a
command and address from the programming bus.
PALE# is multiplexed with P2.1 and RXD.
Address/Command/Data Bus
PBUS.15:0
I/O
During slave programming, ports 3 and 4 serve as a bidirectional port with
open-drain outputs to pass commands, addresses, and data to or from the
device. Slave programming requires external pull-up resistors.
During auto programming and ROM-dump, ports 3 and 4 serve as a regular
system bus to access external memory. P4.6 and P4.7 are left unconnected;
P1.1 and P1.2 serve as the upper address lines.
Slave programming:
PBUS.7:0 share package pins with AD7:0 and P3.7:0.
PBUS.15:8 share package pins with AD15:8 and P4.7:0.
Auto programming:
PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share
package pins with AD7:0 and P3.7:0.
PLLEN
I
I
Phase-locked Loop Enable
This active-high input pin enables the on-chip clock multiplier.
PMODE.3:0
Programming Mode Select
These pins determine the programming mode. PMODE:0 are sampled after a
device reset and must be static while the microcontroller is operating.
PMODE:0 share package pins with P0.7:4 and ACH7:4.
PRODUCT PREVIEW
11
87C196LA — AUTOMOTIVE
Table 4. Signal Descriptions (Continued)
Description
Name
PROG#
Type
I
Programming Start
Duringprogramming, a falling edge latches data on the programming bus and
begins programming, while a rising edge ends programming. The current
location is programmed with the same data as long as PROG# remains
asserted, so the data on the programming bus must remain stable while
PROG# is active.
During a word dump, a falling edge causes the contents of an OTPROM
location to be output on the PBUS, while a rising edge ends the data transfer.
PROG# shares a package pin with P2.2 and EXTINT.
Program Verification
PVER
O
During slave or auto programming, PVER is updated after each programming
pulse. A high output signal indicates successful programming of a location,
while a low signal indicates a detected error.
PVER shares a package pin with P2.0 and TXD.
Read
RD#
O
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# shares a package pin with P5.3.
Reset
RESET#
I/O
A level-sensitive reset input to, and an open-drain system reset output from, the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown and idle modes, asserting RESET# causes the chip to reset and
return to normal operating mode. After a device reset, the first instruction fetch
is from 2080H.
RXD
I/O
I/O
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as either an input or an open-drain output for data.
RXD shares a package pin with P2.1 and PALE#.
SC1:0
Clock Pins for SSIO0 and 1
For handshaking transfers, configure SC1:0 as open-drain outputs.
This pin carries a signal only during receptions and transmissions. When the
SSIO port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6.
Data Pins for SSIO0 and 1
SD1:0
I/O
These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure
SDx as a complementary output signal. For receptions, configure SDx as a
high-impedance input signal.
SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7.
12
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 4. Signal Descriptions (Continued)
Description
Name
T2CLK
Type
I
Timer 2 External Clock
External clock for timer 2. Timer 2 increments (or decrements) on both rising
and falling edges of T2CLK. It is also used in conjunction with T2DIR for
quadrature counting mode.
T2CLK shares a package pin with P1.0 and EPA0.
Timer 2 External Direction
T2DIR
TXD
I
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. It is also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR shares a package pin with P1.2 and EPA2.
Transmit Serial Data
O
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode
0, it is the serial clock output.
TXD shares a package pin with P2.0 and PVER.
VCC
VPP
PWR Digital Supply Voltage
Connect each VCC pin to the digital supply voltage.
PWR Programming Voltage
V
PP causes the device to exit powerdown mode when it is driven low for at least
50 ns. Use this method to exit powerdown only when using an external clock
source because it enables the internal phase clocks, but not the internal
oscillator.
If you do not plan to use the powerdown feature, connect VPP to VCC
.
VREF
PWR Reference Voltage for the A/D Converter
This pin supplies operating voltage to the A/D converter.
VSS, VSS1
GND Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each VSS and VSS1 pin
to ground through the lowest possible impedance path. VSS pins are connected
to the core ground region of the microcontroller, while VSS1 pins are connected
to the port ground region. (ANGND is connected to the analog ground region.)
Separating the ground regions provides noise isolation.
†
WR#
O
Write
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
Forcing WR# high while RESET# is low causes the device to enter PLL-bypass
mode. When the device is in PLL-bypass mode, the internal phase clocks
operate at one-half the frequency of the frequency on XTAL1.
WR# shares a package pin with P5.2, WRL#, and PLLEN.
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR#
or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
PRODUCT PREVIEW
13
87C196LA — AUTOMOTIVE
Table 4. Signal Descriptions (Continued)
Name
WRL#
Type
Description
†
O
Write Low
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes to external memory. During 8-bit bus cycles, WRL# is
asserted for all write operations.
WRL# shares a package pin with P5.2, WR#, and PLLEN.
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR#
or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
XTAL2
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal
clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal.
When using an external clock source instead of the on-chip oscillator, connect
the clock input to XTAL1. The external clock signal must meet the VIH
specification for XTAL1.
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
14
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
4.0 ADDRESS MAP
Table 5. Address Map
Description
Hex
Address
Range
Addressing
Modes
FFFF
External device (memory or I/O) connected to address/data bus
Indirect or indexed
Indirect or indexed
8000
7FFF
2080
Program memory (internal nonvolatile or external memory); see
Note 1
207F
2000
Special-purpose memory (internal nonvolatile or external memory) Indirect or indexed
1FFF
1FE0
Memory-mapped SFRs
Peripheral SFRs
Indirect or indexed
1FDF
1F00
Indirect, indexed, or win-
dowed direct
1EFF
0300
External device (memory or I/O) connected to address/data bus;
(future SFR expansion; see Note 2)
Indirect or indexed
02FF
0100
Indirect, indexed, or win-
dowed direct
Upper register file (general-purpose register RAM)
00FF
0000
Direct, indirect, or
indexed
Lower register file (register RAM, stack pointer, and CPU SFRs)
NOTES:
1. After a reset, the microcontroller fetches its first instruction from 2080H.
2. The content or function of these locations may change in future microcontroller revisions, in which
case a program that relies on a location in this range might not function properly.
5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
NOTICE: This document contains information
on products in the design phase of develop-
ment. Do not finalize a design with this infor-
mation. Revised information will be published
when the product is available. Verify with your
local Intel sales office that you have the latest
datasheet before finalizing a design.
Storage Temperature ................................. –60°C to +150° C
Voltage from VPP or EA# to VSS or ANGND... –0.5V to +13.0 V
Voltage from any other pin to VSS or ANGND ...–0.5V to +7.0V
Power Dissipation .......................................................... 0.5 W
†
OPERATING CONDITIONS
†
WARNING: Stressing the device beyond the
TA (Ambient Temperature Under Bias) ......... –40°C to +125°C
“Absolute Maximum Ratings” may cause per-
manent damage. These are stress ratings
only. Operation beyond the “Operating Condi-
tions” is not recommended and extended
exposure beyond the “Operating Conditions”
may affect device
V
V
CC (Digital Supply Voltage) ............................ 4.50V to 5.50V
REF (Analog Supply Voltage)(Notes 1, 2).........4.50V to 5.50V
F
XTAL1 (Input Frequency):
- PLL in 2x mode............................4 MHz to 10 MHz
- PLL in 1x mode............................8 MHz to 20 MHz
reliability.
NOTES:
1. ANGND and VSS should be nominally at the same potential.
2. VREF should not exceed VCC by more than 0.5V.
PRODUCT PREVIEW
15
87C196LA — AUTOMOTIVE
5.1 DC Characteristics
Table 6. DC Characteristics at VCC = 4.5V to 5.5V
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions (Note 1)
ICC
VCC supply current
FXTAL1 = 20 MHz,
50
TBD
mA
(–40° C to +125° C
ambient)
VCC = VPP = VREF = 5.5V
(While device is in reset)
ICC1
IREF
IIDLE
IPD
Active mode supply cur-
rent (typical)
50
mA
A/D reference supply
current
2
TBD
TBD
mA
mA
Idle mode current
15
FXTAL1 = 20 MHz,
V
CC = VPP = VREF = 5.5V
Powerdown mode
current
VCC = VPP = VREF = 5.5V
(Note 2)
50
TBD
µA
VIL
Input low voltage
(all pins)
– 0.5V
0.3 VCC
V
V
VIH
VOL
Input high voltage (all
pins)
0.7 VCC
VCC + 0.5
(Note 3)
Output low voltage
(outputs configured as
complementary)
0.3
0.45
1.5
V
V
V
I
I
I
OL = 200 µA (Notes 4, 5)
OL = 3.2 mA
OL = 7.0 mA
VOH
Output high voltage
(outputs configured as
complementary)
V
V
V
CC – 0.3
CC – 0.7
CC – 1.5
V
V
V
IOH = – 200 µA (Notes 4, 5)
I
I
OH = – 3.2 mA
OH = – 7.0 mA
ILI
Input leakage current
(standard inputs)
± 8
± 1
+175
1
µA
µA
µA
V
V
V
V
SS ≤ VIN ≤ VCC (Note 6)
ILI1
Input leakage current
(port 0—A/D inputs)
SS ≤ VIN ≤ VREF
IIH
Input high current (NMI
pin only)
SS ≤ VIN ≤ VCC
VOL2
NOTES:
Output low voltage in
reset
IOL = 6 µA (Notes 7, 8)
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL
enabled. With the PLL bypassed, the device is tested only down to 8MHz.
2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VREF = VCC = 5.5V.
3.
VIH max for port 0 is VREF + 0.5V.
4. All bidirectional pins when configured as complementary outputs.
5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values
are ± 10 mA.
6. Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
7. All bidirectional pins except P5.1/INST and P2.7/CLKOUT, which are excluded because they are not
weakly pulled low in reset. Bidirectional pins include ports 1–6.
8. This specification is not tested in production and is based upon theoretical estimates and/or product
characterization.
16
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 6. DC Characteristics at VCC = 4.5V to 5.5V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions (Note 1)
IOL2
Output low current in
reset
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
VOL2 = TBD
VOL2 = TBD
VOL2 = TBD
RRST
VOL3
Reset pullup resistor
6K
65K
Ω
Output low voltage in
reset (RESET# pin
only)
0.3
0.5
0.8
V
V
V
IOL3 = 4 mA (Note 8)
IOL3 = 6 mA
IOL3 = 10 mA
VOL4
Output low voltage in
reset (P2.6 only)
1
V
pF
Ω
IOL4 = TBD
FTEST = 1.0 MHz
(Note 2)
CS
Pin capacitance
10
(any pin to VSS
)
RWPU
NOTES:
Weak pullup resistance
(approximate)
150K
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL
enabled. With the PLL bypassed, the device is tested only down to 8MHz.
2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VREF = VCC = 5.5V.
3.
VIH max for port 0 is VREF + 0.5V.
4. All bidirectional pins when configured as complementary outputs.
5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values
are ± 10 mA.
6. Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
7. All bidirectional pins except P5.1/INST and P2.7/CLKOUT, which are excluded because they are not
weakly pulled low in reset. Bidirectional pins include ports 1–6.
8. This specification is not tested in production and is based upon theoretical estimates and/or product
characterization.
PRODUCT PREVIEW
17
87C196LA — AUTOMOTIVE
5.2 AC Characteristics (Over Specified Operating Conditions)
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FXTAL1 = 8MHz with PLL
enabled in clock-doubler mode.
Table 7. AC Characteristics
Symbol
Parameter
Min
Max
Units
The 87C196LA will meet these specifications
FXTAL1
Frequency on XTAL1, PLL in 1x mode
8.0
4.0
20.0
10.0
(1)
MHz
Frequency on XTAL1, PLL in 2x mode
Operating frequency, f = FXTAL1; PLL in 1x mode
Operating frequency, f = 2FXTAL1; PLL in 2x mode
Period t = 1/f
f
8.0
20.0
MHz
ns
t
50
20
125
110
(2)
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
NOTES:
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
ns
2t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT High Period
t – 10
– 10
– 20
t + 15
15
CLKOUT Falling to ALE Rising
ALE Falling to CLKOUT Rising
ALE Cycle Time
15
4t
ALE High Period
t – 10
t – 15
t – 40
t – 30
4
t + 10
Address Setup to ALE Low
Address Hold after ALE Low
ALE Low to RD# Low
RD# Low to CLKOUT Low
RD# Low to RD# High
30
t – 5
t
(3)
RD# High to ALE Rising
t + 25
5
ns
RD# Low to Address Float
ALE Low to WR# Low
ns
ns
ns
ns
ns
ns
ns
t – 10
– 5
CLKOUT Low to WR# Falling Edge
Data Valid to WR# High
25
15
t – 23
– 10
CLKOUT High to WR# Rising Edge
WR# Low to WR# High
t – 20
t – 25
Data Hold after WR# High
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only
down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
18
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
Table 7. AC Characteristics (Continued)
Symbol
TWHLH
Parameter
WR# High to ALE High
Min
Max
Units
(3)
t – 10
t – 30
t – 30
t + 15
ns
(4)
TWHAX
AD15:8 Hold after WR# High
AD15:8 Hold after RD# High
ns
(4)
TRHAX
ns
NOTES:
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only
down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
Table 8. AC Characteristics
Symbol
Parameter
Min
Max
Units
The system must meet these specifications to work with the 87C196LA
TAVDV
TRLDV
TCLDV
TRHDZ
TRXDX
Address Valid to Input Data Valid
RD# Low to Input Data Valid
CLKOUT Low to Input Data Valid
RD# High to Input Data Float
Data Hold after RD# Inactive
3t – 55
t – 22
t – 50
t
ns
ns
ns
ns
ns
0
Table 9. AC Timing Symbol Definitions
Signal(s)
Character
A
C
D
L
AD15:0
CLKOUT
AD15:0, AD7:0
ALE
Q
R
W
X
AD15:0, AD7:0
RD#
WR#, WRL#
XTAL1
Character
Condition
H
L
High
Low
V
X
Z
Valid
No Longer Valid
Floating (low impedance)
PRODUCT PREVIEW
19
87C196LA — AUTOMOTIVE
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TLLCH
TCLLH
TLHLH
ALE/ADV#
TLHLL
TRHLH
TLLRL
TRLRH
RD#
T
TRLAZ
TLLAX
RHDZ
TAVLL
T
RLDV
Address Out
TAVDV
Data In
AD15:0
(read)
TLLWL
TWHLH
TWLWH
WR#
T
TQVWH
Data Out
WHQX
AD15:0
(write)
Address Out
Address Out
TWHBX, TRHBX
Valid
BHE#, INST
TWHAX, TRHAX
AD15:8
(8-bit data bus)
High Address Out
A3100-02
Figure 4. System Bus Timing
20
PRODUCT PREVIEW
AUTOMOTIVE — 87C196LA
6.0 THERMAL CHARACTERISTICS
7.0 DESIGN CONSIDERATIONS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel Packaging Handbook
(order number 240800) describes Intel’s thermal
impedance test methodology. The Components
Quality and Reliability Handbook (order number
210997) provides quality and reliability information.
To be supplied.
8.0 DEVICE ERRATA
There are no known device errata at this time.
9.0 DATASHEET REVISION HISTORY
Table 10. Thermal Characteristics
This datasheet is valid for devices with an “A” at the
end of the topside field process order (FPO)
number. Datasheets are changed as new device
information becomes available. Verify with your
local Intel sales office that you have the latest
Package Type
θ
θ
JC
JA
AN87C196LA (52-pin PLCC) 42°C/W 15°C/W
NOTES:
version before finalizing
devices.
a
design or ordering
1.
θ
= Thermal resistance between junction
JA
and the surrounding environment (ambient).
Measurements are taken 1 ft. away from
case in static air flow environment.
θ
= Thermal resistance between juction
JC
and package surface (case).
2. All values of θ and θ may fluctuate
JA
JC
depending on the environment (with or with-
out airflow, and how much airflow) and
device power dissipation at temperature of
operation. Typical variations are ± 2°C/W.
3. Values listed are at a maximum power dissi-
pation of 0.50 W.
PRODUCT PREVIEW
21
相关型号：
©2020 ICPDF网 联系我们和版权申明