80960RS [INTEL]
Micro Peripheral IC, PBGA540;
| 型号： | 80960RS |
| 厂家： | 
INTEL |
| 描述： | Micro Peripheral IC, PBGA540 |
| 文件： | 总52页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® 80960RS I/O Processor
■ Complies with PCI Local Bus Specification, Revision 2.2
■ Universal (5 V and 3.3 V) PCI Signalling Environment (C-stepping only)
Data Sheet
Product Features
■ High Performance Intel® 80960JT Core
—Sustained One Instruction/Clock Execution —Connects Internal Bus to 32-bit PCI Buses
■ Two Address Translation Units
—16 Kbyte, Two-Way Set-Associative
Instruction Cache
—Inbound/Outbound Address Translation
Support
—4 Kbyte, Direct-Mapped Data Cache
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1 Kbyte, Internal Data RAM
—Direct Outbound Addressing Support
■ DMA Controller
—Three Independent Channels
—PCI Memory Controller Interface
—64-Bit Internal and PCI Bus Addressing
—Local Register Cache
(Eight Available Stack Frames)
—Independent Interface to 32-bit Primary
and Secondary PCI Buses
—Two 32-Bit On-Chip Timer Units
—132 Mbyte/sec Burst Transfers to PCI and
Local Buses
■ PCI-to-PCI Bridge Unit
—Eight Delayed Read/Write Buffers
Holding up to eight Transactions
—Direct Addressing to/from PCI Buses
—Primary and Secondary 32-bit PCI
Interfaces
—Unaligned Transfers Supported in
Hardware
—Two Posting Buffers Holding up to 12
Transactions
—Two Channels Dedicated to Primary PCI Bus
—One Channel Dedicated to Secondary PCI Bus
■ I2C Bus Interface Unit
—Delayed and Posted Transaction Support
—Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
—Serial Bus
—Master/Slave Capabilities
■ I O Messaging Unit
2
—System Management Functions
■ Secondary PCI Arbitration Unit
—Supports Six Secondary PCI Devices
—Multi-priority Arbitration Algorithm
■ Private PCI Device Support
■ Perimeter Land Grid Array Package
—540-pin
—Four Message Registers
—Two Doorbell Registers
—Four Circular Queues
—1004 Index Registers
■ Memory Controller
—128 Mbytes of 64-Bit SDRAM or
64 Mbytes of 32-Bit SDRAM
■ Performance Monitoring
—ECC Single-Bit error correction,
Double-Bit error detection
—Ninety-eight events monitored on-chip
—Two Independent Banks for SRAM /
ROM / Flash (8 Mbytes/Bank; 8-Bit)
Order Number: 273328-006
August, 2001
Intel® 80960RS I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 80960RS I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
Intel, Intel Solutions960 and Intel i960 are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Data Sheet
Intel® 80960RS I/O Processor
Contents
1.0
2.0
About this Document................................................................................................7
1.1
1.2
1.3
Intel® Solutions960® Program...............................................................................7
Terminology...........................................................................................................7
Additional Information Sources .............................................................................7
Functional Overview.................................................................................................8
2.1
Key Functional Units .............................................................................................9
2.1.1 PCI-to-PCI Bridge Unit .............................................................................9
2.1.2 Private PCI Device Support......................................................................9
2.1.3 DMA Controller.........................................................................................9
2.1.4 Address Translation Unit ..........................................................................9
2.1.5 Messaging Unit.........................................................................................9
2.1.6 Memory Controller Unit ..........................................................................10
2.1.7 I2C Bus Interface Unit ............................................................................10
2.1.8 Secondary PCI Arbitration Unit ..............................................................10
2.1.9 Performance Monitor Unit ......................................................................10
2.1.10 Bus Interface Unit...................................................................................10
i960® Core Features (80960JT) ..........................................................................11
2.2.1 Burst Bus................................................................................................12
2.2.2 Timer Unit...............................................................................................12
2.2.3 Priority Interrupt Controller .....................................................................12
2.2.4 Faults and Debugging ............................................................................12
2.2.5 On-Chip Cache and Data RAM ..............................................................12
2.2.6 Local Register Cache .............................................................................13
2.2.7 Test Features .........................................................................................13
2.2.8 Memory-Mapped Control Registers .......................................................13
2.2.9 Instructions, Data Types and Memory Addressing Modes.....................13
2.2
3.0
Package Information...............................................................................................15
3.1
3.2
3.3
Package Introduction...........................................................................................15
3.1.1 Functional Signal Definitions ..................................................................15
3.1.2 540-Lead H-PBGA Package ..................................................................24
Package Thermal Specifications .........................................................................36
3.2.1 Thermal Specifications ...........................................................................36
3.2.2 Thermal Analysis....................................................................................37
Heat Sink Information..........................................................................................38
3.3.1 Socket Information .................................................................................38
3.3.2 Socket-Header Vendor...........................................................................38
3.3.3 Burn-in Socket Vendor ...........................................................................38
3.3.4 Shipping Tray Vendor.............................................................................39
3.3.5 Logic Analyzer Interposer Vendor ..........................................................39
3.3.6 JTAG Emulator Vendor ..........................................................................39
4.0
Electrical Specifications........................................................................................40
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings.................................................................................40
V
Pin Requirements (V
).....................................................................41
CC5REF
DIFF
V
Pin Requirements ...................................................................................41
CCPLL
Targeted DC Specifications.................................................................................42
Targeted AC Specifications.................................................................................44
Data Sheet
3
Intel® 80960RS I/O Processor
4.5.1 Clock Signal Timings..............................................................................44
4.5.2 PCI Interface Signal Timings..................................................................45
4.5.3 Intel® 80960JN Core Interface Timings..................................................46
4.5.4 SDRAM/Flash Interface Signal Timings.................................................46
4.5.5 Boundary Scan Test Signal Timings ......................................................47
4.5.6 I2C Interface Signal Timings ..................................................................48
AC Timing Waveforms ........................................................................................49
AC Test Conditions .............................................................................................51
4.6
4.7
5.0
Device Identification on Reset............................................................................52
4
Data Sheet
Intel® 80960RS I/O Processor
Figures
1
2
3
4
Intel® 80960RS Processor Functional Block Diagram .................................... 8
80960JT Core Block Diagram ....................................................................... 11
540L H-PBGA Package Diagram (Top and Side View) ................................ 24
540L H-PBGA Package Diagram (Bottom View) .......................................... 25
Thermocouple Attachment - A) No Heatsink / B) With Heatsink ................... 36
5
6
V
Current-Limiting Resistor................................................................ 41
CC5REF
7
V
Lowpass Filter .................................................................................. 41
CCPLL
8
P_CLK, TCK, DCLKIN, DCLKOUT Waveform............................................. 49
9
T
T
T
Output Delay Waveform......................................................................... 49
Output Float Waveform.......................................................................... 50
OV
OF
10
11
12
13
and T Input Setup and Hold Waveform ................................................ 50
IS
IH
I2C Interface Signal Timings.......................................................................... 50
AC Test Load (all signals except SDRAM and Flash signals)....................... 51
Tables
1
2
3
4
5
6
7
8
Related Documentation................................................................................... 7
Instruction Set .............................................................................................. 14
Pin Description Nomenclature....................................................................... 16
Memory Controller Signals............................................................................ 17
Primary PCI Bus Signals ............................................................................... 19
Secondary PCI Arbiter Signals...................................................................... 20
Secondary PCI Bus Signals .......................................................................... 21
Intel® 80960Jx Core Signals and Configuration Straps................................. 22
I2C, JTAG, Core Signals ............................................................................... 23
540-Lead H-PBGA Package — Signal Name Order ..................................... 26
540-Lead H-PBGA Pinout — Ballpad Number Order.................................... 31
540-Lead H-PBGA Package Thermal Characteristics .................................. 37
Heat Sink Vendors and Contacts .................................................................. 38
Socket-Header Vendor.................................................................................. 38
Burn-in Socket Vendor .................................................................................. 38
Shipping Tray Vendor.................................................................................... 39
Logic Analyzer Interposer Vendor ................................................................. 39
JTAG Emulator Vendor ................................................................................. 39
Operating Conditions..................................................................................... 40
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
Specification for Dual Power Supply Requirements (3.3 V, 5 V)......... 41
DIFF
DC Characteristics ........................................................................................ 42
Characteristics ........................................................................................ 43
I
CC
Input Clock Timings....................................................................................... 44
SDRAM Output Clock Timings ...................................................................... 44
PCI Signal Timings....................................................................................... 45
Intel® 80960JN Core Signal Timings............................................................. 46
SDRAM / Flash Signal Timings..................................................................... 46
Boundary Scan Test Signal Timings ............................................................. 47
I2C Interface Signal Timings ......................................................................... 48
Device ID Registers...................................................................................... 52
Data Sheet
5
Intel® 80960RS I/O Processor
This Page Intentionally Left Blank
6
Data Sheet
Intel® 80960RS I/O Processor
1.0
About this Document
®
This is the data sheet for the Intel 80960RS processor. This data sheet contains a functional
overview, mechanical data (package signal locations and simulated thermal characteristics),
targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional
®
descriptions other than parametric performance is published in the i960 RM/RN I/O Processor
Developer’s Manual.
1.1
1.2
Intel® Solutions960® Program
®
®
The Intel Solutions960 program features a wide variety of development tools which support the
i960 processor family. Many of these tools are developed by partner companies; some are
developed by Intel, such as profile-driven optimizing compilers. For more information on these
products, contact your local Intel representative.
Terminology
In this document, the following terms are used:
• Primary and Secondary PCI buses are the 80960RS processor’s external PCI buses which
conform to PCI SIG specifications.
®
®
• Intel 80960 core refers to the Intel 80960JT processor which is integrated into the 80960RS
processor.
1.3
Additional Information Sources
Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales.
Intel Corporation
Literature Sales
P.O. Box 5937
Denver, CO 80217-9808
1-800-548-4725
Table 1.
Related Documentation
Document Title
Order / Contact
i960® RM/RN I/O Processor Developer’s Manual
i960® Jx Microprocessor User’s Guide
i960® RM/RN/RS I/O Processor Specification Update
Intel Order # 273158
Intel Order # 272483
Intel Order # 273164
PCI Special Interest
Group 1-800-433-5177
PCI Local Bus Specification, Revision 2.1
PCI Special Interest
Group 1-800-433-5177
PCI-to-PCI Bridge Architecture Specification, Revision 1.1
I2C Peripherals for Microcontrollers
Tuzigoot Microprocessor EAS
Philips Semiconductor
Intel Order # AZ-0824
Data Sheet
7
Intel® 80960RS I/O Processor
2.0
Functional Overview
As indicated in Figure 1, the 80960RS processor combines many features with the 80960JT to
create an intelligent I/O processor. Subsections following the figure briefly describe the main
®
features; for detailed functional descriptions, refer to the i960 RM/RN I/O Processor Developer’s
Manual.
The PCI bus is an industry standard, high performance, low latency system bus that operates up to
264 Mbyte/s. The 80960RS processor, a multi-function PCI device, is fully compliant with the PCI
Local Bus Specification, Revision 2.2. Function 0 is the PCI-to-PCI bridge unit; Function 1 is the
address translation unit.
The PCI-to-PCI bridge unit is the path between two independent 64-bit PCI buses and provides the
®
®
ability to overcome PCI electrical load limits. The addition of the Intel i960 core processor
brings intelligence to the bridge.
The 80960RS processor, object code compatible with the i960 core processor, is capable of
sustained execution at the rate of one instruction per clock.
The internal bus, a 64-bit PCI-like bus, is a high-speed interface to local memory and I/O. Physical
and logical memory attributes are programmed via memory-mapped control registers (MMRs); an
®
®
extension not found on the Intel i960 Kx, Sx or Cx processors.
®
Figure 1.
Intel 80960RS Processor Functional Block Diagram
Local Memory
(SDRAM, Flash)
I2C Serial Bus
80960RS Processor
80960 Core
Processor
Memory
Controller
2
Bus
Interface
I C Bus
Internal
Arbitration
Interface
64-bit Internal Bus
Messaging
Unit
Two DMA
Channels
Address
Translation
One DMA
Channel
Address
Translation
PCI to PCI
Bridge
32-bit Primary PCI Bus
32-bit Secondary PCI Bus
Performance
Monitoring
Unit
Secondary PCI
Arbitration Unit
8
Data Sheet
Intel® 80960RS I/O Processor
2.1
Key Functional Units
2.1.1
PCI-to-PCI Bridge Unit
The PCI-to-PCI bridge unit (referred to as “bridge”) connects two independent PCI buses. Each
PCI bus is 32 bits wide. The bridge is fully compliant with the PCI-to-PCI Bridge Architecture
Specification, Revision 1.1 published by the PCI Special Interest Group. The bridge forwards bus
transactions on one PCI bus to the other PCI bus. Dedicated data queues support high performance
bandwidth on the PCI buses. The 80960RS supports PCI 64-bit Dual Address Cycle (DAC)
addressing.
The bridge has dedicated PCI configuration space accessible through the primary PCI bus.
2.1.2
2.1.3
2.1.4
Private PCI Device Support
The 80960RS processor explicitly supports private PCI devices on the secondary PCI bus. The
bridge and Address Translation Unit work together to hide private PCI devices from PCI
configuration cycles and allow these hidden devices to use a private PCI address space. The
Address Translation Unit issues PCI configuration cycles to configure hidden devices.
DMA Controller
The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents
and local memory. Three separate DMA channels accommodate data transfers: two for primary
PCI bus, one for the secondary PCI bus. The DMA Controller supports chaining and unaligned
data transfers. The DMA Controller is programmable only through the i960 core processor.
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to local memory. The
80960RS processor has direct access to both PCI buses. The ATU supports transactions between
PCI address space and 80960RS processor address space.
Address translation is controlled through programmable registers accessible from both the primary
PCI interface and the 80960 core. Dual access to registers allows flexibility in mapping the two
address spaces.
2.1.5
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the 80960RS
processor. The Messaging Unit uses interrupts to notify the PCI system or the 80960RS processor
when new data arrives. The MU has four messaging mechanisms: Message Registers, Doorbell
Registers, Circular Queues, and Index Registers. Each mechanism allows a host processor or
external PCI device and the 80960RS processor to communicate through message passing and
interrupt generation.
Data Sheet
9
Intel® 80960RS I/O Processor
2.1.6
2.1.7
Memory Controller Unit
The Memory Controller Unit (MCU) allows direct control of a local SDRAM and Flash subsystem.
The MCU features programmable chip selects, a wait state generator and Error Correction and
Detection. With the ATU configuration registers, local memory can be configured as PCI
addressable memory or private processor memory.
I2C Bus Interface Unit
2
The I C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and
2
2
slave device residing on the I C bus. The I C bus is a serial bus developed by Philips
Semiconductor comprising a two pin interface. The bus allows the 80960RS processor to interface
2
to other I C peripherals and microcontrollers for system management functions. It requires a
minimum of hardware for an economical system to relay status and reliability information on the
2
I/O subsystem to an external device. For more information, see I C Peripherals for
Microcontrollers (Philips Semiconductor).
2.1.8
2.1.9
2.1.10
Secondary PCI Arbitration Unit
The Secondary PCI Arbitration Unit provides PCI arbitration for the secondary PCI bus. The
arbitration includes a fairness algorithm with programmable priorities and six external PCI Request
and Grant signal pairs.
Performance Monitor Unit
The Performance Monitor Unit (PMU) allows software to monitor the performance of the different
buses: Primary PCI, Secondary PCI, and Internal. Multiple performance characteristics are
captured with 14 mode registers and a global time stamp register.
Bus Interface Unit
The Bus Interface Unit (BIU) provides an interface between the 100 MHz 80960JT core and the
66 MHz internal bus. To optimize performance, the BIU implements prefetching and write merging.
10
Data Sheet
Intel® 80960RS I/O Processor
2.2
i960® Core Features (80960JT)
The processing power of the 80960RS processor comes from the 100 MHz 80960JT processor
core. The 80960JT is a scalar implementation of the 80960 Core Architecture. Figure 2 shows a
block diagram of the 80960JT Core processor.
Factors that contribute to the 80960JT core’s performance include:
• 100 MHz Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline break latency
• Register and resource scoreboarding allow overlapped instruction execution
• 128-bit register bus speeds local register caching
• 16 Kbyte, two-way set-associative, integrated instruction cache
• 4 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait state program data
The 80960 core operates out of its own 32-bit address space, which is independent of the PCI
address space. Local memory can be:
• Made visible to the PCI address space
• Kept private to the 80960JT core
• Allocated as a combination of the two
Figure 2.
80960JT Core Block Diagram
Control
32-bit buses
address / data
Physical Region
Configuration
P_CLK
PLL, Clocks,
Power Mgmt
Bus
Control Unit
Instruction Cache
16 Kbyte Two-Way
Associative
Address/
Data Bus
Bus Request
Queues
TAP
5
Boundary Scan
Controller
32
Instruction Sequencer
Two 32-Bit
Timers
Constants
Control
Interrupt
Port
Programmable
Interrupt Controller
8-Set
Local Register
Cache
9
Execution
and
Memory
Interface
Unit
Memory-Mapped
Register Interface
Multiply
Divide
Unit
Address
Generation
Unit
128
1 Kbyte
32-bit Addr
32-bit Data
Effective
Address
Global / Local
Register File
Data RAM
SRC1 SRC2
DST
4 Kbyte
Direct Mapped
Data Cache
3 Independent 32-Bit SRC1, SRC2, and DST Buses
Data Sheet
11
Intel® 80960RS I/O Processor
2.2.1
Burst Bus
A 32-bit high-performance bus controller interfaces the 80960RS processor to the Bus Interface
Unit. The Bus Control Unit fetches instructions and transfers data on the internal bus at the rate of
up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed.
Data caching is programmed through a group of logical memory templates and a defaults register.
The Bus Control Unit’s features include:
• Multiplexed external bus minimizes pin count
• External ready control for address-to-data, data-to-data and data-to-next-address wait state types
• Little endian byte ordering
• Unaligned bus accesses performed transparently
• Three-deep load/store queue decouples the bus from the 80960 core
Upon reset, the 80960JT conducts an internal self test. Before executing its first instruction, it performs an
external bus confidence test by performing a checksum on the first words of the Initialization Boot Record.
2.2.2
2.2.3
2.2.4
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed through the Timer Unit registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960JT’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected.
Priority Interrupt Controller
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960JT exploits several techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can be reserved on-chip
• Register frames for high-priority interrupt handlers can be cached on-chip
• The interrupt stack can be placed in cacheable memory space
Faults and Debugging
The 80960JT employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. With software, the 80960JT may be configured
to detect as many as seven different trace event types. Alternatively, mark and fmark instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.2.5
On-Chip Cache and Data RAM
Memory subsystems often impose substantial wait state penalties. The 80960JT integrates
considerable storage resources on-chip to decouple CPU execution from the external bus. The
80960JT includes a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM.
12
Data Sheet
Intel® 80960RS I/O Processor
2.2.6
2.2.7
Local Register Cache
The 80960JT rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.
Test Features
The 80960RS processor incorporates numerous features that enhance the user’s ability to test both
the processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960JT provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE
mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960RS processor to
electrically “remove” itself from a circuit board allowing system-level testing where a remote
tester can exercise the processor system.
The test logic does not interfere with component or system behavior and ensures that components
function correctly and the connections between various components are correct.
The JTAG Boundary Scan feature is an alternative to conventional “bed-of-nails” testing.
Boundary Scan can examine connections that might otherwise be inaccessible to a test system.
2.2.8
2.2.9
Memory-Mapped Control Registers
The 80960JT is compliant with 80960 family architecture. Each memory-mapped, 32-bit register is
accessed via memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.
Instructions, Data Types and Memory Addressing Modes
As with all 80960 family processors, the instruction set supports several different data types and formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960JT provides a full set of addressing modes for C and assembly:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement mode
• IP with displacement mode
Data Sheet
13
Intel® 80960RS I/O Processor
Table 2 shows the available 80960JT instructions.
Instruction Set
Table 2.
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Add
Subtract
Multiply
And
Set Bit
Divide
Not And
And Not
Or
Clear Bit
Remainder
Not Bit
Load
Modulo
Alter Bit
Store
Shift
Exclusive Or
Not Or
Scan For Bit
Span Over Bit
Extract
Move
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Conditional Add
Conditional Subtract
Rotate
Conditional Select
Load Address
Or Not
Nor
Modify
Exclusive Nor
Not
Scan Byte for Equal
Byte Swap
Nand
Comparison
Branch
Call/Return
Fault
Compare
Call
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call Extended
Call System
Return
Conditional Fault
Synchronize Faults
Branch and Link
Processor
Management
Debug
Atomic
Flush Local Registers
Modify Arithmetic
Controls
Modify Trace Controls
Mark
Modify Process Controls
Halt
Atomic Add
Atomic Modify
Force Mark
System Control
Cache Control
Interrupt Control
14
Data Sheet
Intel® 80960RS I/O Processor
3.0
Package Information
3.1
Package Introduction
The 80960RS processor is offered in a Perimeter Land Grid Array (PBGA) package. This is a
perimeter array package with five rows of ball connections in the outer area of the package. See
Figure 4 “540L H-PBGA Package Diagram (Bottom View)” on page 25.
3.1.1
Functional Signal Definitions
This section defines the pins and signals in the following tables:
• Table 3 “Pin Description Nomenclature” on page 16
• Table 4 “Memory Controller Signals” on page 17
• Table 5 “Primary PCI Bus Signals” on page 19
• Table 6 “Secondary PCI Arbiter Signals” on page 20
• Table 8 “Intel® 80960Jx Core Signals and Configuration Straps” on page 22
• Table 9 “I2C, JTAG, Core Signals” on page 23
Data Sheet
15
Intel® 80960RS I/O Processor
3.1.1.1
Table 3.
Signal Pin Description
Pin Description Nomenclature
SYMBOL
DESCRIPTION
I
Input pin only
O
Output pin only
I/O
OD
-
Pin can be either an input or output
Open Drain pin
Pin must be connected as described
N/C
5V
NO CONNECT. Do not make electrical connections to these balls.
Input pin is 5 volt tolerant
Synchronous. Inputs meet setup and hold times relative to an input clock.
Sync(P) Synchronous to P_CLK
Sync(D) Synchronous to DCLKIN
Sync(...)
Async
Sync(T) Synchronous to TCK
Asynchronous. Inputs may be asynchronous relative to P_CLK, DCLKIN, or TCK. All
asynchronous signals are level-sensitive.
While the P_RST# pin is asserted, the pin:
Prst(1) Is driven to VCC
Prst(0) Is driven to VSS
Prst(X) Is driven to unknown state
Prst(H) Is pulled up to VCC
Prst(L) Is pulled down to VSS
Prst(Z) Floats
Prst(...)
Prst(Q) Is a valid output
Since P_RST# is asynchronous, these are asynchronous events.
While the S_RST# pin is asserted, the pin:
Srst(1) Is driven to VCC
Srst(0) Is driven to VSS
Srst(X) Is driven to unknown state
Srst(H) Is pulled up to VCC
Srst(L) Is pulled down to VSS
Srst(Z) Floats
Srst(...)
Srst(Q) Is a valid output
Note that S_RST# is asserted when P_RST# is asserted or BCR[6] is set with software.
While the I_RST# pin is asserted, the pin:
Irst(...)
Irst(1) Is driven to VCC
Irst(0) Is driven to VSS
Irst(X) Is driven to unknown state
Irst(H) Is pulled up to VCC
Irst(L) Is pulled down to VSS
Irst(Z) Floats
Irst(Q) Is a valid output
Note that I_RST# is asserted when P_RST# is asserted or EBCR[5] is set with software.
16
Data Sheet
Intel® 80960RS I/O Processor
Table 4.
Memory Controller Signals (Sheet 1 of 2)
NAME
COUNT
TYPE
DESCRIPTION
O
Irst(Q)
DCLKOUT
1
SDRAM OUTPUT CLOCK dedicated for SDRAM memory subsystem.
SDRAM INPUT CLOCK dedicated for SDRAM memory subsystem.
Skews DCLKOUT appropriately to accommodate flight time and clock
buffer delays.
DCLKIN
1
I
O
SDRAM MULTIPLEXED ADDRESS BUS carries multiplexed row and
SA[11:0]
SBA[1:0]
SRAS#
12
2
Irst(Q) column addresses to SDRAM memory banks. For SA[10], see note 1.
SDRAM INTERNAL BANK SELECT indicates which of the SDRAM
Irst(Q) internal banks are read or written during the current transaction.
O
O
Irst(1)
SDRAM ROW ADDRESS STROBE indicates the presence of a valid
row address on the Multiplexed Address Bus SA[11:0]. See note 1.
1
O
Irst(1)
SDRAM COLUMN ADDRESS STROBE indicates the presence of a valid
column address on the Multiplexed Address Bus SA[11:0]. See note 1.
SCAS#
1
SDRAM DATA MASK controls which eight bytes on data bus are written
or read. When SDQM[7:0] asserted, the SDRAM devices do not accept
or drive valid data from/to the byte lanes. When SDQM[7:0] deasserted,
the SDRAM devices accept/drive valid data from/to the byte lanes.
O
Irst(1)
SDQM[7:0]
8
By convention, SDQM[1] masks two x8 SDRAM devices. Functionally,
all SDQM[7:0] signals are equivalent.
O
Irst(1)
SDRAM WRITE ENABLE indicates that the current memory
transaction is a write operation. See note 1.
SWE#
1
2
2
O
Irst(1)
SDRAM CHIP ENABLE enables the SDRAM devices for a memory
access (1 per bank supported). See note 1.
SCE[1:0]#
SCKE[1:0]
O
SCKE[1:0] are the clock enables for the SDRAM memory.
Irst(Q) Deasserting will place the SDRAM in self-refresh mode. See note 1.
DATA BUS carries 64-bit data to/from memory. During a data (T ) cycle,
d
I/O
RW data is present on one or more contiguous bytes, comprising
DQ[63:0]
64
Irst(1)
DQ[63:56], DQ[55:48], DQ[47:40], DQ[39:32], DQ[31:24], DQ[23:16],
Sync(D) DQ[15:8] and DQ[7:0]. During write operations, unused pins are driven to
determinate values.
I/O
Irst(1)
Sync(D)
ERROR CORRECTION CODE carries the 8-bit ECC code to and
from memory during data cycles.
SCB[7:0]
ROE#
8
1
1
ROM OUTPUT ENABLE specifies during a TA cycle, whether operation
is a write or read to ROM interface. It remains valid during TD cycles.
When ROE# is asserted, data is transferred from memory on RAD[16:9].
O
Irst(1)
ROM WRITE ENABLE indicates direction data is to be transferred
to/from ROM and controls the ROM device WE input. When RWE# is
asserted, the data is transferred to the memory on DQ[7:0].
O
Irst(1)
RWE#
O
Irst(1)
FLASH CHIP ENABLE enables the Flash devices for a memory
access.
RCE[1:0]#
RALE
2
1
O
Irst(0)
ROM ADDRESS LATCH ENABLE indicates cycle in which the address
on RAD[16:3] should be externally latched for the Flash subsystem.
I/O
5V
Irst(X)
Sync(D)
FLASH ADDRESS/DATA BUS: During an address (Ta) cycle, bits
16:9 contain a physical word address. During a data cycle (Td), bits
16:9 carry data bits 16:9 of the Flash data byte.
RAD[16:9]
RAD[8]
8
1
1
FLASH ADDRESS BUS: During address (Ta) cycle, bit 8 contains a
physical word address. RAD[8]. multiplexes physical address bits [22]
with [8]. Refer to the MCU chapter of the i960® RM/RN I/O Processor
Developer’s Manual for details.
O
Prst(H)
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 7 contain a
physical word address. RAD[7]. multiplexes physical address bits [21]
with [7]. Refer to the MCU chapter of the i960® RM/RN I/O Processor
Developer’s Manual for details.
O
RAD[7]
Prst(H)
Data Sheet
17
Intel® 80960RS I/O Processor
Table 4.
Memory Controller Signals (Sheet 2 of 2)
NAME
COUNT
TYPE
DESCRIPTION
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 6 contain a
physical word address. RAD[6]. multiplexes physical address bits [20]
with [6]. Within four clocks after the deassertion of P_RST#, this pin is
an output only. Refer to the MCU chapter of the i960® RM/RN I/O
Processor Developer’s Manual for details.
RAD[6]/
I/O
5V
RST_MODE#
1
Prst(H)
RESET MODE is sampled at Primary PCI bus reset to determine if
the 80960RS processor is to be held in reset. If asserted, the
80960RS processor will be held in reset until the 80960 Processor
Reset bit is cleared in the Extended Bridge Control Register.
(Config. Pin)
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 5 contain a
physical word address. RAD[5]. multiplexes physical address bits [19]
with [5]. Within four clocks after the deassertion of P_RST#, this pin is
an output only. Refer to the MCU chapter of the i960® RM/RN I/O
Processor Developer’s Manual for details.
O
RAD[5]
1
Prst(H)
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 4 contain a
physical word address. RAD[4]. multiplexes physical address bits [18]
with [4]. Within four clocks after the deassertion of P_RST#, this pin is
an output only. Refer to the MCU chapter of the i960® RM/RN I/O
Processor Developer’s Manual for details.
RAD[4]/
I/O
5V
Prst(H)
SELF TEST enables or disables the processor’s internal self-test
feature at initialization. STEST is examined at the end of P_RST#.
When STEST is asserted, the processor performs its internal self-test
and the external bus confidence test. When STEST is deasserted, the
processor performs only the external bus confidence test.
0 = Self Test Disabled
STEST
1
(Config. Pin)
1 = Self Test Enabled
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 3 contain a
physical word address. RAD[3]. multiplexes physical address bits [17]
with [3]. Within four clocks after the deassertion of P_RST#, this pin is
an output only. Refer to the MCU chapter of the i960® RM/RN I/O
Processor Developer’s Manual for details.
RAD[3]/
I/O
5V
Prst(H)
RETRY
1
RETRY is sampled at Primary PCI bus reset to determine if the
Primary PCI interface will be disabled. If high, the Primary PCI
interface will disable PCI configuration cycles by signaling a Retry
until the Configuration Cycle Retry bit is cleared in the Extended
Bridge Control Register. If low, the Primary PCI interface allow
configuration cycles to occur.
(Config. Pin)
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 2 contains
a physical word address. Within four clocks after the deassertion of
P_RST#, this pin is an output only. Refer to the MCU chapter of the
i960® RM/RN I/O Processor Developer’s Manual for details.
RAD[2]/
32-BIT Memory Enable The 32BITMEM_EN# signal is sampled at
Primary PCI Reset to notify the memory controller if 32-bit wide
SDRAM memories are connected to the memory controller.
I/O
5V
Prst(H)
32BITMEM_EN#
(Config. Pin)
1
If 32BITMEM_EN# is high, the memory controller supports the 64-bit
SDRAM protocol for accesses to SDRAM memories.
If 32BITMEM_EN# is low, the memory controller supports the 32-bit
SDRAM protocol for accesses to SDRAM memories.
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 1 contains
a physical word address. Within four clocks after the deassertion of
P_RST#, this pin is an output only. Refer to the MCU chapter of the
i960® RM/RN I/O Processor Developer’s Manual for details.
I/O
5V
Prst(H)
RAD[1]
1
1
O
FLASH ADDRESS BUS: During an address (Ta) cycle, bit 0 contains
a physical word address. Refer to the MCU chapter of the i960®
Prst(H) RM/RN I/O Processor Developer’s Manual for details.
RAD[0]
NOTE:
1. These pins remain functional for 20 DCLKIN periods after I_RST# is asserted for a warm boot. The designated
Irst() state applies after 20 DCLKIN periods after I_RST# is asserted. For more details, see MCU Chapter 8.
18
Data Sheet
Intel® 80960RS I/O Processor
Table 5.
Primary PCI Bus Signals (Sheet 1 of 2)
NAME
COUNT
TYPE
DESCRIPTION
I/O
5V
Sync(P)
Prst(Z)
P_AD[31:0]
32
PRIMARY PCI ADDRESS/DATA is the multiplexed primary PCI bus.
I/O
5V
PRIMARY PCI BUS PARITY is even parity across P_AD[31:0] and
P_PAR
1
Sync(P) P_C/BE[3:0]#.
Prst(Z)
I/O
5V
PRIMARY PCI BUS COMMAND and BYTE ENABLES are multiplexed
on the same PCI pins. During the address phase, they define the bus
P_C/BE[3:0]#
P_REQ#
4
1
1
Sync(P) command. During the data phase, they are used as byte enables for
Prst(Z) P_AD[31:0].
O
PRIMARY PCI BUS REQUEST indicates to the primary PCI bus arbiter
Prst(Z) that the 80960RS processor desires use of the PCI bus.
I
5V
PRIMARY PCI BUS GRANT indicates that access to the primary PCI
P_GNT#
Sync(P) bus has been granted.
Prst(Z)
I/O
5V
PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the
P_FRAME#
P_IRDY#
1
1
1
Sync(P) beginning and duration of an access.
Prst(Z)
I/O
5V
PRIMARY PCI BUS INITIATOR READY indicates the initiating agent’s
ability to complete the current data phase of the transaction. During a
Sync(P) write, it indicates that valid data is present on the Address/Data bus.
Prst(Z) During a read, it indicates the processor is ready to accept the data.
I/O
5V
PRIMARY PCI BUS TARGET READY indicates the target agent’s ability
to complete the current data phase of the transaction. During a read, it
P_TRDY#
Sync(P) indicates that valid data is present on the Address/Data bus. During a
Prst(Z) write, it indicates the target is ready to accept the data.
I/O
5V
Sync(P)
PRIMARY PCI BUS STOP indicates a request to stop the current
transaction on the primary PCI bus.
P_STOP#
1
1
Prst(Z)
I/O
5V
Sync(P)
PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that
has successfully decoded the address. As an input, it indicates whether
or not an agent has been selected.
P_DEVSEL#
Prst(Z)
I/O
5V
OD
PRIMARY PCI BUS SYSTEM ERROR is driven for address parity errors
on the primary PCI bus.
P_SERR#
P_CLK
1
1
Sync(P)
Prst(Z)
I
PRIMARY PCI BUS INPUT CLOCK provides the timing for all primary
PCI transactions and is the clock source for all internal 80960RS units.
5V
Data Sheet
19
Intel® 80960RS I/O Processor
Table 5.
Primary PCI Bus Signals (Sheet 2 of 2)
NAME
COUNT
TYPE
DESCRIPTION
PRIMARY RESET brings PCI-specific registers, sequencers, and signals
to a consistent state. When P_RST# is asserted:
PCI output signals are driven to a known consistent state.
PCI bus interface output signals are three-stated.
open drain signals such as P_SERR# are floated.
I
P_RST#
1
5V
Async
P_RST# may be asynchronous to P_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
I/O
5V
PRIMARY PCI BUS PARITY ERROR is asserted when a data parity
P_PERR#
1
Sync(P) error occurs during a primary PCI bus transaction.
Prst(Z)
I
PRIMARY PCI BUS LOCK indicates the need to perform an atomic
operation on the primary PCI bus.
P_LOCK#
P_IDSEL
1
1
5V
Sync(P)
I
PRIMARY PCI BUS INITIALIZATION DEVICE SELECT is used to select
the 80960RS processor during a Configuration Read or Write command
5V
Sync(P) on the primary PCI bus.
PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion
and deassertion of P_INT[A:D]# is asynchronous to P_CLK. A device
asserts its P_INT[A:D]# line when requesting attention from its device
driver. Once the P_INT[A:D]# signal is asserted, it remains asserted until
the device driver clears the pending request. P_INT[A:D]# Interrupts are
level sensitive.
O
OD
Prst(Z)
P_INT[A:D]#
4
Table 6.
Secondary PCI Arbiter Signals
NAME
COUNT
TYPE
DESCRIPTION
I
SECONDARY PCI BUS REQUESTS are the request signals from
devices 0 through 5 on the secondary PCI bus.
S_REQ[5:0]#
6
5V
Sync(P)
O
SECONDARY PCI BUS GRANT are grant signals sent to devices 5-0 on
S_GNT[5:0]#
6
Srst(Z) the secondary PCI bus
20
Data Sheet
Intel® 80960RS I/O Processor
Table 7.
Secondary PCI Bus Signals
NAME
COUNT
TYPE
DESCRIPTION
I/O
5V
Sync(P)
Srst(0)
S_AD[31:0]
32
SECONDARY PCI ADDRESS/DATA is the multiplexed secondary PCI bus.
I/O
Sync(P)
Srst(0)
SECONDARY PCI BUS PARITY is even parity across S_AD[31:0] and
S_C/BE[3:0]#.
S_PAR
1
4
I/O
5V
SECONDARY PCI BUS COMMAND and BYTE ENABLES are
multiplexed on the same PCI pins. During the address phase, they define
S_C/BE[3:0]#
Sync(P) the bus command. During the data phase, they are used as the byte
Srst(0) enables for S_AD[31:0].
I/O
5V
SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the
S_FRAME#
S_IRDY#
1
1
1
Sync(P) beginning and duration of an access.
Srst(Z)
I/O
5V
SECONDARY PCI BUS INITIATOR READY indicates the initiating agent’s
ability to complete the current data phase of the transaction. During a write,
Sync(P) it indicates that valid data is present on the secondary Address/Data bus.
Srst(Z) During a read, it indicates the processor is ready to accept the data.
I/O
5V
SECONDARY PCI BUS TARGET READY indicates the target agent’s
ability to complete the current data phase of the transaction. During a read,
S_TRDY#
Sync(P) it indicates that valid data is present on the secondary Address/Data bus.
Srst(Z) During a write, it indicates the target is ready to accept the data.
I/O
5V
Sync(P)
SECONDARY PCI BUS STOP indicates a request to stop the current
transaction on the secondary PCI bus.
S_STOP#
1
1
Srst(Z)
I/O
5V
Sync(P)
SECONDARY PCI BUS DEVICE SELECT is driven by a target agent
that has successfully decoded the address. As an input, it indicates
whether or not an agent has been selected.
S_DEVSEL#
Srst(Z)
I/O
5V
OD
Sync(P)
Srst(Z)
SECONDARY PCI BUS SYSTEM ERROR is driven for address parity
errors on the secondary PCI bus.
S_SERR#
1
1
SECONDARY PCI BUS RESET is an output based on P_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent state. When
P_RST# is asserted or BCR[6] is set, it causes S_RST# to assert and:
PCI output signals are driven to a known consistent state.
PCI bus interface output signals are three-stated.
open drain signals such as S_SERR# are floated
O
Async
S_RST#
S_RST# may be asynchronous to P_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
I/O
5V
SECONDARY PCI BUS PARITY ERROR is asserted when a data parity
S_PERR#
S_LOCK#
1
1
Sync(P) error during a secondary PCI bus transaction.
Srst(Z)
I/O
5V
SECONDARY PCI BUS LOCK indicates the need to perform an atomic
Sync(P) operation on the secondary PCI bus.
Srst(Z)
Data Sheet
21
Intel® 80960RS I/O Processor
®
Table 8.
Intel 80960Jx Core Signals and Configuration Straps
NAME
COUNT
TYPE
DESCRIPTION
SECONDARY PCI BUS INTERRUPT REQUESTS. S_INT[D:A]#
assertion and deassertion is asynchronous to P_CLK. As device asserts
S_INT[D:A]# when requesting attention from it device driver. When
S_INT[D:A]# is asserted, it remains asserted until the device driver clears
the pending request. S_INT[D:A]# interrupts are level low sensitive.
EXTERNAL INTERRUPT. External devices use this signal to request an
interrupt service. These signals operate in dedicated mode, where each
signal is assigned a dedicated interrupt level.
I
XINT[3:0]#/
S_INT[D:A]#
4
5V
Async The S_INT[D:A]#/XINT[3:0]# signals can be directed as follows:
Sec. PCIPrimary PCIi960 core processor
S_INTA# P_INTA# or XINT0#
S_INTB# P_INTB# or XINT1#
S_INTC# P_INTC# or XINT2#
S_INTD# P_INTD# or XINT3#
I
EXTERNAL INTERRUPT pins are used to request 80960RS processor
interrupt service.
XINT[5:4]#
2
5V
Async
I
NON-MASKABLE INTERRUPT causes an i960 core processor
non-maskable interrupt event to occur. NMI# is the highest priority
NMI#
1
1
5V
Async interrupt source.
INPUT REFERENCE VOLTAGE is strapped to 5V. This reference
voltage allows the 80960RS processor input pins to be 5V tolerant.
VCC5REF
-
-
PLL POWER is a separate VCC supply pin for the phase lock loop clock
generator. It is intended for external connection to the VCC board plane.
In noisy environments, add a simple bypass filter circuit to reduce
noise-induced clock jitter and its effects on timing relationships.
VCCPLL
3
FAIL indicates a failure of the processor’s built-in self-test performed
during initialization. FAIL# is asserted immediately upon reset and
toggles during self-test to indicate the status of individual tests:
When self-test passes, the processor deasserts FAIL# and commences
operation from user code.
O
Irst(0)
FAIL#
1
When self-test fails, the processor asserts FAIL# and then stops
executing. Self-test failing does not cause the bridge to stop execution.
0 = Self Test Failed
1 = Self Test Passed
22
Data Sheet
Intel® 80960RS I/O Processor
2
Table 9.
I C, JTAG, Core Signals
NAME
COUNT
TYPE
DESCRIPTION
TEST CLOCK is an input which provides the clocking function for the
IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data
are clocked into the component on the rising edge and data is clocked
out of the component on the falling edge.
I
TCK
1
5V
TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is
sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR
states of the Test Access Port. This signal has a weak internal pull-up to
ensure proper operation when this signal is unconnected.
I
TDI
1
1
1
5V
Sync(T)
TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO
is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR
states of the Test Access Port. At other times, TDO floats.
TDO
TRST#
O
TEST RESET asynchronously resets the Test Access Port (TAP)
controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This
signal has a weak internal pull-up to ensure proper operation when this
signal is unconnected.
I
5V
Async
TEST MODE SELECT is sampled at the rising edge of TCK to select the
operation of the test logic for IEEE 1149.1 Boundary Scan testing. This
signal has a weak internal pull-up to ensure proper operation when this
signal is unconnected.
I
TMS
SDA
SCL
1
1
1
5V
Sync(T)
I/O
5V
OD
I2C DATA is used for data transfer and arbitration on the I2C bus.
I2C CLOCK provides synchronous operation of the I2C bus.
Irst(Z)
I/O
5V
OD
Irst(Z)
LCD INITIALIZATION is a static signal used to initialize the internal logic
for the LCD960 debugger. This signal has an internal pull-up for normal
operation.
I
LCDINIT#
I_RST#
1
1
Sync(I)
O
INTERNAL BUS RESET indicates when the internal bus has been reset
Async with P_RST# or a software reset.
ONCE MODE: The processor samples this pin during reset. If it is
asserted LOW at the end of reset, the processor enters ONCE Mode. In
80960RS processor Mode, the processor stops all clocks and floats all
output pins except the TDO and RAD[8:0] pins. The pin has a weak
internal pull-up which is active during reset to ensure normal operation if
the pin is left unconnected.
ONCE#
I
1
5V
(Config. Pin)
Data Sheet
23
Intel® 80960RS I/O Processor
3.1.2
540-Lead H-PBGA Package
Figure 3.
540L H-PBGA Package Diagram (Top and Side View)
Pin #1 Corner
27.700
42.500 ± 0.200
GC80960RS100
SSSSSS
MALAY
FFFFFFFF-[{SN}]
M
© ‘98
INTEL
27.700
42.500 ± 0.200
Slug
1.56 REF
0.55 ± 0.15
Seating Plane
Ball spacing is 1.270
Ball width is 0.750 ± 0.150
1.025 ± 0.075
3.845 ± 0.255
2.150 ± 0.150
NOTES:
1. All dimensions and tolerances conform to ANSI Y14.5M 1982.
2. Dimensions are measured at the maximum solder ball diameter parallel to primary datum.
3. Primary datum and seating plane are defined by the spherical crowns of the solder balls.
4. All dimensions are in millimeters.
24
Data Sheet
Intel® 80960RS I/O Processor
Figure 4.
540L H-PBGA Package Diagram (Bottom View)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AM
AL
AK
AJ
AM
AL
AK
AJ
AH
AG
AF
AH
AG
AF
AE
AD
AE
AD
AC
AB
AA
Y
AC
AB
AA
Y
W
V
W
V
U
U
T
T
R
R
P
P
N
N
M
L
M
L
K
K
J
J
H
H
G
F
G
F
E
E
D
D
C
B
A
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Data Sheet
25
Intel® 80960RS I/O Processor
Table 10.
540-Lead H-PBGA Package — Signal Name Order (Sheet 1 of 5)
Signal
Ball #
Signal
Ball #
Signal
Ball #
DCLKIN
DCLKOUT
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
E21
A22
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
FAIL#
LCDINIT#
I_RST#
ONCE#
NMI#
C24
E24
P_AD03
P_AD04
P_AD05
P_AD06
P_AD07
P_AD08
P_AD09
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
N/C
T1
T3
T4
T5
R1
R3
R5
P1
P3
P4
P5
N1
N2
K3
K4
K5
J1
D22
B25
A23
E25
C23
C26
A27
A24
D24
C27
A28
A25
C25
G32
H31
H28
J30
A26
E26
B27
E27
J28
C28
W28
Y31
H32
H30
Y28
J32
AA30
AA28
AB31
AB28
AC30
AC28
AD31
AD28
AE30
AE28
AF31
AF28
AH32
E12
J29
J2
W29
Y32
J3
J5
Y30
H1
H5
G1
G2
G3
E5
A6
C6
D6
A16
G5
U5
V1
V3
V4
V5
V28
AA32
AA29
AB32
AB30
AC32
AC29
AD32
AD30
AE32
AE29
AF32
AF30
AG32
E22
A21
N/C
A11
N/C
C21
A9
N/C
N/C
P_AD00
P_AD01
P_AD02
U1
N/C
B23
U2
N/C
E23
U3
N/C
26
Data Sheet
Intel® 80960RS I/O Processor
Table 10.
540-Lead H-PBGA Package — Signal Name Order (Sheet 2 of 5)
Signal
Ball #
Signal
Ball #
Signal
Ball #
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
W1
W2
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
AH4
AH6
N/C
P_CLK
AM13
C20
R2
W3
AH7
P_C/BE0#
P_C/BE1#
P_C/BE2#
P_C/BE3#
P_DEVSEL#
P_FRAME#
P_GNT#
P_IDSEL
P_INTA#
P_INTB#
P_INTC#
P_INTD#
P_IRDY#
P_LOCK#
P_PAR
W5
AH8
N5
Y1
AH9
K1
Y3
AH10
AH11
AH12
AH13
AJ2
H4
Y4
L1
Y5
L5
AA1
AA2
AA3
AA5
AB1
AB3
AB4
AB5
AC1
AC2
AC3
AC5
AD1
AD3
AD4
AD5
AE1
AE2
AE3
AE5
AF1
AF3
AF4
AF5
AG1
AG2
AG3
AH1
AH3
A7
H3
AJ5
E8
AJ7
D8
AJ9
E7
AJ11
AJ13
AK5
C7
L3
M4
N3
AK6
AK7
P_PERR#
P_SERR#
P_STOP#
P_REQ#
P_RST#
P_TRDY#
RAD00
M3
M1
M5
E6
AK8
AK9
AK10
AK11
AK12
AK13
AL6
B7
L2
A13
B13
C13
E13
A14
C14
D14
E14
A15
C15
E15
E17
A18
C18
RAD01
AL8
RAD02
AL10
AL12
AL16
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
RAD03
RAD04
RAD05
RAD06
RAD07
RAD08
RAD09
RAD10
RAD11
RAD12
RAD13
Data Sheet
27
Intel® 80960RS I/O Processor
Table 10.
540-Lead H-PBGA Package — Signal Name Order (Sheet 3 of 5)
Signal
Ball #
Signal
Ball #
Signal
Ball #
RAD14
RAD15
RAD16
RALE
RCE0#
RCE1#
ROE#
RWE#
SA00
D18
E18
A19
B19
C19
E19
D20
A20
N30
N29
N28
P32
P31
P30
P28
R32
R30
R29
R28
T32
T31
T30
L30
K32
K30
V31
W32
K31
K28
V30
W30
M30
M28
T28
U32
A8
SDQM0
SDQM1
SDQM2
SDQM3
SDQM4
SDQM5
SDQM6
SDQM7
SRAS#
L29
M32
S_AD27
S_AD28
S_AD29
S_AD30
S_AD31
S_C/BE0#
S_C/BE1#
S_C/BE2#
S_C/BE3#
S_DEVSEL#
S_FRAME#
S_GNT0#
S_GNT1#
S_GNT2#
S_GNT3#
S_GNT4#
S_GNT5#
S_IRDY#
S_LOCK#
S_PAR
AH25
AJ25
AK25
AM25
AH26
AH17
AJ19
AM21
AH24
AM20
AK21
AM26
AJ27
AM27
AK28
AM28
AK29
AJ21
AK20
AK19
AH20
AL26
AH27
AK27
AH28
AL28
AJ29
AK26
AM19
AL20
AH21
C12
U30
U28
L28
M31
U29
V32
N32
SA01
SWE#
L32
SA02
S_AD00
S_AD01
S_AD02
S_AD03
S_AD04
S_AD05
S_AD06
S_AD07
S_AD08
S_AD09
S_AD10
S_AD11
S_AD12
S_AD13
S_AD14
S_AD15
S_AD16
S_AD17
S_AD18
S_AD19
S_AD20
S_AD21
S_AD22
S_AD23
S_AD24
S_AD25
S_AD26
AH14
AK14
AL14
AM14
AH15
AJ15
AK15
AM15
AJ17
AK17
AM17
AH18
AK18
AL18
AM18
AH19
AH22
AK22
AL22
AM22
AH23
AJ23
AK23
AM23
AK24
AL24
AM24
SA03
SA04
SA05
SA06
SA07
SA08
SA09
SA10
SA11
SBA0
SBA1
SCAS#
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCE0#
SCE1#
SCKE0
SCKE1
SCL
S_PERR#
S_REQ0#
S_REQ1#
S_REQ2#
S_REQ3#
S_REQ4#
S_REQ5#
S_RST#
S_SERR#
S_STOP#
S_TRDY#
TCK
TDI
A12
TDO
E11
TMS
B11
TRST#
C11
SDA
C8
VCC
A17
28
Data Sheet
Intel® 80960RS I/O Processor
Table 10.
540-Lead H-PBGA Package — Signal Name Order (Sheet 4 of 5)
Signal
Ball #
Signal
Ball #
Signal
Ball #
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A29
B2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F2
F3
VCC
VCC
AL3
AL4
AL5
AL7
AL9
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL30
AL31
AM4
E20
C22
B15
D26
A1
B3
F4
VCC
B4
G30
G31
H2
VCC
B5
VCC
B6
VCC
B8
J31
VCC
B10
B12
B14
B16
B17
B18
B20
B22
B24
B26
B28
B29
B30
B31
C2
K2
VCC
L31
VCC
M2
VCC
N31
P2
VCC
VCC
R31
T2
VCC
VCC
U31
V2
VCC
VCC
W31
Y2
VCC
VCC
AA31
AB2
AC31
AD2
AE31
AF2
AG30
AG31
AH2
AH30
AH31
AJ1
AJ30
AJ31
AK2
AK3
AK30
AK31
AL2
VCC5REF
VCCPLL1
VCCPLL2
VCCPLL3
VSS
C3
C5
VSS
A2
C16
C29
C30
C31
D2
VSS
A3
VSS
A4
VSS
A5
VSS
A30
A31
A32
B1
VSS
D12
D30
D31
D32
E2
VSS
VSS
VSS
B21
B32
C1
VSS
VSS
E3
VSS
C4
E10
E31
VSS
C17
C32
VSS
Data Sheet
29
Intel® 80960RS I/O Processor
Table 10.
540-Lead H-PBGA Package — Signal Name Order (Sheet 5 of 5)
Signal
Ball #
Signal
Ball #
Signal
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D1
D3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G4
G28
G29
H29
J4
VSS
VSS
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28
AJ32
AK1
D4
VSS
D5
VSS
D7
VSS
D9
K29
L4
VSS
D11
D13
D15
D16
D17
D19
D21
D23
D25
D27
D28
D29
E1
VSS
M29
N4
VSS
VSS
P29
R4
VSS
VSS
T29
U4
VSS
VSS
V29
W4
VSS
AK4
VSS
AK16
AK32
AL1
Y29
AA4
AB29
AC4
AD29
AE4
AF29
AG4
AG5
AG28
AG29
AH5
AH16
AH29
AJ3
AJ4
AJ6
VSS
VSS
VSS
AL32
AM1
AM2
AM3
AM16
AM29
AM30
AM31
AM32
B9
VSS
E4
VSS
E16
E28
E29
E30
E32
F1
VSS
VCC
VSS
VSS
VSS
VSS
F5
XINT0#
XINT1#
XINT2#
XINT3#
XINT4#
XINT5#
F28
F29
F30
F31
F32
C9
E9
A10
C10
D10
30
Data Sheet
Intel® 80960RS I/O Processor
Table 11.
540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 1 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
A1
A2
VSS
VSS
B6
B7
VCC
P_RST#
VCC
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D1
TRST#
TCK
A3
VSS
B8
RAD02
RAD05
RAD09
VCC
A4
VSS
B9
XINT0#
VCC
A5
VSS
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
A6
P_AD29
P_GNT#
SCL
TMS
A7
VCC
VSS
A8
RAD01
VCC
RAD13
RCE0#
P_CLK
ONCE#
VCCPLL1
DQ02
DQ35
DQ06
DQ39
DQ41
DQ11
VCC
A9
NMI#
XINT3#
I_RST#
TDI
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B1
VCCPLL2
VCC
VCC
RAD00
RAD04
RAD08
N/C
VCC
RALE
VCC
VSS
VCC
VCC
RAD12
RAD16
RWE#
LCDINIT#
DCLKOUT
DQ01
DQ03
DQ05
DQ07
DQ40
DQ42
VCC
DQ33
VCC
DQ37
VCC
VCC
VCC
DQ09
VCC
VSS
VSS
VCC
D2
VCC
VCC
D3
VSS
VCC
D4
VSS
VSS
D5
VSS
VSS
D6
P_AD31
VSS
C2
VCC
D7
VSS
C3
VCC
D8
P_INTB#
VSS
VSS
C4
VSS
D9
VSS
C5
VCC
D10
D11
D12
D13
D14
D15
XINT5#
VSS
VSS
C6
P_AD30
P_INTD#
SDA
B2
VCC
C7
VCC
B3
VCC
C8
VSS
B4
VCC
C9
XINT1#
XINT4#
RAD06
VSS
B5
VCC
C10
Data Sheet
31
Intel® 80960RS I/O Processor
Table 11.
540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 2 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
E1
VSS
VSS
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
F1
DCLKIN
DQ32
DQ34
DQ36
DQ38
DQ08
DQ10
VSS
H28
H29
H30
H31
H32
J1
DQ45
VSS
RAD14
VSS
DQ13
DQ44
ROE#
VSS
DQ12
P_AD19
P_AD20
P_AD21
VSS
DQ00
VSS
J2
J3
DQ04
VSS
VSS
J4
VSS
J5
P_AD22
DQ47
VCCPLL3
VSS
VCC
J28
J29
J30
J31
J32
K1
VSS
DQ15
VSS
VSS
DQ46
VSS
F2
VCC
VCC
VCC
F3
VCC
DQ14
VCC
F4
VCC
P_C/BE2#
VCC
VCC
F5
VSS
K2
VSS
F28
F29
F30
F31
F32
G1
VSS
K3
P_AD16
P_AD17
P_AD18
SCB5
E2
VCC
VSS
K4
E3
VCC
VSS
K5
E4
VSS
VSS
K28
K29
K30
K31
K32
L1
E5
P_AD28
P_REQ#
P_INTC#
P_INTA#
XINT2#
VCC
VSS
VSS
E6
P_AD25
P_AD26
P_AD27
VSS
SCB1
E7
G2
SCB4
E8
G3
SCB0
E9
G4
P_DEVSEL#
P_TRDY#
P_IRDY#
VSS
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
G5
N/C
L2
TDO
G28
G29
G30
G31
G32
H1
VSS
L3
FAIL#
RAD03
RAD07
RAD10
VSS
VSS
L4
VCC
L5
P_FRAME#
SDQM4
SDQM0
SCAS#
VCC
VCC
L28
L29
L30
L31
L32
M1
DQ43
P_AD23
VCC
RAD11
RAD15
RCE1#
VCC5REF
H2
H3
P_IDSEL
P_C/BE3#
P_AD24
SWE#
H4
P_SERR#
VCC
H5
M2
32
Data Sheet
Intel® 80960RS I/O Processor
Table 11.
540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 3 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
M3
M4
P_PERR#
P_LOCK#
P_STOP#
SCE1#
VSS
R32
T1
SA07
P_AD03
VCC
W29
W30
W31
W32
Y1
DQ16
SCB7
VCC
M5
T2
M28
M29
M30
M31
M32
N1
T3
P_AD04
P_AD05
P_AD06
SCKE0
VSS
SCB3
N/C
T4
SCE0#
SDQM5
SDQM1
P_AD14
P_AD15
P_PAR
VSS
T5
Y2
VCC
T28
T29
T30
T31
T32
U1
Y3
N/C
Y4
N/C
SBA1
SBA0
SA11
P_AD00
P_AD01
P_AD02
VSS
Y5
N/C
N2
Y28
DQ50
VSS
N3
Y29
N4
Y30
DQ18
DQ49
DQ17
N/C
N5
P_C/BE1#
SA02
U2
Y31
N28
N29
N30
N31
N32
P1
U3
Y32
SA01
U4
AA1
AA2
AA3
AA4
AA5
AA28
AA29
AA30
AA31
AA32
AB1
AB2
AB3
AB4
AB5
AB28
AB29
AB30
AB31
AB32
AC1
AC2
AC3
SA00
U5
N/C
N/C
VCC
U28
U29
U30
U31
U32
V1
SDQM3
SDQM6
SDQM2
VCC
N/C
SRAS#
P_AD10
VCC
VSS
N/C
P2
DQ52
DQ20
DQ51
VCC
P3
P_AD11
P_AD12
P_AD13
SA06
SCKE1
N/C
P4
P5
V2
VCC
P28
P29
P30
P31
P32
R1
V3
N/C
DQ19
N/C
VSS
V4
N/C
SA05
V5
N/C
VCC
SA04
V28
V29
V30
V31
V32
W1
W2
W3
W4
W5
W28
N/C
N/C
SA03
VSS
N/C
P_AD07
P_C/BE0#
P_AD08
VSS
SCB6
SCB2
SDQM7
N/C
N/C
R2
DQ54
VSS
R3
R4
DQ22
DQ53
DQ21
N/C
R5
P_AD09
SA10
N/C
R28
R29
R30
R31
N/C
SA09
VSS
SA08
N/C
N/C
VCC
DQ48
N/C
Data Sheet
33
Intel® 80960RS I/O Processor
Table 11.
540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 4 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AC4
AC5
VSS
N/C
AG1
AG2
N/C
N/C
AH28
AH29
AH30
AH31
AH32
AJ1
S_REQ3#
VSS
AC28
AC29
AC30
AC31
AC32
AD1
DQ56
DQ24
DQ55
VCC
AG3
N/C
VCC
AG4
VSS
VCC
AG5
VSS
DQ63
VCC
AG28
AG29
AG30
AG31
AG32
AH1
VSS
DQ23
N/C
VSS
AJ2
N/C
VCC
AJ3
VSS
AD2
VCC
VCC
AJ4
VSS
AD3
N/C
DQ31
N/C
AJ5
N/C
AD4
N/C
AJ6
VSS
AD5
N/C
AH2
VCC
AJ7
N/C
AD28
AD29
AD30
AD31
AD32
AE1
DQ58
VSS
AH3
N/C
AJ8
VSS
AH4
N/C
AJ9
N/C
DQ26
DQ57
DQ25
N/C
AH5
VSS
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
VSS
AH6
N/C
N/C
AH7
N/C
VSS
AH8
N/C
N/C
AE2
N/C
AH9
N/C
VSS
AE3
N/C
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
N/C
S_AD05
VSS
AE4
VSS
N/C
AE5
N/C
N/C
S_AD08
VSS
AE28
AE29
AE30
AE31
AE32
AF1
DQ60
DQ28
DQ59
VCC
N/C
S_AD00
S_AD04
VSS
S_C/BE1#
VSS
S_IRDY#
VSS
DQ27
N/C
S_C/BE0#
S_AD11
S_AD15
S_PERR#
S_TRDY#
S_AD16
S_AD20
S_C/BE3#
S_AD27
S_AD31
S_REQ1#
S_AD21
VSS
AF2
VCC
AF3
N/C
S_AD28
VSS
AF4
N/C
AF5
N/C
S_GNT1#
VSS
AF28
AF29
AF30
AF31
AF32
DQ62
VSS
S_REQ5#
VCC
DQ30
DQ61
DQ29
VCC
VSS
34
Data Sheet
Intel® 80960RS I/O Processor
Table 11.
540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 5 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AK1
AK2
VSS
VCC
AL1
AL2
VSS
VCC
AM1
AM2
VSS
VSS
AK3
VCC
AL3
VCC
AM3
VSS
AK4
VSS
AL4
VCC
AM4
VCC
AK5
N/C
AL5
VCC
AM5
N/C
AK6
N/C
AL6
N/C
AM6
N/C
AK7
N/C
AL7
VCC
AM7
N/C
AK8
N/C
AL8
N/C
AM8
N/C
AK9
N/C
AL9
VCC
AM9
N/C
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
N/C
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
N/C
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
N/C
N/C
VCC
N/C
N/C
N/C
N/C
N/C
VCC
N/C
S_AD01
S_AD06
VSS
S_AD02
VCC
S_AD03
S_AD07
VCC
N/C
S_AD09
S_AD12
S_PAR
S_LOCK#
S_FRAME#
S_AD17
S_AD22
S_AD24
S_AD29
S_RST#
S_REQ2#
S_GNT3#
S_GNT5#
VCC
VCC
S_AD10
S_AD14
S_SERR#
S_DEVSEL#
S_C/BE2#
S_AD19
S_AD23
S_AD26
S_AD30
S_GNT0#
S_GNT2#
S_GNT4#
VSS
S_AD13
VCC
S_STOP#
VCC
S_AD18
VCC
S_AD25
VCC
S_REQ0#
VCC
S_REQ4#
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VSS
Data Sheet
35
Intel® 80960RS I/O Processor
3.2
Package Thermal Specifications
The device is specified for operation when T (case temperature) is within the range of 0°C to
C
85°C, depending on operating conditions. Refer to the “Thermal Data for the 540-lead PBGA
package” application note for more information regarding maximum case temperatures on the
540-lead PBGA package. Case temperature may be measured in any environment to determine
whether the processor is within specified operating range. Measure the case temperature at the
center of the top surface, opposite the ballpad.
3.2.1
Thermal Specifications
This section defines the terms used for thermal analysis.
3.2.1.1
Ambient Temperature
Ambient temperature, T , is the temperature of the ambient air surrounding the package. In a
A
system environment, ambient temperature is the temperature of the air upstream from the package.
3.2.1.2
Case Temperature
When measuring case temperature, attention to detail is required to ensure accuracy. If a
thermocouple is used, calibrate it before taking measurements. Errors may result when the
measured surface temperature is affected by the surrounding ambient air temperature. Such errors
may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by
radiation, or conduction through thermocouple leads.
To minimize measurement errors:
• Use a 35 gauge K-type thermocouple or equivalent.
• Attach the thermocouple bead or junction to the package top surface at a location
corresponding to the center of the die (Figure 5A). The center of the die gives a more accurate
measurement and less variation as the boundary condition changes.
• Attach the thermocouple bead at a 0° angle with respect to the package as shown in Figure 5A,
when no heatsink is attached.
• When a passive heat sink is attached, a groove is made on the bottom surface of the heatsink
and the thermocouple is attached at a 0° angle, as shown in Figure 5B.
Figure 5.
Thermocouple Attachment - A) No Heatsink / B) With Heatsink
80960RS
Bottom of
Processor
Heatsink
Groove for
thermocouple
Thermocouple
A) No Heatsink
B) With Heatsink
36
Data Sheet
Intel® 80960RS I/O Processor
3.2.1.3
3.2.2
Thermal Resistance
The thermal resistance value for the case-to-ambient, θ , is used as a measure of the cooling
solution’s thermal performance.
CA
Thermal Analysis
Table 12 lists the case-to-ambient thermal resistances of the 80960RM for different air flow rates
with and without a heat sink.
To calculate T , the maximum ambient temperature to conform to a particular case temperature:
A
T = T - P (θ )
CA
A
C
Compute P by multiplying I and V . Values for θ and θ are given in Table 12.
CC
CC
JC
CA
Junction temperature (T ) is commonly used in reliability calculations. T can be calculated from
J
J
θ
(thermal resistance from junction to case) using the following equation:
JC
T = T + P (θ )
JC
J
C
Similarly, when T is known, the corresponding case temperature (T ) can be calculated as
A
C
follows:
T = T + P (θ )
CA
C
A
The θ (Junction to Ambient) for this package is currently estimated at 13.10° C/Watt with no
JA
airflow and no heatsink. The θ (Junction to Ambient) for this package is currently estimated at
JA
8.30° C/Watt with no airflow and a passive heatsink:
θJA = θJC + θ
CA
Table 12.
540-Lead H-PBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
(0.50)
0.44
200
(1.01)
0.44
300
(1.52)
0.44
400
(2.03)
0.44
600
(3.04)
0.44
800
(4.06)
0.44
(0)
(0.25)
0.44
θJC (Junction-to-Case)
0.44
θCA (Case-to-Ambient)
Without Heatsink
12.66
11.61
10.66
9.26
8.26
7.61
6.57
5.78
θCA (Case-to-Ambient)
With Passive 0.25 in.
Heatsink2,3
9.0
8.2
7.5
6.1
5.1
4.7
3.8
3.2
θCA (Case-to-Ambient)
With Passive 0.35 in.
Heatsink2
7.86
6.96
6.06
4.56
3.66
3.16
2.56
2.16
θJA
θCA
θJC
NOTES:
1. This table applies to a H-PBGA device soldered directly onto a board.
2. See Table 13 for heatsink information.
3. Estimated value.
Data Sheet
37
Intel® 80960RS I/O Processor
3.3
Heat Sink Information
Table 13 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a
warranty of the performance of any of the listed products and/or companies.
Table 13.
Heat Sink Vendors and Contacts
Heatsink Part #
Factory
Company
Phone #
Fax #
Representative
Passive
AAVID Thermalloy, Inc
80 Commercial Street
Concord, NH 03301 USA
Attention: Sales (603) 224-9988 (603) 223-1790 21933B withoou thermal
grease (uses pins)
21935B withoou thermal
grease (uses pins)
info@aavid.com
http://www.aavidthermalloy.com/atp/atp.html
3.3.1
Socket Information
®
Table 14 and Table 15 provide vendor details for socket-headers and burn-in sockets for the Intel
80960RS processor. This is neither an endorsement nor a warranty of the performance of any of the
listed products and/or companies.
3.3.2
Socket-Header Vendor
Table 14.
Socket-Header Vendor
Part #
Factory
Representative
Company
Phone/Fax #
BGA 540 Pin Header
BGA 540 Pin Socket Carrier
Adapter Technologies, Inc.
214-218 South 4th St.
Perkasie, PA 18944
John Miller
215-258-5750/ BGAH-540-0-01-3201-0277-1 BGA-540-0-02-3201-0275P-130
215-258-5760
3.3.3
Burn-in Socket Vendor
Table 15.
Burn-in Socket Vendor
Company
Factory Representative
W. Ray Johnson
Phone #
Burn-in Socket Part #
Texas Instruments
111 Forbes Blvd.
508-236-5375
ULGA540-005
Mansfield, MA 02048
38
Data Sheet
Intel® 80960RS I/O Processor
3.3.4
Shipping Tray Vendor
Table 16.
Shipping Tray Vendor
Company
3M
Factory Representative
Phone #
Shipping Tray Part #
Ron Goth
602-465-5381
7-0000-21001-184-167
3.3.5
Logic Analyzer Interposer Vendor
Table 17.
Logic Analyzer Interposer Vendor
Company
Factory Representative
Phone/Fax #
Part #
Packard-Hughes Interconnect
17150 Von Karman Ave
Irvine, CA 92614-0968
Karen May
949-660-5773
949-660-5825
1126898
3.3.6
JTAG Emulator Vendor
Table 18.
JTAG Emulator Vendor
Phone/
Fax #
Company
Factory Representative
Part #
281-494-4500/
281-494-5310
Spectrum Digital, Inc.
Jeff Bond
701500
Data Sheet
39
Intel® 80960RS I/O Processor
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
–55° C to + 125° C
0° C to + 85° C
NOTICE: This data sheet contains information on
products in the design phase of development. Do
not finalize a design with this information. Revised
information will be published when the product
becomes available. The specifications are subject
to change without notice. Contact your local Intel
representative before finalizing a design.
Storage Temperature
Case Temperature Under Bias
Supply Voltage wrt. VSS
–0.5 V to + 4.6 V
Supply Voltage wrt. VSS on VCC5 –0.5 V to + 6.5 V
Voltage on Any Ball wrt. VSS
–0.5 V to VCC + 0.5 V
†WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is
not recommended and extended exposure beyond
the “Operating Conditions” may affect device
reliability.
Table 19.
Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
V
Supply Voltage
3.0
3.6
V
V
CC
V
F
Input Protection Bias
Input Clock Frequency
V
V
+2.5
CC5
CC
CC
16
33.33
85
MHz
P_CLK
Case Temperature Under Bias
GC (540L PBGA)
TC
0
°C
40
Data Sheet
Intel® 80960RS I/O Processor
4.2
VCC5REF Pin Requirements (VDIFF)
In mixed voltage systems that drive 80960RS processor inputs in excess of 3.3 V, the V
pin
CC5REF
must be connected to the system’s 5 V supply. To limit current flow into the V
pin, there is
CC5REF
a limit to the voltage differential between the V
pin and the other V pins. The voltage
CC5REF
CC
differential between the V
pin and its 3.3 V V pins should never exceed 2.25 V. This
CC5REF
CC
limit applies to power-up, power-down, and steady-state operation. Table 20 outlines this
requirement.
If the voltage difference requirements cannot be met due to system design limitations, an alternate
solution may be employed. As shown in Figure 6, a minimum of 100 Ω series resistor may be used
to limit the current into the V
pin. This resistor ensures that current drawn by the V
CC5REF
CC5REF
pin does not exceed the maximum rating for this pin.
Figure 6.
V
Current-Limiting Resistor
CC5REF
VCC5REF Pin
+5 V (±0.25 V)
100 Ω
(±5%, 0.5 W)
This resistor is not necessary in systems that can guarantee the V
specification.
DIFF
In 3.3 V-only systems and systems that drive pins from 3.3 V logic, connect the V
pin
CC5REF
directly to the 3.3 V V plane.
CC
Table 20.
V
Specification for Dual Power Supply Requirements (3.3 V, 5 V)
DIFF
Symbol
Parameter
Min
Max
Units
Notes
V
CC5REF input should not exceed VCC by more than
VCC5-VCC
Difference
VDIFF
2.25
V
2.25 V during power-up and power-down, or during
steady-state operation.
4.3
VCCPLL Pin Requirements
To reduce clock skew on the i960 Jx processor, the V
pin for the Phase Lock Loop (PLL)
CCPLL
circuit is isolated on the pinout. The lowpass filter, as shown in Figure 7, reduces noise induced
clock jitter and its effects on timing relationships in system designs. The trace lengths between the
4.7 µF capacitor, the 0.01 µF capacitor, and V
must be as short as possible.
CCPLL
Figure 7.
V
Lowpass Filter
CCPLL
10Ω, 5%, 1/8W
VCCPLL
(On i960® Jx processors)
+
VCC
(Board Plane)
4.7µF
0.01µF
Data Sheet
41
Intel® 80960RS I/O Processor
4.4
Targeted DC Specifications
Table 21.
DC Characteristics
Symbol
Parameter
Min
Max
Units
Notes
VIL5
Input Low Voltage 5 Volt PCI
Input High Voltage 5 Volt PCI
Input Low Voltage 3.3 Volt PCI
Input High Voltage 3.3 Volt PCI
Output Low Voltage Processor signals
-0.5
2
0.8
V
V
V
V
V
(1,4)
(1,4)
(1,4)
(1,4)
VIH5
VCC + 0.5
0.3VCC
VCC + 0.5
0.4
VIL3.3
VIH3.3
VOL1
-0.5
0.5VCC
IOL = 6 mA (3)
2.4
VCC - 0.5
I
OH = -2 mA (3)
VOH1
VOL2
VOH2
Output High Voltage Processor signals
V
V
V
IOH = -200 µA (3, 5)
Output Low Voltage 5 V PCI / Flash
signals
0.4
I
OL = 6 mA (1)
OH = -2 mA (1)
Output High Voltage 5 V PCI / Flash
signals
2.4
I
VOL3
VOH3
VOL4
VOH4
CIN
Output Low Voltage SDRAM signals
Output High Voltage SDRAM signals
Output Low Voltage 3.3 V PCI signals
Output Low Voltage 3.3 V PCI signals
Input Capacitance - PBGA
-2.0
2.4
0.4
V
V
IOL = 3 mA (4)
IOH = -2 mA (4)
IOL = 1500 µA (1)
IOH = -500 µA (1)
FS_CLK = TF Min (1, 2)
FS_CLK = TF Min (1, 2)
FS_CLK = TF Min (1, 2)
(1,2)
VCC + 2.0
0.1VCC
V
0.9VCC
V
10
10
10
8
pF
pF
pF
pF
nH
COUT
CCLK
CIDSEL
LPIN
I/O or Output Capacitance - PBGA
S_CLK Capacitance - PBGA
IDSEL Ball Capacitance
5
Ball Inductance
25
(1,2)
NOTES:
1. As required by the PCI Local Bus Specification, Revision 2.2.
2. Not tested.
3. Processor signals include RALE, RCE[1:0]#, ROE#, RWE#, XINT[5:4]#, NMI#, FAIL#, TDI, TDO, TMS,
TRST#, SDA, and SCL.
4. SDRAM signals include SA[11:0], SBA[1:0], SCAS#, SCE[1:0]#, SCKE[1:0], SDQM[7:0], SRAS#,
SWE#, DCLKIN, DCLKOUT, DQ[63:0], and SCB[7:0].
5. Guaranteed by characterization
42
Data Sheet
Intel® 80960RS I/O Processor
Table 22.
I
Characteristics
CC
Symbol
Parameter
Typ Max Units
Notes
µA 0 ≤ VIN ≤ VCC
µA IN = 0.45 V (1)
µA 0.4 ≤ VOUT ≤ VCC
Input Leakage Current for each signal except TMS,
TRST#, TDI, ONCE#, RAD[8:0] and LCDINIT#.
ILI1
± 5
Input Leakage Current for TMS, TRST#, and TDI,
ONCE#, RAD[8:0] and LCDINIT#.
ILI2
ILO
-140 -250
± 5
V
Output Leakage Current
Power Supply Current
ICC Active
(Power Supply)
1.45
A
A
A
(1,2)
(1,3)
I
CC Active
(Thermal)
Thermal Current
Reset Mode
1.1
I
CC Active
(Power Modes) ONCE Mode
0.95
0.02
(4)
(4)
NOTES:
1. Measured with device operating and outputs loaded to the test condition in Figure 13.
2. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.6 V and ambient temperature = 55°C.
3. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC = 3.3 V and ambient temperature = 55°C.
4. ICC Test (Power modes) refers to the ICC values that are tested when the device is in Reset mode or ONCE
mode with VCC = 3.6 V and ambient temperature = 55°C.
Data Sheet
43
Intel® 80960RS I/O Processor
4.5
Targeted AC Specifications
4.5.1
Clock Signal Timings
Table 23.
Input Clock Timings
Symbol
TF
Parameter
P_CLK Frequency
Min
Max
Units
Notes
16
30
33.33
62.5
MHz
ns
TC
P_CLK Period
(1)
TCS
P_CLK Period Stability
P_CLK High Time
P_CLK Low Time
P_CLK Rise Time
P_CLK Fall Time
±250
ps
Adjacent Clocks (2)
Measured at 1.5 V (2)
Measured at 1.5 V (2)
12
12
1
ns
TCH
TCL
ns
TCR
4
4
V/ns 0.4 V to 2.4 V (2)
V/ns 2.4 V to 0.4 V (2)
TCF
1
TDICS
DCLKIN Period Stability
DCLKIN High Time
DCLKIN Low Time
±250
ps
ns
ns
Adjacent Clocks (2)
Measured at 1.5 V (2)
Measured at 1.5 V (2)
5
5
TDICH
TDICL
NOTES:
1. See Figure 8 “P_CLK, TCK, DCLKIN, DCLKOUT Waveform” on page 49.
2. Not tested.
Table 24.
SDRAM Output Clock Timings
Symbol
Parameter
Min
Max
Units
Notes
TDOF
DCLKOUT Frequency
DCLKOUT Period
2TF
TC / 2
±250
MHz
ns
TDOC
TDOCS
(1)
DCLKOUT Period Stability
DCLKOUT High Time
DCLKOUT Low Time
ps
Adjacent Clocks
Measured at 1.5 V
Measured at 1.5 V
5
5
ns
TDOCH
TDOCL
ns
NOTE:
1. See Figure 8 “P_CLK, TCK, DCLKIN, DCLKOUT Waveform” on page 49.
44
Data Sheet
Intel® 80960RS I/O Processor
4.5.2
PCI Interface Signal Timings
Table 25.
PCI Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
(1,2)
Output Valid Delay from P_CLK - PCI Signals Except
P_REQ#, P_INT[A:D]#, and S_GNT[5:0]#
TOV1
TOV2
TOV4
TOF
2
0
2
11
25
12
28
ns
ns
ns
ns
ns
Output Valid Delay from P_CLK - P_INT[A:D]#
(1,2,6)
(1,2)
Output Valid Delay from P_CLK - P_REQ# and
S_GNT[5:0]#
Output Float Delay from P_CLK
(1,4,5,6)
(1,3)
Input Setup to P_CLK - PCI Signals Except P_GNT# and
TIS1
7
S_REQ[5:0]#
TIS2
TIS3
TIH1
Input Setup to P_CLK - P_GNT#
Input Setup to P_CLK - S_REQ[5:0]#
Input Hold from P_CLK - PCI Signals
Input Setup to P_CLK - S_INT[A:D]#
Input Hold to P_CLK - S_INT[A:D]#
Input Setup to P_CLK - P_RST#
Input Hold to P_CLK - P_RST#
10
12
0
ns
ns
ns
ns
ns
ns
ns
(1,3)
(1,3)
(1,3)
25
2
(1,3,7,8)
(1,3,7,8)
(1,3,7)
(1,3,7)
TIS4
TIH2
TIS5
6
TIH3
2
NOTES:
1. The PCI Local Bus Specification, Revision 2.2 requires that all of the PCI signal AC timings use 0 pF for
minimum timings and 50 pF for maximum timings.
2. See Figure 9 “TOV Output Delay Waveform” on page 49.
3. See Figure 11 “TIS and TIH Input Setup and Hold Waveform” on page 50.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See
Figure 10 “TOF Output Float Waveform” on page 50.
5. See Figure 10 “TOF Output Float Waveform” on page 50.
6. Outputs precharged to VCC5
.
7. P_RST#, S_INT[A:D]# may be synchronous or asynchronous. Meeting setup and hold time guarantees
recognition at a particular clock edge.
8. S_INT[A:D]# must be asserted for a minimum of two P_CLK periods to guarantee recognition.
Data Sheet
45
Intel® 80960RS I/O Processor
4.5.3
Intel® 80960JN Core Interface Timings
®
Table 26.
Intel 80960JN Core Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
(1,5)
TOV5
Output Valid Delay from P_CLK - FAIL#
Input Setup to P_CLK - NMI#, XINT[5:4]#
Input Hold from P_CLK - NMI#, XINT[5:4]#
2
25
2
TBD
ns
ns
ns
TIS7
(2,3)
(2,3)
TIH5
NOTES:
1. See Figure 9 “TOV Output Delay Waveform” on page 49.
2. See Figure 11 “TIS and TIH Input Setup and Hold Waveform” on page 50.
3. Setup and hold times must be met for proper processor operation. NMI# and XINT[5:4]# may be
synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock
edge. For asynchronous operation, NMI# and XINT[5:4]# must be asserted for a minimum of two P_CLK
periods to guarantee recognition.
4. Core signals include: XINT[5:4]#, NMI#, FAIL# .
5. The processor asserts FAIL# during built-in self-test. If self-test passes, FAIL# is deasserted. The
processor asserts FAIL# during the bus confidence test. If the test passes, FAIL# is deasserted and user
program execution begins.
4.5.4
SDRAM/Flash Interface Signal Timings
Table 27.
SDRAM / Flash Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
(1,5)
Output Valid Delay from DCLKIN - SA[11:0], SBA[1:0],
SCAS#, SRAS#, and SWE#.
TOV6
1.62
6.6
ns
TOV7
TOV8
TOV9
TOV10
TIS8
Output Valid Delay from DCLKIN - DQ[63:0], and SCB[7:0].
Output Valid Delay from DCLKIN - SDQM[7:0]
Output Valid Delay from DCLKIN - SCKE[1:0]
Output Valid Delay from DCLKIN - SCE[1:0]#
Input Setup to DCLKIN - DQ[63:0], and SCB[7:0]
Input Hold from DCLKIN - DQ[63:0], and SCB[7:0]
2.03
2.57
1.74
1.65
3
7.14
6.85
5.5
ns
ns
ns
ns
ns
ns
(1,5)
(1,5)
(1,5)
(1,5)
(2)
5.25
TIH6
1.5
(2)
Output Valid Delay from DCLKIN - RAD[16:0], RALE,
RCE[1:0]#, ROE#, and RWE#.
TOV11
1.4
11
ns
(1,5)
TIS9
Input Setup to DCLKIN - RAD[16:0]
Input Hold from DCLKIN - RAD[16:0]
5
ns
ns
(2)
(2)
TIH7
1.4
NOTES:
1. See Figure 9 “TOV Output Delay Waveform” on page 49.
2. See Figure 11 “TIS and TIH Input Setup and Hold Waveform” on page 50.
3. SDRAM signals include SA[11:0], SBA[1:0], SCAS#, SCE[1:0]#, SCKE[1:0], SDQM[7:0], SRAS#,
SWE#, DQ[63:0], and SCB[7:0]. Timings are for 3.3V signalling environment.
4. Flash signals include RAD[16:0], RALE, RCE[1:0]#, ROE#, and RWE#. Timings are for 5 V signalling
environment.
5. These output valid times are specified with a 0 pF loading.
46
Data Sheet
Intel® 80960RS I/O Processor
4.5.5
Boundary Scan Test Signal Timings
Table 28.
Boundary Scan Test Signal Timings
Symbol
Parameter
TCK Frequency
Min
Max
Units
Notes
TBSF
0
0.5TF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBSCH
TCK High Time
15
15
Measured at 1.5 V (1)
TCK Low Time
Measured at 1.5 V (1)
TBSCL
TBSCR
TCK Rise Time
5
5
0.8 V to 2.0 V (1)
TBSCF
TBSIS1
TBSIH1
TBSIS2
TBSIH2
TBSOV1
TOF1
TCK Fall Time
2.0 V to 0.8 V (1)
Input Setup to TCK — TDI, TMS
Input Hold from TCK — TDI, TMS
Input Setup to TCK — TRST#
Input Hold from TCK — TRST#
TDO Valid Delay
4
6
(4)
(4)
25
3
(4)
(4)
3
30
30
30
30
Relative to falling edge of TCK (2, 3)
Relative to falling edge of TCK (2, 5)
Relative to falling edge of TCK (2, 3)
Relative to falling edge of TCK (2, 5)
TDO Float Delay
3
TOV12
TOF2
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
3
3
Input Setup to TCK — All Inputs
(Non-Test)
TIS10
4
6
ns
ns
(4)
(4)
Input Hold from TCK — All Inputs
(Non-Test)
TIH8
NOTES:
1. Not tested.
2. Outputs precharged to VCC5
.
3. See Figure 9 “TOV Output Delay Waveform” on page 49.
4. See Figure 11 “TIS and TIH Input Setup and Hold Waveform” on page 50.
5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See
Figure 10 “TOF Output Float Waveform” on page 50.
Data Sheet
47
Intel® 80960RS I/O Processor
4.5.6
I2C Interface Signal Timings
2
Table 29.
I C Interface Signal Timings
Std. Mode
Fast Mode
Symbol
Parameter
Units Notes
Min
Max
Min
Max
400 KHz
µs
FSCL
TBUF
SCL Clock Frequency
0
100
0
Bus Free Time Between STOP and START
Condition
4.7
1.3
(1)
THDSTA
TLOW
Hold Time (repeated) START Condition
SCL Clock Low Time
4
4.7
4
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
(1,3)
(1,2)
(1,2)
(1)
THIGH
TSUSTA
THDDAT
TSUDAT
TSR
SCL Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time
4.7
0
0.9
(1)
Data Setup Time
250
100
(1)
SCL and SDA Rise Time
SCL and SDA Fall Time
1000 20+0.1Cb
300 ns
300 ns
µs
(1,4)
(1,4)
(1)
TSF
300
20+0.1Cb
0.6
TSUSTO
NOTES:
Setup Time for STOP Condition
4
1. See Figure 12.
2. Not tested.
3. After this period, the first clock pulse is generated.
4. Cb = the total capacitance of one bus line, in pF.
48
Data Sheet
Intel® 80960RS I/O Processor
4.6
AC Timing Waveforms
Figure 8.
P_CLK, TCK, DCLKIN, DCLKOUT Waveform
T
T
CR
CF
2.0V
1.5V
0.8V
T
CH
T
CL
T
C
Figure 9.
T
Output Delay Waveform
OV
1.5V
1.5V
P_CLK / DCLKIN
TOVX Min
TOVX Max
1.5V
1.5V
Valid
Data Sheet
49
Intel® 80960RS I/O Processor
Figure 10.
Figure 11.
Figure 12.
T
Output Float Waveform
OF
1.5V
1.5V
P_CLK / DCLKIN
T
OF
TIS and TIH Input Setup and Hold Waveform
1.5V
1.5V
1.5V
P_CLK / DCLKIN
T
IHX
T
ISX
Valid
1.5V
2
I C Interface Signal Timings
SDA
T
T
LOW
BUF
T
T
T
T
T
T
T
HDSTA
SF
SP
SR
SCL
T
HDSTA
SUSTO
T
T
HIGH
HDDAT
SUDAT
SUSTA
Stop
Start
Stop
Repeated
Start
50
Data Sheet
Intel® 80960RS I/O Processor
4.7
AC Test Conditions
The AC specifications in Section 4.5, “Targeted AC Specifications” on page 44 are tested with a
50 pF load indicated in Figure 13.
Figure 13.
AC Test Load (all signals except SDRAM and Flash signals)
Output Ball
CL = 50 pF
CL
The PCI maximum AC specifications are tested with the 50 pF load indicated in Figure 13. The
PCI minimum AC specifications are tested with a 0 pF load. All of the SDRAM and Flash timings
are specified for a 0 pF load.
Data Sheet
51
Intel® 80960RS I/O Processor
5.0
Device Identification on Reset
During the manufacturing process, values characterizing the 80960 RM/RN I/O processor type and
stepping are programmed into memory-mapped registers. The 80960 RM/RN I/O processor
contains two read-only device ID MMRs. One holds the Processor Device ID (PDIDR MMR
Location - 0000 1710H) and the other holds the 80960 Core Processor Device ID (DEVICEID
MMR Location - FF00 8710H). During initialization, the DEVICEID is placed in g0.
The device identification values are compliant with the IEEE 1149.1 specification and Intel
standards. Table 30 describes the fields of the two Device IDs.
Note: The value programmed into these registers varies with stepping. Refer to the Specification Update
for the correct value.
Table 30.
Device ID Registers
31
28
24
20
16
12
8
4
0
IB
ro ro
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Legend:NA = Not AccessibleRO = Read Only
RV = ReservedPR = PreservedRW = Read/Write
RS = Read/SetRC = Read Clear
IB:
0000 1710H
FF00 8710H
NA
PCI:
IB = Internal Bus AddressPCI = PCI Configuration Address Offset
Bit
31:28
27
Default
Description
X
X
Version - Indicates stepping changes.
VCC - Indicates device voltage type.
0 = 5.0 V
1 = 3.3 V
26:21
20:17
16:12
11:01
X
X
X
X
Product Type - Indicates the generation or “family member”.
Generation Type - Indicates the generation of the device.
Model Type - Indicates member within a series and specific model information.
Manufacturer ID - Indicates manufacturer ID assigned by IEEE.
0000 0001 001 = Intel Corporation
0
1
Constant
52
Data Sheet
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