80960VH [INTEL]

RISC Microprocessor, 32-Bit, 33.33MHz, CMOS, PBGA324, PLASTIC, BGA-324;


型号：	80960VH
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 33.33MHz, CMOS, PBGA324, PLASTIC, BGA-324 时钟外围集成电路
文件：	总64页 (文件大小：444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

i960^®VH Embedded-PCI Processor

Preliminary Datasheet

Product Features

■ High Performance 80960JT Core

■ Memory Controller

—Sustained One Instruction/Clock

Execution

—256 Mbytes of 32- or 36-Bit DRAM

—Interleaved or Non-Interleaved DRAM

—Fast Page-Mode DRAM Support

—Extended Data Out DRAM Support

—16 Kbyte Two-Way Set-Associative

Instruction Cache

—4 Kbyte Direct-Mapped Data Cache

—Sixteen 32-Bit Global Registers

—Sixteen 32-Bit Local Registers

—Two Independent Banks for SRAM /

ROM / Flash (16 Mbytes/Bank; 8- or

32-Bit)

—Programmable Bus Widths:

8-, 16-, 32-Bit

■ DMA Controller

—Two Independent Channels

—PCI Memory Controller Interface

—32-Bit Local Bus Addressing

—64-Bit PCI Bus Addressing

—Independent Interface to PCI Bus

—1 Kbyte Internal Data RAM

—Local Register Cache

(Eight Available Stack Frames)

—Two 32-Bit On-Chip Timer Units

—Core Clock Rate: 1x, 2x or 3x Local Bus

Clock

—132 Mbyte/sec Burst Transfers to PCI

and Local Buses

■ PCI Interface

—Direct Addressing to and from PCI

Buses

—Complies with PCI Local Bus

Specification 2.2

—Unaligned Transfers Supported in

Hardware

—Runs at Local Bus Clock Rate

—5 Volts PCI Signaling Environment

■ Address Translation Unit

—Channels Dedicated to PCI Bus

■ I²C Bus Interface Unit

—Serial Bus

—Connects Local Bus to PCI Bus

—Inbound/Outbound Address Translation

Support

—Master/Slave Capabilities

—System Management Functions

■ 3.3 V Supply

—Direct Outbound Addressing Support

■ Messaging Unit

—5 V Tolerant Inputs

—Four Message Registers

—Two Doorbell Registers

—TTL Compatible Outputs

■ Plastic BGA* Package

—324 Ball-Grid Array (PBGA)

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Order Number: 273179-004

April 1999

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The i960^®VH Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Preliminary Datasheet

80960VH

Contents

1.0

About This Document.........................................................................................................7

1.1

1.2

1.3

Solutions960^®Program.........................................................................................7

Terminology...........................................................................................................7

Additional Information Sources .............................................................................7

2.0

Functional Overview...........................................................................................................8

2.1

Key Functional Units .............................................................................................9

2.1.1 DMA Controller.........................................................................................9

2.1.2 Address Translation Unit..........................................................................9

2.1.3 Messaging Unit.........................................................................................9

2.1.4 Memory Controller....................................................................................9

2.1.5 Core and Peripheral Unit..........................................................................9

2.1.6 I2C Bus Interface Unit ..............................................................................9

i960^®Core Features (80960JT) ..........................................................................10

2.2.1 Burst Bus................................................................................................11

2.2.2 Timer Unit...............................................................................................11

2.2.3 Priority Interrupt Controller .....................................................................11

2.2.4 Faults and Debugging ............................................................................11

2.2.5 On-Chip Cache and Data RAM..............................................................12

2.2.6 Local Register Cache.............................................................................12

2.2.7 Test Features .........................................................................................12

2.2.8 Memory-Mapped Control Registers .......................................................12

2.2.9 Instructions, Data Types and Memory Addressing Modes.....................13

2.2

3.0

Package Information ........................................................................................................15

3.1

Package Introduction...........................................................................................15

3.1.1 Functional Signal Definitions..................................................................15

3.1.2 324-Lead PBGA Package ......................................................................25

Package Thermal Specifications.........................................................................33

3.2.1 Thermal Specifications...........................................................................33

3.2.1.1 Ambient Temperature................................................................33

3.2.1.2 Case Temperature ....................................................................33

3.2.1.3 Thermal Resistance ..................................................................34

3.2.2 Thermal Analysis....................................................................................34

3.2

4.0

Electrical Specifications....................................................................................................35

4.1

4.2

4.3

4.4

Pin Requirements (V

) ..........................................................................35

DIFF

CC5

Pin Requirements ...................................................................................36

CCPLL

DC Specifications................................................................................................37

AC Specifications ................................................................................................39

4.4.1 Relative Output Timings .........................................................................41

4.4.2 Memory Controller Relative Output Timings ..........................................41

4.4.3 Boundary Scan Test Signal Timings ......................................................43

4.4.4 I2C Interface Signal Timings ..................................................................44

AC Test Conditions .............................................................................................44

AC Timing Waveforms ........................................................................................45

Memory Controller Output Timing Waveforms....................................................48

4.5

4.6

4.7

Preliminary Datasheet

80960VH

5.0

6.0

Bus Functional Waveforms ..............................................................................................54

Device Identification On Reset.........................................................................................63

Figures

Product Name Functional Block Diagram ............................................................. 8

80960JT Core Block Diagram .............................................................................10

324-Plastic Ball Grid Array Top and Side View...................................................25

324-Plastic Ball Grid Array (Top View)................................................................26

Thermocouple Attachment ..................................................................................33

Current-Limiting Resistor ...........................................................................36

CC5

Lowpass Filter ........................................................................................36

CCPLL

AC Test Load ......................................................................................................44

P_CLK, TCLK Waveform ....................................................................................45

Output Delay Waveform ..............................................................................45

Output Float Waveform................................................................................46

and T Input Setup and Hold Waveform ......................................................46

and T

Relative Timings Waveform ........................................................46

LXL

LXA

DT/R# and DEN# Timings Waveform .................................................................47

I²C Interface Signal Timings................................................................................47

Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960

Local Bus ............................................................................................................48

Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960

Local Bus ............................................................................................................49

FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States..................50

FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States..................51

EDO DRAM, Read Cycle ....................................................................................52

EDO DRAM, Write Cycle ....................................................................................52

32-Bit Bus, SRAM Read Accesses with 0 Wait States .......................................53

32-Bit Bus, SRAM Write Accesses with 0 Wait States........................................53

Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local

Bus......................................................................................................................54

Burst Read and Write Transactions without Wait States, 32-Bit 80960

Local Bus ............................................................................................................55

Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus.......56

Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus57

Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on

Read, 16-Bit 80960 Local Bus ............................................................................58

Bus Transactions Generated by Double Word Read Bus Request, Misaligned One

Byte From Quad Word Boundary, 32-Bit 80960 Local Bus.................................59

HOLD/HOLDA Waveform For Bus Arbitration ....................................................60

80960 Core Cold Reset Waveform .....................................................................61

80960 Local Bus Warm Reset Waveform ...........................................................62

Preliminary Datasheet

80960VH

Tables

Related Documentation.........................................................................................7

80960VH Instruction Set .....................................................................................14

Signal Type Definition .........................................................................................15

Signal Descriptions..............................................................................................16

Power Requirement, Processor Control and Test Signal Descriptions...............19

Interrupt Unit Signal Descriptions........................................................................20

PCI Signal Descriptions.......................................................................................21

Memory Controller Signal Descriptions...............................................................22

DMA, I²C Units Signal Descriptions ....................................................................24

Clock Related Signals .........................................................................................24

PBGA 324 Package Dimensions.........................................................................26

324-Plastic Ball Grid Array Ballout — In Ball Order ............................................27

324-Plastic Ball Grid Array Ballout — In Signal Order ........................................30

324-Lead PBGA Package Thermal Characteristics ............................................34

Absolute Maximum Ratings.................................................................................35

Operating Conditions...........................................................................................35

Specification for Dual Power Supply Requirements (3.3 V, 5 V)...............36

DIFF

DC Characteristics ..............................................................................................37

Characteristics ..............................................................................................38

Input Clock Timings.............................................................................................39

Synchronous Output Timings..............................................................................39

Synchronous Input Timings.................................................................................40

Relative Output Timings......................................................................................41

Fast Page Mode Non-interleaved DRAM Output Timings...................................41

Fast Page Mode Interleaved DRAM Output Timings ..........................................41

EDO DRAM Output Timings................................................................................42

SRAM/ROM Output Timings ...............................................................................42

Boundary Scan Test Signal Timings ...................................................................43

I2C Interface Signal Timings ...............................................................................44

Processor Device ID Register - PDIDR..............................................................63

Preliminary Datasheet

80960VH

1.0

About This Document

This is the Preliminary data sheet for the low-power (3.3 V) version of Intel’s i960 VH processor

(“80960VH”) family.

This data sheet contains a functional overview, mechanical data (package signal locations and

simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional

waveforms. Detailed functional descriptions other than parametric performance is published in the

i960 VH Processor Developer’s Manual.

1.1

1.2

Solutions960^®Program

Intel’s Solutions960 program features a wide variety of development tools which support the i960

processor family. Many of these tools are developed by partner companies; some are developed by

Intel, such as profile-driven optimizing compilers. For more information on these products, contact

your local Intel representative.

Terminology

In this document, the following terms are used:

• local bus refers to the 80960VH’s internal local bus, not the PCI local bus.

• primary PCI bus is the 80960VH’s internal PCI bus which conforms to PCI SIG

specifications.

• 80960 core refers to the 80960JT processor which is integrated into the 80960VH.

1.3

Additional Information Sources

Intel documentation is available from your local Intel Sales Representative or Intel Literature

Sales.

Call 1-800-879-4683 or visit Intel’s website at http://www.intel.com.

Table 1. Related Documentation

Document Title

Order / Contact

i960^®VH Processor Developer’s Manual

i960® Jx Microprocessor User’s Guide

PCI Local Bus Specification, revision 2.2

I²C Peripherals for Microcontrollers

Intel Order # 273173

Intel Order # 272483

PCI Special Interest Group 1-800-433-5177

Philips Semiconductor

Preliminary Datasheet

80960VH

2.0

Functional Overview

As indicated in Figure 1, the 80960VH combines many features with the 80960JT to create a

highly integrated processor. Subsections following the figure briefly describe the main features; for

detailed functional descriptions, refer to the i960 VH Processor Developer’s Manual.

The PCI bus is an industry standard, high performance, low latency system bus that operates up to

132 Mbyte/sec. The 80960VH is fully compliant with the PCI Local Bus Specification, revision

2.2. Function 0 is the address translation unit.

The 80960VH, object code compatible with the i960 core processor, is capable of sustained

execution at the rate of one instruction per clock.

The local bus, a 32-bit multiplexed burst bus, is a high-speed interface to system memory and I/O.

A full complement of control signals simplifies the connection of the 80960VH to external

components. Physical and logical memory attributes are programmed via memory-mapped control

registers (MMRs), an extension not found on the i960 Kx, Sx or Cx processors. Physical and

logical configuration registers enable the processor to operate with all combinations of bus width

and data object alignment.

Figure 1. Product Name Functional Block Diagram

Local Memory

I²C Serial Bus

i960 JT

Memory

Core

Internal

Arbitration

I C Bus

Controller

Processor

Interface Unit

Local Bus

Primary ATU

Core and

Peripheral

Control Unit

Address

Translation

Unit

Two DMA

Channels

Messaging

Unit

Primary PCI Bus

Preliminary Datasheet

80960VH

2.1

Key Functional Units

2.1.1

DMA Controller

The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents

and 80960 local memory. Two separate DMA channels accommodate data transfers for the primary

PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable

only through the i960 core processor.

2.1.2

Address Translation Unit

The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960VH local

memory. The 80960VH has direct access to the PCI bus. The ATU supports transactions between

PCI address space and 80960VH address space.

Address translation is controlled through programmable registers accessible from the PCI interface

and the 80960 core. Dual access to registers allows flexibility in mapping the two address spaces.

2.1.3

2.1.4

Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 80960VH. It

uses interrupts to notify each system when new data arrives. The MU has two messaging

mechanisms. Each allows a host processor or external PCI device and the 80960VH to

communicate through message passing and interrupt generation. The two mechanisms are Message

Registers and Doorbell Registers.

Memory Controller

The Memory Controller allows direct control of external memory systems, including DRAM,

SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically

does not require external logic. It features programmable chip selects, a wait state generator and

byte parity. External memory can be configured as PCI addressable memory.

2.1.5

2.1.6

Core and Peripheral Unit

The Core and Peripheral Unit allows software to control the 80960VH through the primary PCI

bus. For example, the 80960 processor core and the 80960VH local bus can be reset via the PCI

bus.

I C Bus Interface Unit

The I C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and

slave device residing on the I C bus. The I C bus is a serial bus developed by Philips

Semiconductor consisting of a two pin interface. The bus allows the 80960VH to interface to other

I C peripherals and microcontrollers for system management functions. It requires a minimum of

hardware for an economical system to relay status and reliability information on the I/O subsystem

to an external device. For more information, see I C Peripherals for Microcontrollers (Philips

Semiconductor).

Preliminary Datasheet

80960VH

2.2

i960^®Core Features (80960JT)

The processing power of the 80960VH comes from the 80960JT processor core. The 80960JT is a

new, scalar implementation of the 80960 Core Architecture. Figure • shows a block diagram of the

80960JT Core processor.

Factors that contribute to the 80960 family core’s performance include:

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

• Efficient instruction pipeline minimizes pipeline break latency

• Register and resource scoreboarding allow overlapped instruction execution

• 128-bit register bus speeds local register caching

• 16 Kbyte two-way set-associative, integrated instruction cache

• 4 Kbyte direct-mapped, integrated data cache

• 1 Kbyte integrated data RAM delivers zero wait state program data

The 80960 core operates out of its own 32-bit address space, which is independent of the PCI

address space. The local bus memory can be:

• Made visible to the PCI address space

• Kept private to the 80960 core

• Allocated as a combination of the two

Figure 2. 80960JT Core Block Diagram

Control

32-bit buses

address / data

Physical Region

Configuration

P_CLK

PLL, Clocks,

Power Mgmt

Bus

Instruction Cache

Control Unit

Address/

Data Bus

16 Kbyte Two-Way Set

Bus Request

Queues

TAP

Boundary Scan

Controller

Instruction Sequencer

Two 32-Bit

Timers

Constants

Control

Interrupt

Port

Programmable

Interrupt Controller

8-Set

Local Register

Cache

Execution

and

Address

Generation

Memory

Interface

Unit

Memory-Mapped

Multiply

Divide

Unit

128

Unit

1 Kbyte

32-bit Addr

32-bit Data

Effective

Address

Global / Local

Data RAM

SRC1 SRC2 DST

4 Kbyte

Direct Mapped

Data Cache

3 Independent 32-Bit SRC1, SRC2, and DST Buses

Preliminary Datasheet

80960VH

2.2.1

Burst Bus

A 32-bit high-performance bus controller interfaces the 80960VH to external memory and

peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate

of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed.

Users may configure the 80960VH’s bus controller to match an application’s fundamental memory

organization. Physical bus width is programmable for up to eight regions. Data caching is

programmed through a group of logical memory templates and a defaults register. The Bus Control

Unit’s features include:

• Multiplexed external bus minimizes pin count

• 32-, 16- and 8-bit bus widths simplify I/O interfaces

• External ready control for address-to-data, data-to-data and data-to-next-address wait state

types

• Little endian byte ordering

• Unaligned bus accesses performed transparently

• Three-deep load/store queue decouples the bus from the 80960 core

Upon reset, the 80960VH conducts an internal self test. Before executing its first instruction, it

performs an external bus confidence test by performing a checksum on the first words of the

Initialization Boot Record.

2.2.2

2.2.3

Timer Unit

The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several

clock rates and generating interrupts. Each is programmed by use of the Timer Unit registers.

These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-

shot mode and auto-reload capabilities for continuous operation. Each timer has an independent

interrupt request to the 80960VH’s interrupt controller. The TU can generate a fault when

unauthorized writes from user mode are detected.

Priority Interrupt Controller

Low interrupt latency is critical to many embedded applications. As part of its highly flexible

interrupt mechanism, the 80960VH exploits several techniques to minimize latency:

• Interrupt vectors and interrupt handler routines can be reserved on-chip

• Register frames for high-priority interrupt handlers can be cached on-chip

• The interrupt stack can be placed in cacheable memory space

2.2.4

Faults and Debugging

The 80960VH employs a comprehensive fault model. The processor responds to faults by making

implicit calls to a fault handling routine. Specific information collected for each fault allows the

fault handler to diagnose exceptions and recover appropriately.

Preliminary Datasheet

80960VH

The processor also has built-in debug capabilities. Via software, the 80960VH may be configured

to detect as many as seven different trace event types. Alternatively, mark and fmark instructions

can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are

also available to trap on execution and data addresses.

2.2.5

2.2.6

2.2.7

On-Chip Cache and Data RAM

External memory subsystems often impose substantial wait state penalties. The 80960VH

integrates considerable storage resources on-chip to decouple CPU execution from the external bus

by including a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM.

Local Register Cache

The 80960VH rapidly allocates and deallocates local register sets during context switches. The

processor needs to flush a register set to the stack only when it saves more than seven sets to its

local register cache.

Test Features

The 80960VH incorporates numerous features that enhance the user’s ability to test both the

processor and the system to which it is attached. These features include ONCE (On-Circuit

Emulation) mode and Boundary Scan (JTAG).

The 80960VH provides testability features compatible with IEEE Standard Test Access Port and

Boundary Scan Architecture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins

(ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan

mechanism.

ONCE mode is useful for board-level testing. This feature allows a mounted 80960VH to

electrically “remove” itself from a circuit board. This mode allows system-level testing where a

remote tester can exercise the processor system.

The test logic does not interfere with component or system behavior and ensures that components

function correctly, and also the connections between various components are correct.

The JTAG Boundary Scan feature is an alternative to conventional “bed-of-nails” testing. It can

examine connections that might otherwise be inaccessible to a test system.

2.2.8

Memory-Mapped Control Registers

The 80960VH is compliant with 80960 family architecture and has the added advantage of

memory-mapped, internal control registers not found on the 80960Kx, Sx or Cx processors. This

feature provides software an interface to easily read and modify internal control registers.

Each memory-mapped, 32-bit register is accessed via regular memory-format instructions. The

processor ensures that these accesses do not generate external bus cycles.

Preliminary Datasheet

80960VH

2.2.9

Instructions, Data Types and Memory Addressing Modes

As with all 80960 family processors, the 80960VH instruction set supports several different data

types and formats:

• Bit

• Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

• Triple word (96 bits)

• Quad word (128 bits)

The 80960VH provides a full set of addressing modes for C and assembly:

• Two Absolute modes

• Five Register Indirect modes

• Index with displacement mode

• IP with displacement mode

Table 2 shows the available instructions.

Preliminary Datasheet

80960VH

Table 2. 80960VH Instruction Set

Data Movement

Arithmetic

Logical

Bit, Bit Field and Byte

Add

Subtract

Multiply

And

Set Bit

Divide

Not And

And Not

Clear Bit

Remainder

Not Bit

Load

Modulo

Alter Bit

Store

Shift

Exclusive Or

Not Or

Scan For Bit

Span Over Bit

Extract

Move

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

Conditional Add

Conditional Subtract

Rotate

Conditional Select

Load Address

Or Not

Nor

Modify

Exclusive Nor

Not

Scan Byte for Equal

Byte Swap

Nand

Comparison

Branch

Call/Return

Fault

Compare

Call

Conditional Compare

Compare and Increment

Compare and Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call Extended

Call System

Return

Conditional Fault

Synchronize Faults

Branch and Link

Processor

Management

Debug

Atomic

Flush Local Registers

Modify Arithmetic

Controls

Modify Trace Controls

Mark

Modify Process Controls

Halt

Atomic Add

Atomic Modify

Force Mark

System Control

Cache Control

Interrupt Control

Preliminary Datasheet

80960VH

3.0

Package Information

3.1

Package Introduction

The 80960VH is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array

package with five rows of ball connections in the outer area of the package. See Figure , (pg. 26).

Section 3.1.1, Functional Signal Definitions describes signal function. Section 3.1.2, 324-Lead

PBGA Package defines the signal and ball locations.

3.1.1

Functional Signal Definitions

Table 3 presents the legend for interpreting the Type Field in the following tables. Table 4 defines

signals associated with the bus interface. Table 5 defines signals associated with basic control and

test functions. Table 6 defines signals associated with the Interrupt Unit. Table 7 defines PCI

signals. Table 8 defines Memory Controller signals. Table 9 defines DMA, and I C signals. Table

10 defines clock signals.

Table 3. Signal Type Definition

Symbol

Description

Input signal only.

Output signal only.

I/O

–

Signal can be either an input or output.

Open Drain signal.

Signal must be connected as described.

Synchronous. Inputs must meet setup and hold times relative to P_CLK.

S (...)

A (...)

S(E) Edge sensitive input

S(L) Level sensitive input

Asynchronous. Inputs may be asynchronous relative to P_CLK.

A(E) Edge sensitive input

A(L) Level sensitive input

While the P_RST# signal is asserted, the signal:

R(1) is driven to V_CC

R(0) is driven to V_SS

R(Q) is a valid output

R(Z) Floats

R (...)

R(H) is pulled up to V_CC

R(X) is driven to an unknown state

Preliminary Datasheet

80960VH

Table 3. Signal Type Definition

Symbol

Description

While the is in the hold state, the signal:

H(1) is driven to V_CC

H(0) is driven to V_SS

H (...)

H(Q) Maintains previous state or continues to be a valid output

H(Z) Floats

While the 80960VH is halted, the signal:

P(1) is driven to V_CC

P(0) is driven to V_SS

P(Q) Maintains previous state or continues to be a valid output

P (...)

K (...)

While the PCI Bus is in park mode, the pin:

K(Z) Floats

K(Q) Maintains previous state or continues to be a valid output

Table 4. Signal Descriptions (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-

bit data to and from memory. During an address (T_a) cycle, bits 2-31 contain a

physical word address (bits 0-1 indicate SIZE; see below). During a data (T )

cycle, read or write data is present on one or more contiguous bytes,

comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations,

unused signals are driven to determinate values.

SIZE, which comprises bits 0-1 of the AD lines during a T_acycle, specifies the

number of data transfers during the bus transaction on the local bus.

When the DMA or ATUs initiate data transfers, transfer size shown below is

not valid.

I/O

S(L)

R(Z)

H(Z)

P(Q)

AD31:0

AD1

AD0

Bus Transfers

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the 80960VH enters Halt mode and the previous bus operation was:

•

write — AD31:2 are driven with the last data value on the AD bus.

read — AD31:2 are driven with the last address value on the AD bus.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ADDRESS STROBE indicates a valid address and the start of a new bus

access. The processor asserts ADS# for the entire T_acycle. External bus

control logic typically samples ADS# at the end of the cycle.

R(1)

H(Z)

P(1)

ADS#

ALE

ADDRESS LATCH ENABLE indicates the transfer of a physical address.

ALE is asserted during a T_acycle and deasserted before the beginning of the

R(0)

H(Z)

P(0)

state. It is active HIGH and floats to a high impedance state during a hold

cycle (T ).

BURST LAST indicates the last transfer in a bus access. BLAST# is asserted

in the last data transfer of burst and non-burst accesses. BLAST# remains

active while wait states are detected via the LRDYRCV# or RDYRCV# signal

on the memory controller. BLAST# becomes inactive after the final data

transfer in a bus cycle. BLAST# has a weak internal pullup which is active

during reset to ensure normal operation when the signal is not connected.

R(H)

H(Z)

P(1)

BLAST#

0 = Last Data Transfer

1 = Not the Last Data Transfer

Preliminary Datasheet

80960VH

Table 4. Signal Descriptions (Sheet 2 of 4)

NAME

TYPE

DESCRIPTION

BYTE ENABLES select which of up to four data bytes on the bus participate

in the current bus access. Byte enable encoding depends on the bus width of

the memory region accessed:

32-bit bus:

BE3# enables data on AD31:24

BE2# enables data on AD23:16

BE1# enables data on AD15:8

BE0# enables data on AD7:0

16-bit bus:

BE3# becomes Byte High Enable (enables data on AD15:8)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

R(1)

H(Z)

P(1)

(increments with the assertion of LRDY# or RDYRCV#)

BE0# becomes Byte Low Enable (enables data on AD7:0)

BE3:0#

8-bit bus:

BE3# is not used (state is high)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

(increments with the assertion of LRDY# or RDYRCV#)

BE0# becomes Address Bit 0 (A0)

(increments with the assertion of LRDY# or RDYRCV#)

The processor asserts byte enables, byte high enable and byte low enable

during T_a. Since unaligned bus requests are split into separate bus

transactions, these signals do not toggle during a burst (32-bit bus only) from

the i960 core processor; they do toggle for DMA and ATU cycles. They remain

active through the last T_dcycle.

DATA ENABLE indicates data transfer cycles during a bus access. DEN# is

asserted at the start of the first data cycle in a bus access and deasserted at

the end of the last data cycle. DEN# is used with DT/R# to provide control for

data transceivers connected to the data bus. DEN# has a weak internal pullup

which is active during reset to ensure normal operation when the signal is not

connected.

R(H)

H(Z)

P(1)

DEN#

0 = Data Cycle

1 = Not a Data Cycle

DATA/CODE/RESET_MODE indicates that a bus access is a data access or

an instruction access. D/C# has the same timing as W/R#.

0 = Instruction Access

1 = Data Access

The RST_MODE# signal is sampled at primary PCI bus reset to determine

whether the 80960 core is to be held in reset. When RST_MODE# is high, the

80960VH begins initialization immediately following the deassertion of

P_RST#. When RST_MODE# is low, the 80960 core remains in reset until the

80960 core reset bit is cleared in the Reset/Retry control register. This signal

has a weak internal pullup that is active during reset to ensure normal

operation when the signal is left unconnected.

I/O

D/C#/

RST_MODE#

R(H)

H(Z)

P(Q)

0 = RST_MODE enabled

1 = RST_MODE not enabled

While the 80960 core is in reset, all peripherals may be accessed from the

primary PCI bus depending on the status of the WIDTH/HLTD1/RETRY/

signal.

DATA TRANSMIT/RECEIVE indicates the direction of data transfer to and

from the address/data bus. It is low during T_aand T_w/T cycles for a read; it is

high during T_aand T_w/T cycles for a write. DT/R# never changes state when

DEN# is asserted.

R(0)

H(Z)

P(Q)

DT/R#

0 = Receive

1 = Transmit

Preliminary Datasheet

80960VH

Table 4. Signal Descriptions (Sheet 3 of 4)

NAME

TYPE

DESCRIPTION

BUS LOCK indicates that an atomic read-modify-write operation is in

progress. The LOCK# output is asserted in the first clock of an atomic

operation and deasserted in the last data transfer of the sequence. The

processor does not grant HOLDA while asserting LOCK#. This prevents

external agents from accessing memory involved in semaphore operations.

I/O

0 = Atomic Read-Modify-Write in Progress

1 = No Atomic Read-Modify-Write in Progress

S(L)

R(H)

H(Z)

P(Q)

LOCK#/ONCE#

ONCE MODE: The processor samples the ONCE input during reset. When

ONCE# is asserted LOW at the end of reset, the processor enters ONCE

mode, stops all clocks and floats all output signals. This signal has a weak

internal pullup which is active during reset to ensure normal operation when

the signal is not connected.

0 = ONCE Mode Enabled

1 = ONCE Mode Not Enabled

LOCAL READY/RECOVER, generated by the 80960VH’s memory controller

unit, is an output version of the READY/RECOVER (RDYRCV#) signal. Refer

to the RDYRCV# signal description.

SELF TEST enables or disables the processor’s internal self-test feature at

initialization. STEST is examined at the end of P_RST#. When STEST is

asserted, the processor performs its internal self-test and the external bus

confidence test. When STEST is deasserted, the processor performs only the

external bus confidence test. This signal has a weak internal pullup which is

active during reset to ensure normal operation.

I/O

LRDYRCV#/

STEST

R(H)

H(Q)

P(Q)

0 = Self Test Disabled

1 = Self Test Enabled

HOLD is a request from an external bus master to acquire the bus. When the

processor receives HOLD and grants bus control to another master, it asserts

HOLDA, floats the address/data and control lines and enters the T state.

When HOLD is deasserted, the processor deasserts HOLDA and enters

HOLD

either the T or T_astate, resuming control of the address/data and control

S(L)

lines. See Figure , (pg. 61).

0 = No Hold Request

1 = Hold Requested

HOLD ACKNOWLEDGE indicates to an external bus master that the

processor has relinquished bus control. The processor can grant HOLD

requests and enter the T_hstate and while halted as well as during regular

operation. See Figure , (pg. 61).

R(0)

H(1)

P(Q)

HOLDA

0 = No Hold Acknowledged

1 = Hold Acknowledged

READY/RECOVER is only used in systems that use an external memory

controller (and do not use the 80960VH’s memory controller unit). This signal

indicates that data on AD lines can be sampled or removed. When RDYRCV#

is not asserted during a T cycle, the T_dcycle extends to the next cycle by

inserting a wait state (T ).

0 = Sample Data

1 = Do Not Sample Data

RDYRCV#

RDYRCV# has an alternate function during the recovery (T_r) state. The

processor continues to insert recovery states until it samples the signal HIGH.

This gives slow external devices more time to float their buffers before the

processor drives addresses.

S(L)

0 = Insert Wait States

1 = Recovery Complete

When using the internal memory controller, connect this signal to V_CCthrough

a 2.7 KΩ resistor.

Preliminary Datasheet

80960VH

Table 4. Signal Descriptions (Sheet 4 of 4)

NAME

TYPE

DESCRIPTION

WRITE/READ specifies during a T_acycle whether the operation is a write or

read. It is latched on-chip and remains valid during T cycles.

R(0)

H(Z)

P(Q)

W/R#

0 = Read

1 = Write

WIDTH denotes the physical memory attributes for a bus transaction in

conjunction with WIDTH/HLTD1/RETRY:

WIDTH/HLTD1/RETRY WIDTH/HLTD0

8 Bits Wide

16 Bits Wide

32 Bits Wide

Undefined

I/O

WIDTH/

HLTD0

R(H)

H(Z)

P(Q)

WIDTH/HLTD0 For proper operation, do not connect this signal to ground.

This signal has a weak internal pullup which is active during reset to ensure

normal operation.

HLTD0 signal name has no function in the 80960VH; the signal name is

included for 80960JT naming convention compatibility.

WIDTH denotes the physical memory attributes for a bus transaction in

conjunction with the WIDTH/HLTD0 signal. Refer to description above.

RETRY is sampled at primary PCI bus reset to determine when the primary

PCI interface is disabled. When high, the Primary PCI interface disables PCI

configuration cycles by signaling a RETRY until the Reset/Retry Control

PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY

has a weak internal pullup which is active during reset to ensure normal

operation when the signal is not connected. When the RST_MODE# pin is

asserted, RETRY is internally forced low [inactive] regardless of its external

state.

I/O

WIDTH/

HLTD1/

RETRY

R(H)

H(Z)

P(Q)

HLTD1 signal name has no function in the 80960VH; the signal name is

included for 80960JT naming convention compatibility.

Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

FAIL indicates a failure of the processor’s built-in self-test performed

during initialization. FAIL# is asserted immediately upon reset and toggles

during self-test to indicate the status of individual tests:

•

When self-test passes, the processor deasserts FAIL# and

commences operation from user code.

R(0)

FAIL#

H(Q)

•

When self-test fails, the processor asserts FAIL# and then stops

executing.

0 = Self Test Failed

1 = Self Test Passed

L_RST#

TCK

LOCAL BUS RESET notifies external devices that the local bus has reset.

TEST CLOCK is a CPU input that provides the clocking function for

IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data

are clocked into the processor on the rising edge; data is clocked out of the

processor on the falling edge.

TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on

the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the

Test Access Port. This signal has a weak internal pullup to ensure normal

operation.

TDI

S(L)

Preliminary Datasheet

80960VH

Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on

the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the

Test Access Port. At other times, TDO floats.

R(Q)

H(Q)

P(Q)

TDO

TMS

TEST MODE SELECT is sampled at the rising edge of TCK to select the

operation of the test logic for IEEE 1149.1 Boundary Scan testing. This

signal has a weak internal pullup to ensure normal operation.

S(L)

TEST RESET asynchronously resets the Test Access Port (TAP) controller

function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the

Boundary Scan feature, connect a pulldown resistor (1.5 KΩ) between this

signal and V_SS. When TAP is not used, this signal must be connected to

TRST#

V_SS; however, no resistor is required. The signal has a weak internal pullup

A(L)

which must be overcome during reset to ensure normal operation.

NOTE: The system must ensure that TRST# is asserted after power-up to

put the TAP controller in a known state. Failure to do so may

cause improper processor operation.

LCD INITIALIZATION is a static signal used to initialize the internal logic of

the LCD960 debugger. This signal has an internal pullup for normal

operation.

LCDINIT#

V_CC

–

POWER. Connect to a 3.3 Volt power board plane.

5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the

5 V-tolerant I/O buffers. Connect this signal to +5 V for use with signals

which exceed 3.3 V. When all inputs are from 3.3 V components, connect

this signal to 3.3 V.

V_CC5REF

–

V_SS

–

GROUND. Connect to a V_SSboard plane.

N.C.

NO CONNECT. Do not make electrical connections to these balls.

PLL POWER. For external connection to a 3.3 V V_CCboard plane. Power

to PLLs requires external filtering. See Section 4.2, VCCPLL Pin

Requirements.

VCCPLL2:1

Preliminary Datasheet

80960VH

Table 6. Interrupt Unit Signal Descriptions

NAME

TYPE

DESCRIPTION

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to

occur. NMI# is the highest priority interrupt source and is level-detect. When

NMI#

A(L)

NMI# is unused, it is recommended that you connect it to V_CC

EXTERNAL INTERRUPT. External devices use this signal to request an

interrupt service. These signals operate in dedicated mode, where each signal

is assigned a dedicated interrupt level.

The XINT3:0# signals can be directed as follows:

External Int.

XINT0#

Primary PCI

P_INTA#

80960 Core Processor

XINT0#

XINT3:0#

A(L)

XINT1#

P_INTB#

P_INTC#

P_INTD#

XINT1#

XINT2#

XINT3#

EXTERNAL INTERRUPT. External devices use this signal to request an

interrupt service. These signals operate in dedicated mode, where each signal

is assigned a dedicated interrupt level.

XINT7:4#

A(L)

NOTE:

1. PCI signal functions are summarized in this data sheet. Refer to the PCI Local Bus Specification, revision 2.2 for

a more complete definition.

Table 7. PCI Signal Descriptions (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION¹

I/O

K(Q)

R(Z)

PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address and

data bus.

P_AD31:0

I/O

K(Q)

R(Z)

PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are multiplexed

on the same PCI signals. During an address phase, P_C/BE3:0# define the

bus command. During a data phase, P_C/BE3:0# are used as byte enables.

P_C/BE3:0#

P_DEVSEL#

P_FRAME#

I/O

PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has

successfully decoded the address. As an input, it indicates whether or not an

agent has been selected.

R(Z)

I/O

PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning

and duration of an access on the Primary PCI bus.

R(Z)

PRIMARY PCI BUS GRANT indicates to the agent that access to the bus has

been granted. This is a point-to-point signal.

P_GNT#

P_IDSEL

R(Z)

PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the 80960VH

during a Configuration Read or Write command on the primary PCI bus.

S(L)

PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and

deassertion of P_INTx# is asynchronous to P_CLK. A device asserts its

P_INTx# line when requesting attention from its device driver. Once the

P_INTx# signal is asserted, it remains asserted until the device driver clears

the pending request. P_INTx# Interrupts are level sensitive.

R(Z)

P_INT[A:D]#

I/O

R(Z)

PRIMARY PCI BUS INITIATOR READY indicates the initiating agent’s (bus

master’s) ability to complete the current data phase of the transaction.

P_IRDY#

NOTE:

1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, revision 2.2 for

a more complete definition.

Preliminary Datasheet

80960VH

Table 7. PCI Signal Descriptions (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION¹

PRIMARY PCI BUS LOCK indicates an atomic operation that may require

multiple transactions to complete.

P_LOCK#

S(L)

I/O

K(Q)

R(Z)

PRIMARY PCI BUS PARITY. This signal ensures even parity across

P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.

P_PAR

I/O

R(Z)

PRIMARY PCI BUS PARITY ERROR is used for reporting data parity errors

during all PCI transactions except a special cycle.

P_PERR#

P_REQ#

K(Q)

R(Z)

PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent desires

use of the bus. This is a point to point signal.

PRIMARY RESET brings 80960VH to a consistent state. When P_RST# is

asserted:

•

PCI output signals are driven to a known consistent state.

PCI bus interface output signals are three-stated.

open drain signals such as P_SERR# are floated.

S_RST# asserts.

P_RST#

A(L)

P_RST# may be asynchronous to P_CLK when asserted or deasserted.

Although asynchronous, deassertion must be guaranteed to be a clean,

bounce-free edge.

I/O

R(Z)

PRIMARY PCI BUS SYSTEM ERROR reports address and data parity errors

on the special cycle command, or any other system error where the result

would be catastrophic.

P_SERR#

P_STOP#

I/O

PRIMARY PCI BUS STOP indicates that the current target is requesting the

master to stop the current transaction on the primary PCI bus.

R(Z)

I/O

PRIMARY PCI BUS TARGET READY indicates the target agent's (selected

P_TRDY#

device's) ability to complete the current data phase of the transaction.

R(Z)

NOTE:

1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, revision 2.2 for

a more complete definition.

Preliminary Datasheet

80960VH

Table 8. Memory Controller Signal Descriptions (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

COLUMN ADDRESS STROBE signals are used for DRAM accesses

and are asserted when the MA11:0 signals contain a valid column

address. CAS7:0# signals are asserted during refresh.

Non-Interleaved Operation:

CAS0#,CAS4# = BE0#

CAS1#,CAS5# = BE1#

CAS2#,CAS6# = BE2#

CAS3#,CAS7# = BE3#

lane access

R(1)

H(Q)

P(Q)

CAS7:0#

Interleaved Operation:

CAS0# = BE0#

CAS1# = BE1#

CAS2# = BE2#

CAS3# = BE3#

CAS4# = BE0#

CAS5# = BE1#

CAS6# = BE2#

CAS7# = BE3#

Even leaf lane access

Odd leaf lane access

CHIP ENABLE signals indicate an access to one of the two SRAM/

FLASH/ ROM memory banks. CE0# and CE1# are never asserted at the

same time. These signals are valid during the entire memory operation.

CE0# is asserted for accesses to memory bank 0. CE1# is asserted for

accesses to memory bank 1.

R(1)

H(Q)

P(Q)

CE1:0#

DRAM ADDRESS LATCH ENABLE signals support external address

demultiplexing of the MA11:0 address lines for interleaved DRAM

systems. Use these to directly interface to ‘373’ type latches. These

signals are only valid for accesses to interleaved memory systems.

DALE0 is asserted during a valid even leaf address. DALE1 is asserted

during a valid odd leaf address.

R(0)

H(Q)

P(Q)

DALE1:0

DATA PARITY carries the parity information for DRAM accesses. Each

parity bit corresponds to a group of 8 data bus signals as follows:

DP0 — AD7:0

DP1 — AD15:8

DP2 — AD23:16

DP3 — AD31:24

I/O

The memory controller generates parity information for local bus writes

during data cycles. During read data cycles, the memory controller

checks parity and provides notification of parity errors on the clock

following the data cycle.

R(X)

H(Q)

P(Q)

DP3:0

Parity checking and polarity are user-programmable. Parity generation

and checking are valid only for data lines that have their associated

enable bits asserted.

DRAM WRITE ENABLE signals distinguish between read and write

accesses to DRAM. DWE1:0# lines are asserted for writes and

deasserted for reads. CAS7:0# determine valid bytes lanes during the

access. These two outputs are functionally equivalent for all DRAM

accesses; these provide increased drive capability for heavily loaded

systems.

R(1)

H(Q)

P(Q)

DWE1:0#

LEAF1:0#

LEAF ENABLE signals control the data output enables of the memory

system during an interleaved DRAM read access. Use these to directly

interface to either DRAM or transceiver output enable signals. LEAF0# is

asserted during an even leaf access. LEAF1# is asserted during an odd

leaf access.

R(1)

H(Q)

P(Q)

Preliminary Datasheet

80960VH

Table 8. Memory Controller Signal Descriptions (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

MULTIPLEXED ADDRESS signals are multi-purpose depending on the

device that is selected.

For memory banks 0 and 1, these signals output address bits A13:2.

These address bits are incremented for each data transfer of a burst

access.

R(X)

H(Q)

P(Q)

MA11:0

For DRAM bank, these signals output the row/column multiplexed

address bits 11:0. The relationship between the AD31:0 lines and the

MA11:0 lines depends on the bank size, type and arrangement of the

DRAM that is accessed.

MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH

devices. The MWE’s rising edge strobes valid data into these devices.

R(1)

H(Q)

P(Q)

MWE0# is asserted for writes to the BE0# lane

MWE1# is asserted for writes to the BE1# lane

MWE2# is asserted for writes to the BE2# lane

MWE3# is asserted for writes to the BE3# lane

MWE3:0#

RAS3:0#

ROW ADDRESS STROBE signals are used for DRAM accesses and

are asserted when the MA11:0 signals contain a valid row address.

RAS3:0# always deasserts after the last data transfer in a DRAM

access.

Non-Interleaved Operation:

RAS0# = Bank0 access

RAS1# = Bank1 access

RAS2# = Bank2 access

RAS3# = Bank3 access

R(1)

H(Q)

P(Q)

Interleaved Operation:

RAS0,2# = Even leaf

RAS1,3# = Odd leaf

Table 9. DMA, I C Units Signal Descriptions

NAME

TYPE

DESCRIPTION

DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this

signal to indicate (1) it can receive new data from an external device or (2) it

has data to send to an external device. This signal has a weak internal pullup

which is active during reset to ensure normal operation.

R(H)

H(Q)

P(Q)

DACK#

DMA DEMAND MODE REQUEST External devices use this signal to

indicate (1) new data is ready for transfer to the DMA controller or (2) buffers

are available to receive data from the DMA controller.

DREQ#

SCL

S(L)

I/O

R(Z)

H(Q)

P(Q)

I²C CLOCK provides synchronous I²C bus operation.

I/O

R(Z)

H(Q)

P(Q)

SDA

I²C DATA used for data transfer and arbitration on the I²C bus.

R(1)

H(Q)

P(Q)

WAIT is an output that allows the DMA controller to insert wait states during

DMA accesses to an external memory system.

WAIT#

Preliminary Datasheet

80960VH

Table 10. Clock Related Signals

NAME

TYPE

DESCRIPTION

SYNCHRONOUS PCI BUS CLOCK Provides the timing for all primary PCI

transactions and is the clock source for all internal units. All input/output timings

are relative to P_CLK.

P_CLK

CLOCK MODE are used to select the mode of operation in terms of the 80960

local bus / PCI bus vs. the internal 80960 processor core. These signals are

internally pulled high. This causes the 80960 processor core to run in DX mode

after reset. In this mode, the 80960 processor core speed can be altered by

using the Core Select Register (CSR).

CLKMODE1:0#

00 - DX4 Mode

01 - DX2 Mode

10 - DX Mode

11 - Select Speed via PCI Bus

Preliminary Datasheet

80960VH

3.1.2

324-Lead PBGA Package

Figure 3. 324-Plastic Ball Grid Array Top and Side View

Pin #1

Corner

D₁

30˚

Pin #1 I.D.

E₁

Seating

Plate

Top View

Side View

Note: All Dimensions are in Millimeters

A4628-01

Preliminary Datasheet

80960VH

Figure 4. 324-Plastic Ball Grid Array (Top View)

Pin #1

Corner

10 11 12 13 14 15 16 17 18 19 20

325 Balls

20 x 20

Matrix

1.0

3 places

Top View

A4630-01

Table 11. PBGA 324 Package Dimensions

PBGA Package Dimensions

Min

Max

N (# of balls)

324

A₁

A₂

D/E

D₁/E₁

S₁

2.14

0.50

2.52

0.70

1.12

1.22

26.80

23.75

27.20

24.25

1.44 Ref

1.27

0.60

0.52

0.90

0.60

Preliminary Datasheet

80960VH

Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet 1 of 3)

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

A10

V_SS

WAIT#

P_AD3

V_CC

B12

B13

B14

B15

B16

B17

B18

B19

B20

P_LOCK#

V_CC

CLKMODE1#

V_SS

E14

E15

E16

E17

E18

E19

E20

P_C/BE2#

V_SS

P_AD2

V_CC

P_C/BE0#

V_SS

P_AD21

V_CC

P_AD7

V_SS

P_AD10

V_CC

P_AD24

V_SS

P_AD31

MA6

V_SS

D10

D11

D12

V_CC

P_AD13

P_AD14

P_AD28

DP3

V_CC

MA11

CLKMODE0

A11

P_PAR

D13

V_SS

V_CC

A12

A13

A14

A15

A16

A17

A18

A19

A20

P_PERR#

V_CC

DACK#

P_AD1

P_AD4

P_AD6

P_AD8

P_AD11

D14

D15

D16

D17

D18

D19

D20

P_AD18

V_CC

P_TRDY#

V_SS

P_AD26

V_SS

F14

F15

F16

F17

F18

F19

F20

V_CC

P_AD17

P_AD22

P_IDSEL

P_C/BE3#

V_SS

P_AD30

V_CC

P_REQ#

V_SS

C10

C11

P_AD15

P_SERR#

MA9

DP0

P_GNT#

DREQ#

V_SS

C12 P_DEVSEL#

DP2

C13

C14

C15

C16

C17

C18

C19

C20

P_IRDY#

P_AD16

P_AD20

P_AD23

P_AD25

P_AD27

P_AD29

V_CC

MA5

P_AD0

V_CC

MA7

MA10

P_AD5

V_SS

V_CC

P_AD9

V_CC

G16

G17

G18

G19

E10

E11

E12

P_C/BE1#

P_STOP#

P_FRAME#

P_RST#

P_INTD#

V_CC

P_AD12

V_SS

B10

DP1

Preliminary Datasheet

80960VH

Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet 2 of 3)

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

B11

H16

H17

H18

H19

H20

V_SS

V_CC

K11

K12

K16

K17

K18

K19

K20

V_CC

V_SS

E13

M17

M18

M19

M20

P_AD19

BE3#

BE2#

BE1#

V_CC

G20

VCCPLL2

V_CC

V_SS

R15

R16

R17

R18

R19

R20

V_CC

MA4

V_SS

BE0#

V_CC

MA8

P_INTC#

V_SS

DT/R#

V_SS

V_CC

AD23

V_SS

V_CC

W/R#

LEAF0#

V_SS

MWE0#

V_SS

P_INTB#

V_CC

CAS4#

CAS1#

RAS3#

RAS0#

CAS5#

V_CC

CE1#

V_CC

N16

N17

N18

N19

N20

MA0

MA1

MA2

MA3

V_CC

V_SS

CE0#

V_SS

AD30

V_CC

L10

L11

V_SS

V_CC

XINT0#

FAIL#

V_SS

CAS7#

D/C#/

RST_MODE#

V_SS

L12

V_SS

V_CC

J10

J11

J12

J16

J17

J18

J19

J20

V_SS

L16

L17

L18

L19

L20

AD31

V_CC

CAS6#

CAS3#

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

RDYRCV#

V_SS

ALE

V_CC

ADS#

BLAST#

SDA

V_SS

P15

P16

P17

P18

P19

P20

V_CC

AD6

DEN#

DWE1#

DWE0#

MWE3#

MWE2#

MWE1#

V_SS

TCK

AD22

AD27

AD29

VCC5REF

V_SS

TDI

SCL

P_INTA#

LEAF1#

V_SS

AD17

AD20

AD24

AD28

CAS0#

V_CC

DALE0

V_CC

V_SS

M10

M11

M12

V_SS

CAS2#

V_CC

DALE1

V_SS

RAS1#

Preliminary Datasheet

80960VH

Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet 3 of 3)

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

K10

V_SS

V_CC

M16

V13

V14

V15

V16

V17

V18

V19

V20

AD26

AD5

V_CC

V_SS

V_CC

AD8

XINT5#

XINT3#

XINT1#

V_CC

WIDTH/HLTD0

V_SS

TMS

AD12

AD13

AD16

AD19

AD21

V_CC

U10

U11

U12

V_CC

V_SS

V_CC

LCDINIT#

HOLD

V_CC

LRDYRCV#/

STEST

U13

V_SS

U14

U15

U16

U17

U18

U19

U20

AD9

V_CC

V_SS

V_CC

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

VCCPLL1

AD1

V_CC

AD4

V_SS

LRST#

V_SS

AD7

AD18

V_CC

TRST#

V_SS

V_CC

AD25

RAS2#

XINT7#

XINT6#

XINT4#

XINT2#

V_CC

AD10

NMI#

V_SS

W10

W11

W12

W13

AD14

AD15

V_SS

AD3

V_CC

V6 WIDTH/HLTD1/RETRY W14

V_CC

LOCK#/ONCE#

HOLDA

TDO

W15

W16

W17

W18

W19

W20

V_SS

AD11

V_CC

V10

V11

V12

NOTE:

AD0

V_SS

AD2

P_CLK

1. Do not connect any external logic to balls marked NC (no connect balls).

Preliminary Datasheet

80960VH

Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet 1 of 3)

Signal

Ball

Signal

Ball

Signal

Ball

Signal

Ball

AD0

AD1

V11

Y11

V12

W12

Y12

V13

T13

Y13

V14

U14

Y16

W17

V16

V17

Y18

Y19

V18

T17

U18

V19

T18

V20

P17

R18

T19

U20

M16

P18

T20

P19

N18

AD31

ADS#

L16

J16

L18

K16

M19

M18

M17

J17

DWE0#

DWE1#

FAIL#

NMI#

AD2

ALE

AD3

BE0#

HOLD

AD4

BE1#

HOLDA

LCDINIT#

LEAF0#

LEAF1#

LOCK#/ONCE#

LRDYRCV#/STEST

LRST#

MA0

E14

E15

E16

E17

E18

E19

AD5

BE2#

AD6

BE3#

AD7

BLAST#

CAS0#

CAS1#

CAS2#

CAS3#

CAS4#

CAS5#

CAS6#

CAS7#

CE0#

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

F16

MA1

MA2

MA3

G16

N16

MA4

D20

MA5

CE1#

MA6

P16

CLKMODE0#

CLKMODE1#

D/C#/RST_MODE#

DACK#

DALE0

DALE1

DEN#

MA7

MA8

R16

MA9

MA10

MA11

T11

T16

MWE0#

MWE1#

MWE2#

MWE3#

L20

DP0

W16

Y17

DP1

DP2

DP3

DREQ#

DT/R#

P_AD0

P_AD1

K18

Preliminary Datasheet

80960VH

Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet 2 of 3)

Signal

Ball

Signal

Ball

Signal

Ball

Signal

Ball

P_AD2

P_AD3

P_C/BE1#

P_C/BE2#

P_C/BE3#

P_CLK

E10

B14

A19

W20

C12

E12

F20

A18

J20

H18

H16

G18

C13

B12

A11

A12

F18

G17

C11

E11

A14

TMS

TRST#

V_CC

V15

Y14

V_CC

N20

P15

P_AD4

P_AD5

A13

P_AD6

P_DEVSEL#

P_FRAME#

P_GNT#

P_IDSEL

P_INTA#

P_INTB#

P_INTC#

P_INTD#

P_IRDY#

P_LOCK#

P_PAR

P_AD7

R15

R17

P_AD8

B13

B17

P_AD9

P_AD10

P_AD11

P_AD12

P_AD13

P_AD14

P_AD15

P_AD16

P_AD17

P_AD18

P_AD19

P_AD20

P_AD21

P_AD22

P_AD23

P_AD24

P_AD25

P_AD26

P_AD27

P_AD28

P_AD29

P_AD30

P_AD31

P_C/BE0#

U10

U11

U15

U19

W13

D10

D11

D15

D19

A10

C10

C14

A16

D14

E13

C15

B16

A17

C16

B18

C17

D16

C18

B20

C19

D18

E20

P_PERR#

P_REQ#

P_RST#

P_SERR#

P_STOP#

P_TRDY#

RAS0#

F14

F15

F17

D12

G19

M20

RAS1#

H19

H20

RAS2#

RAS3#

RDYRCV#

SCL

T10

J19

J18

T14

T15

V10

K17

U12

U16

W14

W18

SDA

L17

TCK

TDI

TDO

N19

Preliminary Datasheet

80960VH

Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet 3 of 3)

Signal

Ball

Signal

Ball

Signal

Ball

Signal

Ball

V_CC

C20

V_SS

W10

W11

W15

W19

V_CC

T12

P20

Y10

G20

K10

K11

K12

K19

V_SS

VCC5REF

VCCPLL1

VCCPLL2

V_SS

Y15

Y20

K20

V_SS

A15

A20

L10

L11

L12

L19

W/R#

V_SS

WAIT#

V_SS

WIDTH/HLTD0

WIDTH/HLTD1/RETRY

XINT0#

XINT1#

XINT2#

XINT3#

XINT4#

XINT5#

XINT6#

XINT7#

V_SS

B10

B11

B15

B19

V_SS

M10

M11

M12

V_SS

N17

V_SS

D13

D17

V_SS

R19

R20

V_SS

F19

V_SS

H17

V_SS

U13

U17

V_SS

J10

J11

J12

V_SS

NOTE:

1. Do not connect any external logic to balls marked NC (no connect balls).

Preliminary Datasheet

80960VH

3.2

Package Thermal Specifications

The device is specified for operation when T (case temperature) is within the range of 0° C to

95° C. Case temperature may be measured in any environment to determine whether the processor

is within specified operating range. Measure the case temperature at the center of the top surface,

opposite the ballpad.

3.2.1

Thermal Specifications

This section defines the terms used for thermal analysis.

3.2.1.1

Ambient Temperature

Ambient temperature, T , is the temperature of the ambient air surrounding the package. In a

system environment, ambient temperature is the temperature of the air upstream from the package.

3.2.1.2

Case Temperature

To ensure functionality and reliability, the device is specified for proper operation when the case

temperature, T , is within the specified range in Table 16, Operating Conditions (pg. 36).

When measuring case temperature, attention to detail is required to ensure accuracy. If a

thermocouple is used, then calibrate it before taking measurements. Errors may result when the

measured surface temperature is affected by the surrounding ambient air temperature. Such errors

may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by

radiation, or conduction through thermocouple leads.

To minimize measurement errors:

• Use a 35 gauge K-type thermocouple or equivalent.

• Attach the thermocouple bead or junction to the package top surface at a location

corresponding to the center of the die (). The center of the die gives a more accurate

measurement and less variation as the boundary condition changes.

• Attach the thermocouple bead or junction at a 90° angle by an adhesive bond (such as thermal

epoxy or heat-tolerant tape) to the package top surface as shown in .

Figure 5. Thermocouple Attachment

Thermocouple Wire

Epoxy Fillet

Thermocouple Bead

Preliminary Datasheet

80960VH

3.2.1.3

3.2.2

Thermal Resistance

The thermal resistance value for the case-to-ambient, θ , is used as a measure of the cooling

solution’s thermal performance.

Thermal Analysis

Table 14 lists the case-to-ambient thermal resistances of the 80960VH for different air flow rates

without a heat sink.

To calculate T , the maximum ambient temperature to conform to a particular case temperature:

T = T - P (θ )

Compute P by multiplying I and V . Values for θ and θ are given in Table 14.

Junction temperature (T ) is commonly used in reliability calculations. T can be calculated from

(thermal resistance from junction to case) using the following equation:

T = T + P (θ )

Similarly, when T is known, the corresponding case temperature (T ) can be calculated as

follows:

T = T + P (θ

)

The θ (Junction-to-Ambient) for this package is currently estimated at 26.54° C/Watt with no

airflow.

= θ + θ

JC CA

Table 14. 324-Lead PBGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

100

200

400

600

800

(0)

(0.50)

(1.01)

(2.03)

(3.04)

(4.06)

θ_JC(Junction-to-Case)

1.36

θ_CA(Case-to-Ambient)

Without Heatsink

25.18

20.30

18.29

16.57

15.55

14.75

θ_JA

θ_CA

θ_JC

NOTE:

1. This table applies to a PBGA device soldered directly onto a board.

Preliminary Datasheet

80960VH

4.0

Electrical Specifications

Table 15. Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature

Case Temperature Under Bias

Supply Voltage wrt. V_SS

–55° C to + 125° C

0° C to + 95° C

–0.5 V to + 4.6 V

–0.5 V to + 6.5 V

–0.5 V to V_CC+ 0.5 V

Supply Voltage wrt. V_SSon V_CC5

Voltage on Any Ball wrt. V_SS

NOTICE: This data sheet contains information on products in the design phases of development. The

specifications are subject to change without notice. Contact your local Intel representative before finalizing a

design.

WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and

extended exposure beyond the “Operating Conditions” may affect device reliability.

Table 16. Operating Conditions

Symbol

Parameter

Supply Voltage

Min

Max

Units

Notes

3.0

3.6

5.25

33.33

(1)

Input Protection Bias

Input Clock Frequency

CC5

MHz

P_CLK

Case Temperature Under Bias

T_C

i960^®VH processor (324 PBGA)

°C

NOTE:

1. The 80960VH processor is produced on Intel’s advanced CMOS process. Proper bulk decoupling must be

used to prevent device damage during power up and power down. Power supply behavior during these

transitions, without proper bulk decoupling, can cause the power supply to exceed the maximum V_CC

specification, causing device damage.

4.1

V_CC5Pin Requirements (V_DIFF)

In mixed voltage systems that drive 80960VH inputs in excess of 3.3 V, the V

pin must be

CC5

connected to the system’s 5 V supply. To limit current flow into the V

pin, there is a limit to the

CC5

voltage differential between the V

pin and the other V pins. The voltage differential between

CC5

the 80960VH V

pin and its 3.3 V V pins should never exceed 2.25 V. This limit applies to

CC5

power-up, power-down, and steady-state operation. Table 17 outlines this requirement. Meeting

this requirement ensures proper operation and guarantees that the current draw into the V pin

CC5

does not exceed the I

specification.

CC5

If the voltage difference requirements cannot be met due to system design limitations, then an

alternate solution may be employed. As shown in Figure 6., a minimum of 100 Ω series resistor

may be used to limit the current into the V

pin. This resistor ensures that current drawn by the

CC5

pin does not exceed the maximum rating for this pin.

CC5

Preliminary Datasheet

80960VH

Figure 6. V

Current-Limiting Resistor

CC5

+5 V (±0.25 V)

V_CC5Pin

100 Ω

(±5%, 0.5 W)

This resistor is not necessary in systems that can guarantee the V

specification.

DIFF

In 3.3 V-only systems and systems that drive 80960VH pins from 3.3 V logic, connect the V

CC5

pin directly to the 3.3 V V plane.

Table 17. V

Specification for Dual Power Supply Requirements (3.3 V, 5 V)

DIFF

Symbol

Parameter

Min

Max

Units

Notes

_CC5input should not exceed V_CCby more than 2.25 V

V_CC5-V_CC

Difference

V_DIFF

2.25

during power-up and power-down, or during steady-state

operation.

4.2

V_CCPLLPin Requirements

To reduce clock skew on the i960 Jx processor, the V

pin for the Phase Lock Loop (PLL)

CCPLL

circuit is isolated on the pinout. The lowpass filter, as shown in Figure 7., reduces noise-induced

clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be

(low ESR solid tantalum), the 0.01 µF capacitor must be of the type X7R and the node connecting

must be as short as possible.

CCPLL

Figure 7. V

Lowpass Filter

CCPLL

10Ω, 5%, 1/8W

V_CCPLL

V_CC

(Board Plane)

(On i960^®Jx processors)

4.7µF

0.01µF

F_CA078A

Preliminary Datasheet

80960VH

4.3

DC Specifications

Table 18. DC Characteristics

Symbol

Parameter

Input Low Voltage

Min

Max

Units

Notes

V_IL

-0.5

0.8

(1)

Input High Voltage for all signals

except P_CLK

V_CC

V_IH1

V_OL1

V_OH1

2.0

0.5

Output Low Voltage Processor signals

Output High Voltage Processor signals

0.45

I_OL= 6 mA (3)

I_OH= -2 mA (3)

2.4

V_CC- 0.5

I_OH= -200 µA (3)

V_OL2

V_OH2

Output Low Voltage PCI signals

Output High Voltage PCI signals

0.55

0.45

I_OL= 1.5 mA (1)

I_OH= 0.5 mA (1)

2.4

Output Low Voltage Memory Controller

Normal drive

V_OL3

V_OH3

_OL= 6 mA (4)

Output High Voltage Memory

Controller Normal drive

_OH= -2 mA (4)

_OL= 7 mA

Output Low Voltage Memory Controller

High Drive

V_OL4

0.45

Output High Voltage Memory

Controller High Drive

V_OH4

2.4

_OH= -2 mA

C_IN

Input Capacitance - PBGA

F_{P_CLK}= T_FMin (1, 2)

C_OUT

C_CLK

I/O or Output Capacitance - PBGA

P_CLK Capacitance - PBGA

F_{P_CLK}= T_FMin (1, 2)

C_IDSELIDSEL Ball Capacitance

(1)

L_PIN

Ball Inductance

NOTES:

1. As required by the PCI Local Bus Specification, revision 2.2.

2. Not tested.

3. Processor signals include AD31:0, ALE, ADS#, BE3:0#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#, W/

R#, DT/R#, DEN#, BLAST#, LRDYRCV#, LOCK#/ONCE#, HOLD, FAIL#, TDO, DACK#, WAIT#, SDA, SCL.

4. Memory Controller signals include MA11:0, DP3:0, RAS3:0#, CAS7:0#, MWE3:0#, DWE1:0#, DALE1:0, CE1:0#,

LEAF1:0#.

5. Memory Controller signals capable of high drive are MA11:0, CAS7:0#, RAS3:0#, DWE1:0#.

Preliminary Datasheet

80960VH

Table 19. I Characteristics

Symbol

Parameter

Typ

Max Units

Notes

Input Leakage Current for each signal except

PCI Bus Signals, LOCK#/ONCE#, WIDTH/

HLTD0, WIDTH/HLTD1/RETRY, BLAST#,

D/C#/RST_MODE#, DEN#, TMS, TRST#,

TDI, DACK#/PLLEN, LCDINIT#,

_IN= 0.8 V (V_IL)

I_LI1

± 5

µA

and 2.0 V (V_IH

)

LRDYRCV#/STEST, CLKMODE1:0#

Input Leakage Current for LOCK#/ONCE#,

WIDTH/HLTD0, WIDTH/HLTD1/RETRY,

BLAST#, D/C#/RST_MODE#, DEN#, TMS,

TRST#, TDI, DACK#/PLLEN, LCDINIT#,

LRDYRCV#/STEST, CLKMODE1:0#

I_LI2

-140

-250

_IN= 0.45 V (1)

Input Leakage Current for PCI Bus Signals

(except PCLK)

_IN= 0.8 V (V_IL)

I_LI3

I_LO

± 5

µA

and 2.0 V (V_IH

)

Output Leakage Current

0.4 ≤ V_OUT≤ V_CC

Power Supply Current

i960^®VH processor

I_CCActive

(Power Supply)

DX Mode

DX2 Mode

DX4 Mode

450

590

720

(1,2)

Thermal Current

i960^®VH processor

I_CCActive

(Thermal)

DX Mode

DX2 Mode

DX4 Mode

390

550

690

(1,3)

Reset Mode

i960^®VH processor

_CCActive

470

(4)

(Power Modes)

ONCE Mode

i960^®VH processor

NOTES:

1. Measured with device operating and outputs loaded to the test condition in Figure 8.

2. I_CCActive (Power Supply) value is provided for selecting your system’s power supply. It is measured using one of the worst

case instruction mixes with V_CC= 3.6 V and ambient temperature = 55 ° C. This parameter is characterized but not tested.

3. I_CCActive (Thermal) value is provided for your system’s thermal management. Typical I_CCis measured with V_CC= 3.3 V

and ambient temperature = 55 ° C. This parameter is characterized but not tested.

I_CCActive (Power modes) refers to the I_CCvalues that are tested when the device is in Reset mode or ONCE mode with

V_CC= 3.6 V and ambient temperature = 55 ° C.

Preliminary Datasheet

80960VH

4.4

AC Specifications

Table 20. Input Clock Timings

Symbol

Parameter

Min

Max

Units

Notes

T_F

T_C

P_CLK Frequency

P_CLK Period

33.33

62.5

MHz

(1)

T_CS

P_CLK Period Stability

P_CLK High Time

P_CLK Low Time

P_CLK Rise Time

P_CLK Fall Time

±250

Adjacent Clocks (2,3)

Measured at 1.5 V (2,3)

0.4 V to 2.4 V (2,3)

T_CH

T_CL

T_CR

V/ns

T_CF

2.4 V to 0.4 V (2,3)

NOTES:

1. See Figure 9, (pg. 46).

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum

should not have any power peaking between 500 KHz and 1/3 of the P_CLK frequency.

3. Not tested.

Table 21. Synchronous Output Timings

Symbol

Parameter

Min

Max

Units

Notes

Output Valid Delay - All Local Bus Signals Except

ALE Inactive and DT/R#

T_OV1

15.5

(1,2,5)

0.5 T_C

+15

T_OV2

Output Valid Delay, DT/R#

0.5 T_C+3

(2,5)

T_OV3

T_OV4

Output Valid Delay - PCI Signals Except P_REQ#

Output Valid Delay P_REQ#

Output Valid Delay - DP3:0

(2,5)

T_OV5

(2,5)

T_OF

Output Float Delay

(3,4,5)

NOTES:

1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 42).

2. See Figure 10, (pg. 46).

3. A float condition occurs when the output current becomes less than I_LO. Float delay is not tested, but is designed to be no

longer than the valid delay.

4. See Figure 11, (pg. 47).

5. Outputs precharged to V_CC5maximum.

Preliminary Datasheet

80960VH

Table 22. Synchronous Input Timings

Sym

Parameter

Min Max

Units

Notes

T_IS1

Input Setup to P_CLK — NMI#, XINT7:0#, DP3:0

(1,2)

Input Setup to P_CLK — for all accesses except Expansion ROM

Accesses — AD31:0 only

T_IS1A

T_IS1B

(1,2)

Input Setup to P_CLK during Expansion ROM Accesses —

AD31:0 only

T_IH1Input Hold from P_CLK — AD31:0, NMI#, XINT7:0#, DP3:0

T_IS2Input Setup to P_CLK — RDYRCV# and HOLD

T_IH2Input Hold from P_CLK — RDYRCV# and HOLD

T_IS3Input Setup to P_CLK — LOCK#/ONCE#, STEST

T_IH3Input Hold from P_CLK — LOCK#/ONCE#, STEST

T_IS4Input Setup to P_CLK — DREQ#

T_IH4Input Hold from P_CLK — DREQ#

T_IS5Input Setup to P_CLK — PCI Signals Except P_GNT#

T_IH5Input Hold from P_CLK — PCI Signals

(1,2,4)

(2)

(1,2,4)

(2)

(2,4)

(2,3)

(2,3,4)

(2)

T_IS6

Input Setup to P_CLK — P_RST# - DX4 Mode

Input Setup to P_CLK — P_RST# - DX2 and DX Mode

T_IH6Input Hold to P_CLK — P_RST#

T_IS7

T_IS8

Input Setup to P_CLK — P_GNT#

Input Setup to P_RST# —

WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#

(1,2,4)

Input Hold from P_RST# —

WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#

T_IH8

NOTES:

1. Setup and hold times must be met for proper processor operation. NMI#, and XINT7:0# may be synchronous or asynchro-

nous. Meeting setup and hold time guarantees recognition at a particular clock edge.

For asynchronous operation, NMI#, and XINT7:0# must be asserted for a minimum of two P_CLK periods to guarantee

recognition.

2. See Figure 12, (pg. 47).

3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock

edge.

4. Guaranteed by design. May not be 100% tested.

Preliminary Datasheet

80960VH

4.4.1

Relative Output Timings

Table 23. Relative Output Timings

Symbol

Parameter

Min

Max

Units

Notes

T_LXL

T_LXA

ALE Width

0.5T_C-3

0.5T_C-1

0.5T_C-3

(1,2,4)

Address Hold from ALE Inactive

DT/R# Valid to DEN# Active

Equal Loading (1,2,4)

Equal Loading (1,3,4)

T_DXD

NOTES:

1. Guaranteed by design. May not be 100% tested.

2. See Figure 13, (pg. 47).

3. See Figure 14, (pg. 48)

4. Outputs precharged to V_CC5maximum.

4.4.2

Memory Controller Relative Output Timings

Table 24. Fast Page Mode Non-interleaved DRAM Output Timings

Symbol

Description

Min

Max

Units

Notes

RAS3:0# Rising and Falling edge Output Valid

Delay

T_OV6

T_OV7

T_OV8

T_OV9

T_OV10

CAS7:0# Rising Edge Output Valid Delay

CAS7:0# Falling Edge Output Valid Delay

MA11:0 Output Valid Delay-Row Address

MA11:0 Output Valid Delay-Column Address

0.5Tc+1

0.5Tc+8

0.5Tc+10

1,2

DWE1:0# Rising and Falling edge Output Valid

Delay

T_OV11

NOTES:

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK

period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.

2. Output switching between V_CC3maximum and V_SS

Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 1 of 2)

Symbol

Description

Min

Max

Units

Notes

RAS3:0# Rising and Falling edge Output Valid

Delay

T_OV12

T_OV13

T_OV14

T_OV15

T_OV16

CAS7:0# Rising Edge Output Valid Delay

CAS7:0# Falling Edge Output Valid Delay

MA11:0 Output Valid Delay-Row Address

MA11:0 Output Valid Delay-Column Address

0.5Tc+1

0.5Tc+8

0.5Tc+10

1,2

DWE1:0# Rising and Falling Edge Output Valid

Delay

T_OV17

NOTES:

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK

period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.

2. Output switching between V_CC3maximum and V_SS

Preliminary Datasheet

80960VH

Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 2 of 2)

Symbol

Description

Min

Max

Units

Notes

T_OV18

T_OV19

T_OV20

DALE1:0 Initial Falling Edge Output Valid Delay

DALE1:0 Burst Falling Edge Output Valid Delay

DALE1:0 Rising Edge Output Valid Delay

0.5Tc+1

0.5Tc+10

1,2

LEAF1:0# Rising and Falling Edge Output Valid

Delay

T_OV21

NOTES:

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK

period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.

2. Output switching between V_CC3maximum and V_SS

Table 26. EDO DRAM Output Timings

Note

Symbol

Description

Min

Max

Units

T_OV22

T_OV23

RAS3:0# Rising and Falling Edge Output Valid Delay

CAS7:0# Rising Edge Output Valid Delay -

Read Cycles

0.5Tc+1

0.5Tc+8

1,2

CAS7:0# Falling Edge Output Valid Delay -

Read Cycles

T_OV24

T_OV25

T_OV26

CAS7:0# Rising Edge Output Valid Delay -

Write Cycles

CAS7:0# Falling Edge Output Valid Delay -

Write Cycles

0.5Tc+1

0.5Tc+8

1,2

T_OV27

T_OV28

T_OV29

T_OV30

NOTES:

MA11:0 Output Valid Delay - Row Address

0.5Tc+1 0.5Tc+10

1,2

MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc+1 0.5Tc+10

MA11:0 Output Valid Delay - Column Address Write Cycles

DWE1:0# Rising and Falling Edge Output Valid Delay

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK

period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.

2. Output switching between V_CC3maximum and V_SS

Table 27. SRAM/ROM Output Timings (Sheet 1 of 2)

Symbol

Description

Min

Max

Units

Notes

CE1:0# Rising and Falling Edge Output Valid

Delay

T_OV40

T_OV41

T_OV42

MWE3:0# Rising Edge Output Valid Delay

MWE3:0# Falling Edge Output Valid Delay

0.5Tc+1

0.5Tc +9

1,2

Preliminary Datasheet

80960VH

Table 27. SRAM/ROM Output Timings (Sheet 2 of 2)

Symbol

Description

Min

Max

Units

Notes

T_OV43

T_OV44

MA11:0 Output Valid Delay - Initial Address

MA11:0 Output Valid Delay - Burst Address

0.5Tc+1

0.5Tc +10

NOTES:

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK

period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.

2. Output switching between V_CC3maximum and V_SS

4.4.3

Boundary Scan Test Signal Timings

Table 28. Boundary Scan Test Signal Timings

Symbol

Parameter

TCK Frequency

Min

Max

Units

Notes

T_BSF

T_BSCH

T_BSCL

T_BSCR

T_BSCF

0.5T_F

MHz

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

T_BSIS1

Input Setup to TCK — TDI,

TMS

T_BSIH1

Input Hold from TCK — TDI,

TMS

(1)

T_BSOV1

T_BSOF1

T_BSOV2

TDO Valid Delay

TDO Float Delay

Relative to falling edge of TCK (1,2)

All Outputs (Non-Test) Valid

Delay

T_BSOF2

T_BSIS2

All Outputs (Non-Test) Float

Delay

Relative to falling edge of TCK (1,2)

Input Setup to TCK — All

Inputs (Non-Test)

(1)

T_BSIH2

Input Hold from TCK — All

Inputs (Non-Test)

NOTES:

1. Guaranteed by design. Not tested.

2. Outputs precharged to V_CC5maximum.

Preliminary Datasheet

80960VH

4.4.4

I C Interface Signal Timings

Table 29. I C Interface Signal Timings

Std. Mode

Fast Mode

Symbol

Parameter

Units Notes

Min

Max

Min

Max

400

F_SCL

T_BUF

SCL Clock Frequency

100

KHz

Bus Free Time Between STOP and START

Condition

4.7

1.3

µs

(1)

T_HDSTAHold Time (repeated) START Condition

4.7

0.6

1.3

0.6

µs

(1,3)

(1,2)

T_LOW

T_HIGH

SCL Clock Low Time

SCL Clock High Time

Setup Time for a Repeated START

Condition

T_SUSTA

4.7

0.6

µs

(1)

T_HDDATData Hold Time

T_SUDATData Setup Time

0.9

µs

(1)

250

100

T_R

T_F

SCL and SDA Rise Time

SCL and SDA Fall Time

1000 20+0.1C_b

300

(1,4)

(1)

300

20+0.1C_b

0.6

T_SUSTOSetup Time for STOP Condition

NOTES:

1. See Figure 15, (pg. 48).

2. Not tested.

3. After this period, the first clock pulse is generated.

4. C_b= the total capacitance of one bus line, in pF.

4.5

AC Test Conditions

The AC Specifications in Section 4.4, AC Specifications (pg. 40) are tested with the 50 pF load

indicated in .

Figure 8. AC Test Load

Output Ball

C_L= 50 pF for all signals

C_L

Preliminary Datasheet

80960VH

4.6

AC Timing Waveforms

Figure 9. P_CLK, TCLK Waveform

2.0V

1.5V

0.8V

Figure 10. T Output Delay Waveform

1.5V

P_CLK

T_OVXMin

T_OVXMax

1.5V

Valid

Preliminary Datasheet

80960VH

Figure 11. T Output Float Waveform

1.5V

P_CLK

Figure 12. T_ISand T_IHInput Setup and Hold Waveform

1.5V

IHX

1.5V

P_CLK

ISX

Valid

1.5V

Figure 13. T_LXLand T_LXARelative Timings Waveform

T_A

T_W/T_D

1.5V

P_CLK

ALE

T_LXL

1.5V

Valid

1.5V

T_LXA

1.5V

AD31:0

Valid

Preliminary Datasheet

80960VH

Figure 14. DT/R# and DEN# Timings Waveform

T_A

T_W/T_D

P_CLK

1.5V

T_OVX

Valid

DT/R#

DEN#

T_DXD

T_OVX

Figure 15. I C Interface Signal Timings

SDA

LOW

BUF

HDSTA

SCL

HDSTA

SUSTO

HIGH

HDDAT

SUDAT

SUSTA

Stop

Start

Stop

Repeated

Start

Preliminary Datasheet

80960VH

4.7

Memory Controller Output Timing Waveforms

Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960

Local Bus

T_A

T_w

T_d

T_w

T_d

T_w

T_d

T_w

T_d

T_r

P_CLK

AD31:0

MA11:0

ALE

DATA

ADDR

COL

ROW

COL

ADS#

W/R#

BLAST#

DT/R#

DEN#

DWE0#

RAS0#

CAS3:0#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960

Local Bus

T_A

T_w

T_d

T_w

T_d

T_w

T_d

T_w

T_d

T_r

P_CLK

DATAO

DATA

OUT

DATA

OUT

DATA

OUT

ADDR

AD31:0

MA11:0

ALE

ROW

COL

ADS#

BE3:0#

W/R#

BLAST#

DT/R#

MWE0#

DWE0#

RAS0#

CAS3:0#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States

T_A

T_W

T_D

P_CLK

ADDR

AD[31:0]

RAS[n]#

RAS[n+1#]

COL

ROW

MA[11:0]

DALE[0]#

CAS[3:0]#

LEAF[0]#

DALE[1]#

CAS[7:4]#

LEAF[1]#

DWE[1:0]#

Preliminary Datasheet

80960VH

Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States

T_W

T_D

T_R

T_A

P_CLK

DATA

OUT

DATA

OUT

DATA

OUT

DATA

OUT

AD[31:0]

ADDR

RAS[n]#

RAS[n+1]#

COL

ROW

MA[11:0]

DALE[0]#

CAS[3:0]#

LEAF[0]#

DALE[1]#

CAS[7:4]#

LEAF[1]#

DWE[1:0]#

Preliminary Datasheet

80960VH

Figure 20. EDO DRAM, Read Cycle

T_A

T_W

T_D

T_R

P_CLK

RAS#

COL

MA[11:0]

CAS#

COL

ROW

COL

AD[31:0]

ADDR

Figure 21. EDO DRAM, Write Cycle

T_A

T_W

T_D

T_R

P_CLK

RAS#

COL

ROW

COL COL COL

MA[11:0]

CAS#

OUT

AD[31:0]

ADDR

Preliminary Datasheet

80960VH

Figure 22. 32-Bit Bus, SRAM Read Accesses with 0 Wait States

T_A

T_D

T_R

P_CLK

CE[1]#

ADDR ADDR ADDR ADDR

MA[11:0]

MWE[3:0]#

AD[31:0]

ADDR

Figure 23. 32-Bit Bus, SRAM Write Accesses with 0 Wait States

T_A

T_D

T_R

P_CLK

CE[1]#

ADDR ADDR ADDR ADDR

MA[11:0]

MWE[3:0]#

AD[31:0]

ADDR

OUT

OUT OUT

Preliminary Datasheet

80960VH

5.0

Bus Functional Waveforms

Figure 24. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local

Bus

T_A

T_D

T_R

T_I

T_A

T_D

T_R

T_I

P_CLK

AD31:0

ADDR

Invalid

DATA Out

ADDR

ALE

ADS#

BE3:0#

WIDTH1:0

D/C#

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 25. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus

T_A

T_D

T_R

T_A

T_D

T_R

P_CLK

AD31:0

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ALE

ADS#

BE3:0#

1 0

WIDTH1:0

D/C#

1 0

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 26. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus

T_A

T_W

T_D

T_W

T_D

T_W

T_D

T_W

T_D

T_R

P_CLK

AD31:0

ALE

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ADS#

BE3:0#

WIDTH1:0

D/C#

1 0

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 27. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus

T_A

T_D

T_R

T_A

T_D

T_R

P_CLK

AD31:0

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ALE

ADS#

BE1/A1#

BE0/A0#

01 or

00 or 10

WIDTH1:0

D/C#

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 28. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on

Read, 16-Bit 80960 Local Bus

T_W

T_D

T_R

T_A

T_W

T_D

T_R

T_A

P_CLK

AD31:0

ALE

DATA

Out

DATA

Out

ADDR

ADS#

BE1/A1#

BE3#

BE0#

WIDTH1:0

D/C#

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 29. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One

Byte From Quad Word Boundary, 32-Bit 80960 Local Bus

T_A

T_D

T_R

T_A

T_D

T_R

T_A

T_D

T_R

T_A

T_D

T_R

P_CLK

AD31:0

ALE

ADS#

BE3:0#

0 0 0 0

1 1 1 0

0 0 1 1

1 1 0 1

1 0

WIDTH1:0

D/C#

Valid

W/R#

BLAST#

DT/R#

DEN#

LRDYRCV#

RDYRCV#

Preliminary Datasheet

80960VH

Figure 30. HOLD/HOLDA Waveform For Bus Arbitration

T_Ior T_R

T_H

T_Ior T_A

P_CLK

Outputs:

AD31:0,

ALE, ADS#, BE3:0#

D/C#/RSTMODE#

LRDYRCV#, FAIL#

Valid

WIDTH/HLTD1,

WIDTH/HLTD1/RETRY,

W/R#, DT/R#, DEN#,

BLAST#, LOCK#/ONCE#

HOLD

HOLDA

(Note)

NOTE: HOLD is sampled on the rising edge of P_CLK. HOLDA is granted after the latency counter in the local

bus arbiter expires. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes

HOLD if the last state was T_ior the last T_rof a bus transaction. Similarly, the processor deasserts HOLDA on

the same edge in which it recognizes the deassertion of HOLD.

Preliminary Datasheet

t e e t a a s h y r D a n i m i e r l P

6 2

m r

a v e W t f o

R d l e s e r e C C o o 6 0 8 0 9 r e u g 3 i 1 F .

H V

8 0 9 6 0

80960VH

Figure 32. 80960 Local Bus Warm Reset Waveform

Preliminary Datasheet

80960VH

6.0

Device Identification On Reset

During the manufacturing process, values characterizing the i960 VH processor type and stepping

are programmed into the memory-mapped registers. The 80960VH contains two read-only device

ID MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the i960

Core Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed

in g0.

The device identification values are compliant with the IEEE 1149.1 specification and Intel

standards. Table 30 describes the fields of the two Device IDs.

Table 30. Processor Device ID Register - PDIDR

LBA

PCI

ro ro

ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na

Legend:NA = Not AccessibleRO = Read Only

RV = ReservedPR = PreservedRW = Read/Write

LBA: 1710H

RS = Read/SetRC = Read Clear

LBA = 80960 Local Bus Address PCI = PCI Configuration Address Offset

PCI:

Bit

Default

Description

31:28

Version - Indicates stepping changes.

V_CC- Indicates device voltage type.

0 = 5.0 V

1 = 3.3 V

26:21

20:17

16:12

Product Type - Indicates the generation or “family member”.

Generation Type - Indicates the generation of the device.

Model Type - Indicates member within a series and specific model information.

Manufacturer ID - Indicates manufacturer ID assigned by IEEE.

0000 0001 001 = Intel Corporation

11:01

Constant

NOTE:

Values programmed into this register vary with stepping. Refer to the i960^®VH processor Specification Update

(273174-001) for the correct value.

Preliminary Datasheet

80960VH [INTEL]

相关型号：

8096BH

8097

8097

8097BH

8097JF

8098

8098

8099

809A-4.000MHZ-FF0

809A-54.000MHZ-FF0

809A-FREQ-FF0

809A060-1