80960CA-33 [INTEL]
80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR; 80960CA - 33 ， -25 ， -16的32位高性能嵌入式处理器
| 型号： | 80960CA-33 |
| 厂家： | 
INTEL |
| 描述： | 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR |
| 文件： | 总68页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
• Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining
■ 32-bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
■ Four On-Chip DMA Channels
— 59 Mbytes/s Fly-by Transfers
— 32 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Sixteen 32-bit Global Registers
— Sixteen 32-bit Local Registers
— Manipulates 64-bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
— Data Packing/Unpacking
— Programmable Priority Method
■ 32-Bit Demultiplexed Burst Bus
— 128-bit Internal Data Paths to and
from Registers
■ Fast Procedure Call/Return Model
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
— Full Procedure Call in 4 Clocks
■ On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
■ Selectable Big or Little Endian Byte
■ On-Chip Instruction Cache
— 1 Kbyte Two-Way Set Associative
— 128-bit Path to Instruction Sequencer
— Cache-Lock Modes
Ordering
■ High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 750 ns Typical
— Cache-Off Mode
■ High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993
November 1993
Order Number: 270727-006
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
PAGE
1.0 PURPOSE ..................................................................................................................................................1
2.0 80960CA OVERVIEW.................................................................................................................................1
2.1 The C-Series Core ..............................................................................................................................2
2.2 Pipelined, Burst Bus ...........................................................................................................................2
2.3 Flexible DMA Controller ......................................................................................................................2
2.4 Priority Interrupt Controller ..................................................................................................................2
2.5 Instruction Set Summary ....................................................................................................................3
3.0 PACKAGE INFORMATION.........................................................................................................................4
3.1 Package Introduction ..........................................................................................................................4
3.2 Pin Descriptions ..................................................................................................................................4
3.3 80960CA Mechanical Data ............................................................................................................... 11
3.3.1 80960CA PGA Pinout ............................................................................................................ 11
3.3.2 80960CA PQFP Pinout ..........................................................................................................15
3.4 Package Thermal Specifications ......................................................................................................18
3.5 Stepping Register Information ..........................................................................................................20
3.6 Suggested Sources for 80960CA Accessories..................................................................................20
4.0 ELECTRICAL SPECIFICATIONS.............................................................................................................21
4.1 Absolute Maximum Ratings ..............................................................................................................21
4.2 Operating Conditions ........................................................................................................................21
4.3 Recommended Connections ............................................................................................................21
4.4 DC Specifications .............................................................................................................................22
4.5 AC Specifications ..............................................................................................................................23
4.5.1 AC Test Conditions ................................................................................................................29
4.5.2 AC Timing Waveforms ...........................................................................................................29
4.5.3 Derating Curves .....................................................................................................................33
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE .................................................................................35
6.0 BUS WAVEFORMS .................................................................................................................................36
7.0 REVISION HISTORY ................................................................................................................................64
ii
CONTENTS
PAGE
LIST OF FIGURES
Figure 1
80960CA Block Diagram ..............................................................................................................1
80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13
80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14
80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Register g0 .................................................................................................................................20
AC Test Load .............................................................................................................................. 29
Input and Output Clocks Waveform ............................................................................................ 29
CLKIN Waveform ........................................................................................................................ 29
Output Delay and Float Waveform ............................................................................................. 30
Input Setup and Hold Waveform ................................................................................................ 30
NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Hold Acknowledge Timings ........................................................................................................ 31
Bus Backoff (BOFF) Timings ...................................................................................................... 32
Relative Timings Waveforms ...................................................................................................... 33
Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC .................. 34
ICC vs. Frequency and Temperature ........................................................................................... 34
Cold Reset Waveform ................................................................................................................ 36
Warm Reset Waveform .............................................................................................................. 37
Entering the ONCE State ........................................................................................................... 38
Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
iii
CONTENTS
PAGE
LIST OF FIGURES (continued)
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Using External READY ............................................................................................................... 55
Terminating a Burst with BTERM ............................................................................................... 56
BOFF Functional Timing ............................................................................................................ 57
HOLD Functional Timing ............................................................................................................ 58
DREQ and DACK Functional Timing .......................................................................................... 59
EOP Functional Timing .............................................................................................................. 59
Terminal Count Functional Timing .............................................................................................. 60
FAIL Functional Timing ............................................................................................................... 60
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62
Idle Bus Operation ...................................................................................................................... 63
LIST OF TABLES
80960CA Instruction Set ..............................................................................................................3
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Pin Description Nomenclature ......................................................................................................4
80960CA Pin Description — External Bus Signals ......................................................................5
80960CA Pin Description — Processor Control Signals ..............................................................8
80960CA Pin Description — DMA and Interrupt Unit Control Signals ....................................... 10
80960CA PGA Pinout — In Signal Order ................................................................................... 11
80960CA PGA Pinout — In Pin Order ........................................................................................ 12
80960CA PQFP Pinout — In Signal Order ................................................................................. 15
80960CA PQFP Pinout — In Pin Order ..................................................................................... 16
Maximum TA at Various Airflows in oC (PGA Package Only) ..................................................... 18
80960CA PGA Package Thermal Characteristics ...................................................................... 19
80960CA PQFP Package Thermal Characteristics .................................................................... 19
Die Stepping Cross Reference ................................................................................................... 20
Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21
DC Characteristics ..................................................................................................................... 22
80960CA AC Characteristics (33 MHz) ...................................................................................... 23
80960CA AC Characteristics (25 MHz) ...................................................................................... 25
80960CA AC Characteristics (16 MHz) ...................................................................................... 27
Reset Conditions ........................................................................................................................ 35
Hold Acknowledge and Backoff Conditions ................................................................................ 35
iv
80960CA-33, -25, -16
A
32-bit demultiplexed and pipelined burst bus
1.0 PURPOSE
provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory sub-system. In
addition, the 80960CA’s on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system’s
slower, cost sensitive, main memory subsystem.
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic—other than parametric performance—consult
the 80960CA Product Overview (Order No. 270669)
or the i960 CA Microprocessor User’s Manual
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel’s FaxBACK data-on-
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600).
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
2.0 80960CA OVERVIEW
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers—in
addition to source or destination synchronized trans-
fers—are provided.
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (”latency”) time of
750 ns.
DMA
DMA Controller Port
Instruction Prefetch Queue
Four-Channel
Instruction Cache
(1 KByte, Two-way
Set Associative)
Control
Memory Region
Configuration
128-BIT CACHE BUS
Bus
Interrupt
Port
Programmable
Interrupt Controller
Controller
Parallel
Address
Data
Instruction
Scheduler
Bus Request
Queues
Multiply/Divide
Unit
1 KByte
Data RAM
Register-side
Machine Bus
Memory-side
Machine Bus
Execution
Unit
5 to 15 Sets
Register Cache
Six-port
Register File
Address
Generation Unit
64-Bit
32-Bit
SRC1 Bus
Base Bus
64-Bit
SRC2 Bus
128-Bit
Load Bus
64-Bit
DST Bus
128-Bit
Store Bus
F_CX001A
Figure 1. 80960CA Block Diagram
1
80960CA-33, -25, -16
•
•
Demultiplexed, Burst Bus to exploit most efficient
DRAM access modes
2.1 The C-Series Core
The C-Series core is a very high performance
microarchitectural implementation of the 80960 Core
Architecture. The C-Series core can sustain execu-
tion of two instructions per clock (66 MIPs at
33 MHz). To achieve this level of performance, Intel
has incorporated state-of-the-art silicon technology
and innovative microarchitectural constructs into the
implementation of the C-Series core. Factors that
contribute to the core’s performance include:
Address Pipelining to reduce memory cost while
maintaining performance
•
•
32-, 16- and 8-bit modes for I/O interfacing ease
Full internal wait state generation to reduce
system cost
•
Little and Big Endian support to ease application
development
•
•
Unaligned access support for code portability
•
Parallel instruction decoding allows issuance of
up to three instructions per clock
Three-deep request queue to decouple the bus
from the core
•
•
Single-clock execution of most instructions
Parallel instruction decode allows sustained,
simultaneous execution of two single-clock
instructions every clock cycle
2.3 Flexible DMA Controller
A four-channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disas-
sembly and a high performance fly-by mode capable
of transfer speeds of up to 59 Mbytes per second at
33 MHz. The DMA controller features a performance
and flexibility which is only possible by integrating the
DMA controller and the 80960CA core.
•
•
•
•
•
•
Efficient instruction pipeline minimizes pipeline
break losses
Register and resource scoreboarding allow simul-
taneous multi-clock instruction execution
Branch look-ahead and prediction allows many
branches to execute with no pipeline break
Local Register Cache integrated on-chip caches
Call/Return context
Two-way set associative, 1 Kbyte integrated
instruction cache
2.4 Priority Interrupt Controller
1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle
A
programmable-priority
interrupt
controller
manages up to 248 external sources through the 8-
bit external interrupt port. The Interrupt Unit also
handles the four internal sources from the DMA
controller and a single non-maskable interrupt input.
The 8-bit interrupt port can also be configured to
provide individual interrupt sources that are level or
edge triggered.
2.2 Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CA to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 132 Mbytes per second (at 33 MHz). Inter-
nally programmable wait states and 16 separately
configurable memory regions allow the processor to
interface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus Controller’s main features
include:
Interrupts in the 80960CA are prioritized and
signaled within 270 ns of the request. If the interrupt
is of higher priority than the processor priority, the
context switch to the interrupt routine typically is
complete in another 480 ns. The interrupt unit
provides the mechanism for the low latency and high
throughput interrupt service which is essential for
embedded applications.
2
80960CA-33, -25, -16
2.5 Instruction Set Summary
Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960 CA Microprocessor User’s
Manual for a complete description of the instruction set.
Table 1. 80960CA Instruction Set
Data
Movement
Bit and Bit Field
and Byte
Arithmetic
Logical
Load
Store
Move
Add
And
Set Bit
Subtract
Not And
And Not
Or
Clear Bit
Multiply
Not Bit
Load Address
Divide
Alter Bit
Remainder
Modulo
Exclusive Or
Not Or
Scan For Bit
Span Over Bit
Extract
Shift
Or Not
*Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
Nor
Modify
Exclusive Nor
Not
Scan Byte for Equal
Nand
Comparison
Branch
Call/Return
Fault
Compare
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Conditional Fault
Conditional Compare
Call Extended
Call System
Return
Synchronize Faults
Compare and
Increment
Compare and
Decrement
Branch and Link
Test Condition Code
Check Bit
Processor
Management
Debug
Atomic
Modify Trace Controls
Mark
Flush Local Registers
Atomic Add
Modify Arithmetic
Controls
Atomic Modify
Force Mark
Modify Process
Controls
*System Control
*DMA Control
NOTES:
Instructions marked by (*) are 80960CA extensions to the 80960 instruction set.
3
80960CA-33, -25, -16
Table 2. Pin Description Nomenclature
Symbol Description
3.0 PACKAGE INFORMATION
3.1 Package Introduction
I
O
Input only pin
Output only pin
This section describes the pins, pinouts and thermal
characteristics for the 80960CA in the 168-pin
Ceramic Pin Grid Array (PGA) package and the 196-
pin Plastic Quad Flat Package (PQFP). For complete
package specifications and information, see the
Packaging Handbook (Order No. 240800).
I/O
–
Pin can be either an input or output
Pins “must be” connected as described
S(...)
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
S(E)
S(L)
Edge sensitive input
Level sensitive input
3.2 Pin Descriptions
The 80960CA pins are described in this section.
Table 2 presents the legend for interpreting the pin
descriptions in the following tables. Pins associated
with the 32-bit demultiplexed processor bus are
described in Table 3. Pins associated with basic
processor configuration and control are described in
Table 4. Pins associated with the 80960CA DMA
Controller and Interrupt Unit are described in Table
5.
A(...)
H(...)
Asynchronous. Inputs may be
asynchronous to PCLK2:1.
A(E)
Edge sensitive input
A(L)
Level sensitive input
While the processor’s bus is in the
Hold Acknowledge or Bus Backoff state,
the pin:
H(1)
H(0)
H(Z)
H(Q)
is driven to VCC
is driven to VSS
floats
All pins float while the processor is in the ONCE
mode.
continues to be a valid input
R(...)
While the processor’s RESET pin is low,
the pin:
R(1)
R(0)
R(Z)
R(Q)
is driven to VCC
is driven to VSS
floats
continues to be a valid output
4
80960CA-33, -25, -16
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 1 of 3)
Name
A31:2
Type
Description
O
S
H(Z)
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most
significant address bit; A2 is the least significant. During a bus access, A31:2 identify
all external addresses to word (4-byte) boundaries. The byte enable signals indicate
the selected byte in each word. During burst accesses, A3:2 increment to indicate
successive data cycles.
R(Z)
D31:0
BE3:0
I/O
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configu-
ration. The least significant bit of the data is carried on D0 and the most significant on
D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used.
For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is
used.
S(L)
H(Z)
R(Z)
O
S
H(Z)
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3 applies to
D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
R(1)
32-bit bus:
BE3
BE2
BE1
BE0
–Byte Enable 3
–Byte Enable 2
–Byte Enable 1
–Byte Enable 0
–enable D31:24
–enable D23:16
–enable D15:8
–enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the
processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3
BE2
BE1
BE0
–Byte High Enable (BHE)
–Not used (driven high or low)
–Address Bit 1 (A1)
–enable D15:8
–Byte Low Enable (BLE)
–enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the
processor uses the BE1 and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3
BE2
BE1
BE0
–Not used (driven high or low)
–Not used (driven high or low)
–Address Bit 1 (A1)
–Address Bit 0 (A0)
W/R
ADS
O
S
H(Z)
R(0)
WRITE/READ is asserted for read requests and deasserted for write requests. The
W/R signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be
valid in the last cycle of a read access.
O
S
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
H(Z)
R(1)
5
80960CA-33, -25, -16
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 2 of 3)
Name
Type
Description
READY
I
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. If READY is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY pin is deasserted, wait states
S(L)
H(Z)
R(Z)
continue to be inserted until READY becomes asserted. This is true for the NRAD
,
NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended.
BTERM
I
BURST TERMINATE is an input which breaks up a burst access and causes another
address cycle to occur. The BTERM signal works in conjunction with the internally
programmed wait-state generator. If READY and BTERM are enabled in a region, the
BTERM pin is sampled after the programmed number of wait states has expired.
When BTERM is asserted, a new ADS signal is generated and the access is
completed. The READY input is ignored when BTERM is asserted. BTERM must be
externally synchronized to satisfy BTERM setup and hold times.
S(L)
H(Z)
R(Z)
WAIT
BLAST
DT/R
O
S
H(Z)
WAIT indicates internal wait state generator status. WAIT is asserted when wait
states are being caused by the internal wait state generator and not by the READY or
BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be
thought of as a READY output that the processor provides when it is inserting wait
states.
R(1)
O
S
H(Z)
R(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the wait state counter reaches
zero. BLAST remains asserted until the clock following the last cycle of the last data
transfer of a bus access. If the READY or BTERM input is used to extend wait states,
the BLAST signal remains asserted until READY or BTERM terminates the access.
O
S
H(Z)
R(0)
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in
conjunction with DEN to provide control for data transceivers attached to the external
bus. When DT/R is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R changes only while
DEN is high.
DEN
O
S
H(Z)
R(1)
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle.
DEN is used in conjunction with DT/R to provide control for data transceivers attached
to the external bus. DEN remains asserted for sequential reads from pipelined
memory regions. DEN is deasserted when DT/R changes.
LOCK
O
S
H(Z)
BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK
may be used to prevent external agents from accessing memory which is currently
involved in an atomic operation. LOCK is asserted in the first clock of an atomic
operation and deasserted in the clock cycle following the last bus access for the
atomic operation. To allow the most flexibility for memory system enforcement of
locked accesses, the processor acknowledges a bus hold request when LOCK is
asserted. The processor performs DMA transfers while LOCK is active.
R(1)
HOLD
I
HOLD REQUEST signals that an external agent requests access to the external bus.
The processor asserts HOLDA after completing the current bus request. HOLD,
HOLDA and BREQ are used together to arbitrate access to the processor’s external
bus by external bus agents.
S(L)
H(Z)
R(Z)
6
80960CA-33, -25, -16
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 3 of 3)
Name
BOFF
Type
Description
I
BUS BACKOFF, when asserted, suspends the current access and causes the bus
pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock
cycle and the access is resumed.
S(L)
H(Z)
R(Z)
HOLDA
O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin-
quished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ
are used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET is asserted, the state of the HOLDA pin is independent of the
RESET pin.
BREQ
D/C
O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending. BREQ
can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to
determine when to return mastership of the external bus to the processor.
O
S
DATA OR CODE is asserted for a data request and deasserted for instruction
requests. D/C has the same timing as W/R.
H(Z)
R(Z)
DMA
SUP
O
S
H(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA is asserted for any DMA request. DMA is deasserted for all other requests.
R(Z)
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode. SUP is asserted when the request has supervisor privileges and is
deasserted otherwise. SUP can be used to isolate supervisor code and data
structures from non-supervisor requests.
7
80960CA-33, -25, -16
Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 1 of 2)
Name
Type
Description
RESET
I
RESET causes the chip to reset. When RESET is asserted, all external signals
return to the reset state. When RESET is deasserted, initialization begins. When
the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles
before being deasserted to guarantee correct processor initialization. When the 1-x
clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles
before being deasserted to guarantee correct processor initialization. The
CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin.
A(L)
H(Z)
R(Z)
The processor’s Hold Acknowledge bus state functions while the chip is reset. If the
processor’s bus is in the Hold Acknowledge state when RESET is asserted, the
processor will internally reset, but maintains the Hold Acknowledge state on
external pins until the Hold request is removed. If a Hold request is made while the
processor is in the reset state, the processor bus will grant HOLDA and enter the
Hold Acknowledge state.
FAIL
O
S
H(Q)
R(0)
FAIL indicates failure of the processor’s self-test performed at initialization. When
RESET is deasserted and the processor begins initialization, the FAIL pin is
asserted. An internal self-test is performed as part of the initialization process. If
this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The
FAIL pin is reasserted while the processor performs an external bus self-confidence
test. If this self-test passes, the processor deasserts the FAIL pin and branches to
the user’s initialization routine; otherwise the FAIL pin remains asserted. Internal
self-test and the use of the FAIL pin can be disabled with the STEST pin.
STEST
ONCE
I
SELF TEST causes the processor’s internal self-test feature to be enabled or
disabled at initialization. STEST is read on the rising edge of RESET. When
asserted, the processor’s internal self-test and external bus confidence tests are
performed during processor initialization. When deasserted, only the bus
confidence tests are performed during initialization.
S(L)
H(Z)
R(Z)
I
ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE
is continuously sampled while RESET is low and is latched on the rising edge of
RESET. To place the processor in the ONCE state:
A(L)
H(Z)
R(Z)
(1) assert RESET and ONCE (order does not matter)
(2) wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN periods in
1-x mode—after VCC and CLKIN are within operating specifications
(3) deassert RESET
(4) wait at least 32 CLKIN periods
(The processor will now be latched in the ONCE state as long as RESET is high.)
To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert
RESET and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions of the processor until
Step 4 above has been completed. CLKIN may then be changed to DC to achieve
the lowest possible ONCE mode leakage current.
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board.
8
80960CA-33, -25, -16
Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 2 of 2)
Name
CLKIN
Type
Description
I
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
A(E)
H(Z)
R(Z)
CLKMODE
PCLK2:1
I
CLOCK MODE selects the division factor applied to the external clock input
(CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and
the processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to
create PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high
or low in a system as the clock mode is not latched by the processor. If left
unconnected, the processor will internally pull the CLKMODE pin low, enabling the
2-x clock mode.
A(L)
H(Z)
R(Z)
O
S
H(Q)
R(Q)
PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor
inputs and outputs. All input and output timings are specified in relation to PCLK2
and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided
to allow flexibility in the system’s allocation of capacitive loading on the clock.
PCLK2:1 may also be connected at the processor to form a single clock signal.
VSS
–
–
–
GROUND connections must be connected externally to a VSS board plane.
POWER connections must be connected externally to a VCC board plane.
VCC
VCCPLL
VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.
Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in
noisy environments. Otherwise, VCCPLL should be connected to VCC. This pin is
implemented starting with the D-stepping. See Table 13 for die stepping
information.
NC
–
NO CONNECT pins must not be connected in a system.
9
80960CA-33, -25, -16
Table 5. 80960CA Pin Description — DMA and Interrupt Unit Control Signals
Name
Type
Description
DREQ3:0
I
DMA REQUEST causes a DMA transfer to be requested. Each of the four signals
requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1
requests channel 1, etc. When two or more channels are requested simulta-
neously, the channel with the highest priority is serviced first. The channel priority
mode is programmable.
A(L)
H(Z)
R(Z)
DACK3:0
O
S
H(1)
DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of
the four signals acknowledges a transfer for a single channel. DACK0 acknowl-
edges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted
when the requesting device of a DMA is accessed.
R(1)
EOP/TC3:0
I/O
A(L)
H(Z/Q)
R(Z)
END OF PROCESS/TERMINAL COUNT can be programmed as either an input
(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually program-
mable. When programmed as an input, EOPx causes the termination of a current
DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds
to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured
for source and destination chaining, the EOP pin for that channel causes
termination of only the current buffer transferred and causes the next buffer to be
transferred. EOP3:0 are asynchronous inputs.
When programmed as an output, the channel’s TCx pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx is driven with the same
timing as DACKx during the last DMA transfer for a buffer. If the last bus request is
executed as multiple bus accesses, TCx will stay asserted for the entire bus
request.
XINT7:0
I
EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can
A(E/L)
H(Z)
R(Z)
be configured in three modes:
Dedicated Mode:
each pin is a dedicated external interrupt source. Dedicated
inputs can be individually programmed to be level (low) or
edge (falling) activated.
Expanded Mode:
the eight pins act together as an 8-bit vectored interrupt
source. The interrupt pins in this mode are level activat-
ed.Since the interrupt pins are active low, the vector number
requested is the one’s complement of the positive logic
value place on the port. This eliminates glue logic to
interface to combinational priority encoders which output
negative logic.
Mixed Mode:
XINT7:5 are dedicated sources and XINT4:0 act as the five
most significant bits of an expanded mode vector. The least
significant bits are set to 010 internally.
NMI
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated
source.
A(E)
H(Z)
R(Z)
10
80960CA-33, -25, -16
80960CA PGA pinout as viewed from the top side of
the component (i.e., pins facing down). Figure 3
shows the complete 80960CA PGA pinout as viewed
from the pin-side of the package (i.e., pins facing up).
See Section 4.0, ELECTRICAL SPECIFICATIONS
for specifications and recommended connections.
3.3 80960CA Mechanical Data
3.3.1 80960CA PGA Pinout
Tables 6 and 7 list the 80960CA pin names with
package location. Figure 2 depicts the complete
Table 6. 80960CA PGA Pinout — In Signal Order
Data Bus Bus Control Processor Control
Signal Pin Signal Pin
R3 BE3
Address Bus
I/O
Signal
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
Pin
S15
Q13
R14
Q14
S16
R15
S17
Q15
R16
R17
Q16
P15
P16
Q17
P17
N16
N17
M17
L16
L17
K17
J17
Signal
RESET
Pin
Signal
DREQ3
DREQ2
DREQ1
DREQ0
Pin
A7
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
S5
S6
S7
R9
A16
Q5
S2
Q4
R2
Q3
S1
R1
Q2
P3
Q1
P2
P1
N2
N1
M1
L1
BE2
BE1
BE0
B6
A6
B5
FAIL
A2
B2
C3
STEST
ONCE
W/R
ADS
S10
R6
DACK3
DACK2
DACK1
DACK0
A10
A9
A8
CLKIN
C13
C14
B14
B13
B8
READY
BTERM
S3
R4
CLKMODE
PLCK1
EOP/TC3
EOP/TC2
EOP/TC1
EOP/TC0
A14
A13
A12
A11
PLCK2
WAIT
S12
S8
BLAST
VSS
Location
DT/R
DEN
S11
S9
C7, C8, C9, C10,
C11, C12, F15, G3,
G15, H3, H15, J3,
J15, K3, K15, L3,
L15, M3, M15, Q7,
Q8, Q9, Q10, Q11
XINT7
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
C17
C16
B17
C15
B16
A17
A15
B15
L2
K1
J1
LOCK
S14
H1
H2
G1
F1
E1
F2
D1
E2
C1
D2
C2
E3
VCC
HOLD
HOLDA
BREQ
R5
Location
H17
G17
G16
F17
E17
E16
D17
D16
S4
B7, B9, B11, B12,
C6, E15, F3, F16,
G2, H16, J2, J16, K2,
K16, M2, M16, N3,
N15, Q6, R7, R8,
R10, R11
A8
D8
R13
A7
D7
NMI
D15
A6
D6
D/C
S13
R12
Q12
A5
D5
DMA
SUP
A4
D4
VCCPLL
B10
A3
D3
No Connect
A2
D2
BOFF
B1
Location
D1
A1, A3, A4, A5, B3,
B4, C4, C5, D3
D0
11
80960CA-33, -25, -16
Table 7. 80960CA PGA Pinout — In Pin Order
Pin
A1
Signal
NC
Pin
C1
Signal
D3
Pin
G1
Signal
D9
Pin
M1
Signal
D16
Pin
R1
Signal
D24
A2
FAIL
C2
D1
G2
VCC
VSS
VSS
A7
M2
VCC
VSS
VSS
VCC
A14
R2
D27
A3
NC
C3
ONCE
NC
G3
M3
R3
D31
A4
NC
C4
G15
G16
G17
M15
M16
M17
R4
BTERM
HOLD
ADS
VCC
A5
NC
C5
NC
R5
A6
DREQ1
DREQ3
DACK1
DACK2
DACK3
EOP/TC0
EOP/TC1
EOP/TC2
EOP/TC3
XINT1
RESET
XINT2
C6
VCC
A8
R6
A7
C7
VSS
R7
A8
C8
VSS
H1
D11
D10
VSS
VSS
VCC
A9
N1
D17
D18
VCC
VCC
A16
A15
R8
VCC
A9
C9
VSS
H2
N2
R9
BE0
VCC
A10
A11
A12
A13
A14
A15
A16
A17
C10
C11
C12
C13
C14
C15
C16
C17
VSS
H3
N3
R10
R11
R12
R13
R14
R15
R16
R17
VSS
H15
H16
H17
N15
N16
N17
VCC
VSS
DMA
BREQ
A29
CLKIN
CLKMODE
XINT4
XINT6
XINT7
J1
D12
VCC
VSS
VSS
VCC
A10
P1
D19
D20
D22
A20
A19
A17
A26
J2
P2
A23
J3
P3
A22
J15
J16
J17
P15
P16
P17
B1
BOFF
STEST
NC
D1
D5
D2
NC
NMI
A2
S1
D25
B2
D2
S2
D29
B3
D3
S3
READY
HOLDA
BE3
B4
NC
D15
D16
D17
K1
D13
VCC
VSS
VSS
VCC
A11
Q1
D21
D23
D26
D28
D30
VCC
VSS
VSS
VSS
VSS
VSS
SUP
A30
A28
A24
A21
A18
S4
B5
DREQ0
DREQ2
VCC
K2
Q2
S5
B6
A3
K3
Q3
S6
BE2
B7
K15
K16
K17
Q4
S7
BE1
B8
DACK0
VCC
E1
D7
D4
D0
VCC
A4
A5
Q5
S8
BLAST
DEN
W/R
B9
E2
Q6
S9
B10
B11
B12
B13
B14
B15
B16
B17
VCCPLL
VCC
E3
Q7
S10
S11
S12
S13
S14
S15
S16
S17
E15
E16
E17
L1
D15
D14
VSS
VSS
A13
A12
Q8
DT/R
WAIT
D/C
VCC
L2
Q9
PCLK2
PCLK1
XINT0
XINT3
XINT5
L3
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
L15
L16
L17
LOCK
A31
F1
D8
F2
D6
A27
F3
VCC
VSS
VCC
A6
A25
F15
F16
F17
12
80960CA-33, -25, -16
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
1
2
D25
D29
D24
D27
D21
D23
D26
D19
D20
D22
D17
D18
D16
D15
D14
D13
D12
D11
D10
D9
D8
D6
D7
D4
D0
D5
D2
NC
D3
D1
BOFF
STEST
NC
NC
FAIL
NC
V
V
V
V
V
V
V
CC
CC
CC
CC
3
3
READY D31
V
V
V
V
V
ONCE
NC
CC
SS
SS
SS
SS
SS
SS
CC
4
4
HOLDA BTERM D28
BE3 HOLD D30
NC
NC
5
5
NC DREQ0
NC
6
6
BE2
BE1
ADS
V
V
V
V
V
V
V
DREQ2 DREQ1
CC
SS
SS
SS
SS
SS
CC
7
7
V
V
V
V
V
V
CC
DREQ3
CC
SS
SS
SS
SS
8
8
BLAST
DEN
V
DACK0 DACK1
CC
9
9
BE0
V
DACK2
DACK3
CC
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
W/R
V
V
V
CCPLL
CC
CC
DT/R
WAIT
V
V
V
EOP/TC0
EOP/TC1
SS
CC
DMA
SUP
A30
A28
A24
A21
A18
Q
V
CC
SS
D/C BREQ
LOCK A29
CLKIN PCLK2 EOP/TC2
CLK MODE PCLK1 EOP/TC3
NMI XINT4 XINT0 XINT1
A31
A27
A25
S
A26
A23
A22
R
A20
A19
A17
P
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
SS
SS
SS
SS
SS
SS
SS
A16
A15
N
V
A13
A12
L
A7
A4
A2
A3
XINT6 XINT3 RESET
XINT7 XINT5 XINT2
CC
CC
CC
CC
CC
A14
A11
A10
A9
A8
A6
A5
M
K
J
H
G
F
E
D
C
B
A
F_CA002A
Figure 2. 80960CA PGA Pinout — View from Top (Pins Facing Down)
13
80960CA-33, -25, -16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
1
2
1
2
NC
FAIL
NC
BOFF
STEST
NC
D3
D1
D5
D2
NC
D7
D4
D0
D8
D6
D9
D11
D10
D12
D13
D15
D14
D16
D17
D18
D19
D20
D22
D21
D23
D26
D24
D27
D25
D29
V
V
V
V
V
V
V
CC
CC
CC
CC
3
3
ONCE
NC
V
V
V
V
V
D31 READY
CC
SS
SS
SS
SS
SS
SS
CC
4
4
NC
NC
D28 BTERM HOLDA
D30 HOLD BE3
5
5
NC
DREQ0 NC
6
6
DREQ1 DREQ2
V
V
V
V
V
V
V
ADS
BE2
BE1
CC
SS
SS
SS
SS
CC
7
7
DREQ3
V
V
CC
SS
CC
8
8
DACK1 DACK0
V
V
V
BLAST
DEN
SS
SS
CC
Metal Lid
9
9
DACK2
DACK3
V
BE0
CC
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
V
V
V
V
V
W/R
CCPLL
SS
SS
CC
EOP/TC0
EOP/TC1
V
V
V
DT/R
CC
SS
SS
CC
V
SUP
DMA WAIT
CC
EOP/TC2 PCLK2 CLKIN
A30 BREQ
D/C
LOCK
A31
EOP/TC3 PCLK1 CLK MODE
XINT1 XINT0 XINT4 NMI
A28
A24
A29
A26
V
V
V
V
V
V
V
V
V
V
V
CC
A20
CC
SS
SS
SS
SS
SS
SS
SS
RESET XINT3 XINT6
XINT2 XINT5 XINT7
A2
A3
D
A4
V
A7
V
A13
A12
L
V
A16
A15
N
A19
A17
P
A21
A18
Q
A23
A22
R
A27
A25
S
CC
CC
CC
CC
CC
A5
A6
A8
A9
A10
A11
A14
A
B
C
E
F
G
H
J
K
M
F_CA003A
Figure 3. 80960CA PGA Pinout — View from Bottom (Pins Facing Up)
14
80960CA-33, -25, -16
3.3.2 80960CA PQFP Pinout
See Section 4.0, ELECTRICAL SPECIFICATIONS
for specifications and recommended connections.
Tables 8 and 9 list the 80960CA pin names with
package location. Figure 4 shows the 80960CA
PQFP pinout as viewed from the top side.
Table 8. 80960CA PQFP Pinout — In Signal Order
Data Bus Bus Control Processor Control
Signal Signal Pin Signal Pin
D31 BE3 RESET 91
Address Bus
Signal Pin
A31
I/O
Signal
Pin
186
187
188
189
191
192
194
195
3
Pin
60
153
152
151
145
144
143
142
141
139
138
137
136
134
133
132
130
176
175
172
170
DREQ3
DREQ2
DREQ1
DREQ0
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
BE2
BE1
BE0
FAIL
45
46
43
87
85
74
78
59
58
57
STEST
ONCE
CLKIN
CLKMODE
PCLK2
PCLK1
W/R
ADS
164
178
DACK3
DACK2
DACK1
DACK0
65
64
63
62
VSS
Location
4
READY
BTERM
182
184
5
2, 7, 16, 24, 30, 38,
39, 49, 56, 70, 75,
77, 81, 83, 88, 89,
92, 98, 105, 109,
110, 121, 125, 131,
135, 147, 150, 161,
165, 173, 174, 185,
196
EOP/TC3
EOP/TC2
EOP/TC1
EOP/TC0
69
68
67
66
6
8
WAIT
162
169
9
BLAST
10
11
DT/R
DEN
163
167
XINT7
107
A15
A14
A13
A12
A11
A10
A9
129
128
124
123
122
120
119
118
117
116
114
113
112
111
D15
D14
D13
D12
D11
D10
D9
13
14
15
17
18
19
21
22
23
25
26
27
33
34
35
36
VCC
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
106
102
101
100
95
Location
LOCK
156
1, 12, 20, 28, 32, 37,
44, 50, 61, 71, 79,
82, 96, 99, 103, 115,
127, 140, 148, 154,
168, 171, 180, 190
HOLD
HOLDA
BREQ
181
179
155
94
93
A8
D8
VCCPLL
72
A7
D7
D/C
159
160
158
No Connect
NMI
108
A6
D6
DMA
SUP
Location
A5
D5
29, 31, 41, 42, 47,
48, 51, 52, 53, 54,
55, 73, 76, 80, 84,
86, 90, 97, 104, 126,
146, 149, 157, 166,
177, 183, 193
A4
D4
A3
D3
BOFF
40
A2
D2
D1
D0
15
80960CA-33, -25, -16
Pin Signal Pin
Table 9. 80960CA PQFP Pinout — In Pin Order
Signal
D2
Pin
67
Signal
EOP/TC1
EOP/TC2
EOP/TC3
VSS
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
Signal
XINT3
XINT4
XINT5
VCC
NC
Pin
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
Signal
A18
A19
VSS
Pin
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
Signal
NC
1
VCC
VSS
D23
D22
D21
D20
VSS
D19
D18
D17
D16
VCC
D15
D14
D13
VSS
D12
D11
D10
VCC
D9
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
2
D1
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DEN
VCC
3
D0
4
VCC
VSS
VSS
BOFF
NC
A20
A21
A22
A23
VCC
A24
A25
A26
A27
A28
NC
BLAST
BE0
VCC
5
VCC
6
VCCPLL
NC
VSS
7
XINT6
XINT7
NMI
VSS
BE1
VSS
8
PCLK2
VSS
9
NC
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
ONCE
NC
BE2
BE3
NC
V
VSS
VSS
CC
FAIL
PCLK1
VCC
A2
STEST
NC
A3
ADS
HOLDA
VCC
NC
A4
NC
VSS
A5
VSS
VSS
VCC
VCC
A6
VCC
NC
HOLD
READY
NC
VCC
VSS
NC
NC
A7
VSS
NC
CLKMODE 118
A8
A29
A30
A31
VCC
BREQ
LOCK
NC
BTERM
VSS
NC
NC
119
120
121
122
123
124
125
126
127
128
129
130
131
132
A9
NC
CLKIN
VSS
A10
D31
D30
D29
D28
VCC
D8
NC
V
SS
D7
VSS
V
A11
A12
A13
VSS
NC
SS
VSS
D6
DREQ0
DREQ1
DREQ2
DREQ3
VCC
NC
RESET
VSS
D5
SUP
D/C
D27
D26
NC
D4
XINT0
XINT1
XINT2
VCC
VCC
NC
V
DMA
VSS
CC
DACK0
DACK1
DACK2
DACK3
EOP/TC0
A14
A15
A16
VSS
A17
D25
D24
VSS
VSS
NC
WAIT
DT/R
W/R
VSS
NC
VCC
D3
VSS
VCC
16
80960CA-33, -25, -16
98
50
99
49
147
Pin 1
196
148
F_CA004A
Figure 4. 80960CA PQFP Pinout (View from Top Side)
17
80960CA-33, -25, -16
TA = TC – P*θCA
3.4 Package Thermal Specifications
Table 10 shows the maximum TA allowable (without
exceeding TC) at various airflows and operating
frequencies (fPCLK).
The 80960CA is specified for operation when TC
(case temperature) is within the range of 0oC–100oC.
TC may be measured in any environment to deter-
mine whether the 80960CA is within specified oper-
ating range. Case temperature should be measured
at the center of the top surface, opposite the pins.
Refer to Figure 5.
Note that TA is greatly improved by attaching fins or a
heatsink to the package.
P (maximum power
consumption) is calculated by using the typical ICC
as tabulated in Section 4.4, DC Specifications and
VCC of 5V.
TA (ambient temperature) can be calculated from θCA
(thermal resistance from case to ambient) using the
following equation:
Measure PGA temperature at
center of top surface
Measure PQFP case temperature
at center of top surface.
168 - Pin PGA
Pin 196
Pin 1
F_CX007A
Figure 5. Measuring 80960CA PGA and PQFP Case Temperature
Table 10. Maximum TA at Various Airflows in oC (PGA Package Only)
Airflow-ft/min (m/sec)
0
200
400
600
800
1000
fPCLK
(MHz)
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.07)
33
25
16
51
61
74
66
73
82
79
83
89
81
85
90
85
88
92
87
89
93
TA with
Heatsink*
33
25
16
36
49
66
47
58
72
59
67
78
66
73
82
73
78
86
75
80
87
TA without
Heatsink*
NOTES:
*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
18
80960CA-33, -25, -16
Table 11. 80960CA PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.07)
(4.06)
(5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5)
θJA
1.5
1.5
1.5
1.5
1.5
1.5
θJC
θ Case-to-Ambient
(No Heatsink)
17
13
14
9
11
9
5
7.1
3.9
6.6
3.4
θ Case-to-Ambient
(With Heatsink)*
5.5
NOTES:
1. This table applies to 80960CA PGA plugged into socket or soldered directly to board.
2. = θ + θ
θ
JA
JC
CA
*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 12. 80960CA PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θ Junction-to-Case (Case Measured
as shown in Figure 5)
5
5
5
5
5
5
5
9
θ Case-to-Ambient (No Heatsink)
19
18
17
15
12
10
NOTES:
1. This table applies to 80960CA PQFP soldered directly to board.
2. = θ + θ
θ
JA
JC
CA
θ
JC
19
80960CA-33, -25, -16
3.5 Stepping Register Information
3.6 Suggested Sources for 80960CA
Accessories
Upon reset, register g0 contains die stepping infor-
mation. Figure 6 shows how g0 is configured. The
most significant byte contains an ASCII 0. The upper
middle byte contains an ASCII C. The lower middle
byte contains an ASCII A. The least significant byte
contains the stepping number in ASCII. g0 retains
this information until it is overwritten by the user
program.
The following is a list of suggested sources for
80960CA accessories. This is not an endorsement of
any kind, nor is it a warranty of the performance of
any of the listed products and/or companies.
Sockets
1. 3M Textool Test and Interconnection
Products Department
P.O. Box 2963
Austin, TX 78769-2963
ASCII
00
0
43
C
41 Stepping Number
DECIMAL
A
Stepping Number
LSB
2. Augat, Inc.
Interconnection Products Group
33 Perry Avenue
MSB
P.O. box 779
Attleboro, MA 02703
(508) 699-7646
Figure 6. Register g0
Table 13 contains a cross reference of the number in
the least significant byte of register g0 to the die
stepping number.
3. Concept Manufacturing, Inc.
(Decoupling Sockets)
41484 Christy Street
Fremont, CA 94538
Table 13. Die Stepping Cross Reference
(415) 651-3804
g0 Least Significant
Die Stepping
Byte
Heatsinks/Fins
1. Thermalloy, Inc.
01
02
03
04
B
C-1
2021 West Valley View Lane
Dallas, TX 75234-8993
(214) 243-4321
C-2,C-3
D
FAX: (214) 241-4656
2. E G & G Division
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
20
80960CA-33, -25, -16
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings
NOTICE: This is a production data sheet. The
specifications are subject to change without notice.
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause perma-
nent damage. These are stress ratings only. Opera-
tion beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
Parameter
Maximum Rating
o
o
Storage Temperature ................................–65 C to +150 C
o
o
Case Temperature Under Bias .................–65 C to +110 C
Supply Voltage wrt. V ............................. –0.5V to + 6.5V
SS
Voltage on Other Pins wrt. V ...........–0.5V to V
SS
+ 0.5V
CC
4.2 Operating Conditions
Table 14. Operating Conditions (80960CA-33, -25, -16)
Symbol
Parameter
Min
Max
Units
Notes
VCC
Supply Voltage
80960CA-33
80960CA-25
80960CA-16
4.75
4.50
4.50
5.25
5.50
5.50
V
V
V
fCLK2x
Input Clock Frequency (2-x Mode)
Input Clock Frequency (1-x Mode)
80960CA-33
80960CA-25
80960CA-16
0
0
0
66.66
50
32
MHz
MHz
MHz
fCLK1x
80960CA-33
80960CA-25
80960CA-16
8
8
8
33.33
25
16
MHz
MHz
MHz
(1)
TC
Case Temperature Under Bias
80960CA-33, -25, -16
PGA Package
196-Pin PQFP
0
0
100
100
oC
oC
NOTES:
1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum fre-
quency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the pro-
cessor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once
CLKIN restarts and has stabilized.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
4.3 Recommended Connections
performance. Inductance can be reduced by short-
ening the board traces between the processor and
decoupling capacitors as much as possible. Capaci-
tors specifically designed for PGA packages will offer
the lowest possible inductance.
Power and ground connections must be made to
multiple VCC and VSS (GND) pins. Every 80960CA-
based circuit board should include power (VCC) and
ground (VSS) planes for power distribution. Every
VCC pin must be connected to the power plane, and
every VSS pin must be connected to the ground
plane. Pins identified as “NC” must not be
connected in the system.
For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, any
unused interrupt (XINT, NMI) or DMA (DREQ) input
should be connected to VCC through
a pull-up
Liberal decoupling capacitance should be placed
near the 80960CA. The processor can cause tran-
sient power surges when its numerous output buffers
transition, particularly when connected to large
capacitive loads.
resistor, as should BTERM if not used. Pull-up resis-
tors should be in the in the range of 20 KΩ for each
pin tied high. If READY or HOLD are not used, the
unused input should be connected to ground. N.C.
pins must always remain unconnected. Refer to
the i960 Cx Microprocessor User’s Manual (Order
Number 270710) for more information.
21
80960CA-33, -25, -16
4.4 DC Specifications
Table 15. DC Characteristics
(80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.)
Symbol
VIL
Parameter
Min
– 0.3
2.0
Max
+0.8
Units
V
Notes
Input Low Voltage for all pins except RESET
Input High Voltage for all pins except RESET
Output Low Voltage
VIH
VCC + 0.3
0.45
V
VOL
V
IOL = 5 mA
VOH
Output High Voltage
IOH = –1 mA
IOH = – 200 µA
2.4
VCC – 0.5
V
V
VILR
VIHR
ILI1
Input Low Voltage for RESET
Input High Voltage for RESET
– 0.3
3.5
1.5
V
V
VCC + 0.3
Input Leakage Current for each pin except:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY,
HOLD, CLKMODE
±15
µA
µA
0 ≤ VIN ≤ VCC (1)
ILI2
Input Leakage Current for:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF
0
0
– 300
V
IN = 0.45V (2)
IN = 2.4V (3,7)
ILI3
Input Leakage Current for:
READY, HOLD, CLKMODE
500
±15
µA
µA
V
ILO
ICC
Output Leakage Current
0.45 ≤ VOUT ≤ VCC
Supply Current (80960CA-33):
ICC Max
ICCTyp
900
750
mA
mA
(4)
(5)
ICC
Supply Current (80960CA-25):
ICC Max
ICCTyp
750
600
mA
mA
(4)
(5)
ICC
Supply Current (80960CA-16):
ICC Max
ICCTyp
550
400
mA
mA
(4)
(5)
IONCE
CIN
ONCE-mode Supply Current
100
mA
Input Capacitance for:
CLKIN, RESET, ONCE,
READY, HOLD, DREQ3:0, BOFF,
XINT7:0, NMI, BTERM, CLKMODE
0
12
12
12
pF
pF
pF
FC = 1 MHz
FC = 1 MHz (6)
FC = 1 MHz
COUT
Output Capacitance of each output pin
I/O Pin Capacitance
CI/O
NOTES:
1. No pullup or pulldown.
2. These pins have internal pullup resistors.
3. These pins have internal pulldown resistors.
4. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Sec-
tion 4.5.1, AC Test Conditions.
5.
ICC Typical is not tested.
6. Output Capacitance is the capacitive load of a floating output.
7. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.
22
80960CA-33, -25, -16
4.5 AC Specifications
Table 16. 80960CA AC Characteristics (33 MHz)
(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test
Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock (1,9)
T
T
CLKIN Frequency
CLKIN Period
0
66.66
MHz
F
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
30
15
125
∞
ns
ns
(11)
C
)
CLK2x
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
CLK1x
±0.1%
∆
(12)
(11)
CS
CH
In 1-x Mode (f
In 2-x Mode (f
)
)
6
6
62.5
∞
ns
ns
CLK1x
CLK2x
T
CLKIN Low Time
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
6
6
62.5
∞
ns
ns
(11)
CL
)
T
T
CLKIN Rise Time
CLKIN Fall Time
0
0
6
6
ns
ns
CR
CF
Output Clocks (1,8)
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
– 2
2
2
25
ns
ns
(3,12)
(3)
CP
)
T
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
T
2T
ns
ns
(12)
(3)
CLK1x
C
C
)
CLK2x
T
T
T
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
PCLK2:1 Fall Time
(T/2) – 2
T/2
T/2
4
ns
ns
ns
ns
(12)
(12)
(3)
PH
PL
PR
PF
(T/2) – 2
1
1
4
(3)
Synchronous Outputs (8)
T
T
Output Valid Delay, Output Hold
(6,10)
OH
OV
T
T
T
T
T
T
T
T
T
T
T
T
T
T
, T
A31:2
BE3:0
ADS
3
3
6
3
4
5
3
4
14
16
18
18
16
16
16
16
16
18
16
T/2 + 14
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OH1 OV1
, T
OH2 OV2
, T
OH3 OV3
, T
W/R
OH4 OV4
, T
D/C, SUP, DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
DACK3:0
D31:0
DT/R
FAIL
EOP3:0/TC3:0
OH5 OV5
, T
OH6 OV6
, T
OH7 OV7
, T
OH8 OV8
, T
4
4
3
OH9 OV9
, T
OH10 OV10
, T
OH11 OV11
, T
T/2 + 3
2
3
OH12 OV12
, T
OH13 OV13
, T
OH14 OV14
18
(6,10)
(6)
T
Output Float for all outputs
3
22
ns
OF
Synchronous Inputs (1,9,10)
T
Input Setup
IS
T
T
T
T
D31:0
BOFF
BTERM/READY
3
17
7
ns
ns
ns
ns
IS1
IS2
IS3
IS4
HOLD
7
T
Input Hold
IH
T
T
T
T
D31:0
BOFF
BTERM/READY
5
5
2
3
ns
ns
ns
ns
IH1
IH2
IH3
IH4
HOLD
23
80960CA-33, -25, -16
Table 16. 80960CA AC Characteristics (33 MHz) (Continued)
(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test
Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Relative Output Timings (1,2,3,8)
T
A31:2 Valid to ADS Rising
T – 4
T + 4
ns
AVSH1
T
BE3:0, W/R, SUP, D/C,
AVSH2
DMA, DACK3:0 Valid to ADS Rising
T – 6
T – 4
T + 6
T + 4
ns
ns
T
A31:2 Valid to DEN Falling
AVEL1
T
BE3:0, W/R, SUP, INST,
AVEL2
DMA, DACK3:0 Valid to DEN Falling
T – 6
T + 6
ns
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
± 4
NLQV
DVNH
NLNH
NHQX
EHTV
TVEL
N*T – 4
N*T + 4
(4)
N*T ± 4
(4)
(5)
(6)
(N+1)*T–8
T/2 – 7
(N+1)*T+6
∞
DT/R Valid to DEN Falling
T/2 – 4
Relative Input Timings (1,2,3)
T
T
T
T
T
T
T
T
RESET Input Setup (2-x Clock Mode)
RESET Input Hold (2-x Clock Mode)
DREQ3:0 Input Setup
6
ns
ns
ns
ns
ns
ns
ns
ns
(13)
(13)
(7)
IS5
IH5
IS6
IH6
IS7
IH7
IS8
IH8
5
12
DREQ3:0 Input Hold
7
(7)
XINT7:0, NMI Input Setup
7
(15)
(15)
(14)
(14)
XINT7:0, NMI Input Hold
3
3
RESET Input Setup (1-x Clock Mode)
RESET Input Hold (1-x Clock Mode)
T/4 + 1
NOTES:
1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
2. See Figure 16 for capacitive derating information for output delays and hold times.
3. See Figure 17 for capacitive derating information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes
active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for
proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-
chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.
8. These specifications are guaranteed by the processor.
9. These specifications must be met by the system for proper operation of the processor.
10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for
PCLK2:1 loading.
11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in
reset, the input clock may stop even in 1-x mode.
12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-
cent cycles.
13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the
CLKIN. (See Figure 22.)
14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.
(See Figure 23.)
15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins
are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-
ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-
tive PCLK2:1 rising edges.
24
80960CA-33, -25, -16
Table 17. 80960CA AC Characteristics (25 MHz)
(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test
Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock (1,9)
T
T
CLKIN Frequency
CLKIN Period
0
50
MHz
F
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
40
20
125
∞
ns
ns
(11)
C
)
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
CLK1x
±0.1%
∆
(12)
(11)
CS
CH
In 1-x Mode (f
In 2-x Mode (f
)
)
8
8
62.5
∞
ns
ns
CLK1x
CLK2x
T
CLKIN Low Time
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
8
8
62.5
∞
ns
ns
(11)
CL
)
T
T
CLKIN Rise Time
CLKIN Fall Time
0
0
6
6
ns
ns
CR
CF
Output Clocks (1,8)
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
– 2
2
2
25
ns
ns
(3,12)
(3)
CP
)
T
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
T
2T
ns
ns
(12)
(3)
CLK1x
C
C
)
CLK2x
T
T
T
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
PCLK2:1 Fall Time
(T/2) – 3
T/2
T/2
4
ns
ns
ns
ns
(12)
(12)
(3)
PH
PL
PR
PF
(T/2) – 3
1
1
4
(3)
Synchronous Outputs (8)
T
T
Output Valid Delay, Output Hold
(6,10)
OH
OV
T
T
T
T
T
T
T
T
T
T
T
T
T
T
, T
A31:2
BE3:0
ADS
3
3
6
3
4
5
3
4
16
18
20
20
18
18
18
18
18
20
18
T/2 + 16
16
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OH1 OV1
, T
OH2 OV2
, T
OH3 OV3
, T
W/R
OH4 OV4
, T
D/C, SUP, DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
DACK3:0
D31:0
DT/R
FAIL
EOP3:0/TC3:0
OH5 OV5
, T
OH6 OV6
, T
OH7 OV7
, T
OH8 OV8
, T
4
4
3
OH9 OV9
, T
OH10 OV10
, T
OH11 OV11
, T
OH12 OV12
T/2 + 3
2
3
, T
OH13 OV13
, T
(6,10)
(6)
OH14 OV14
T
Output Float for all outputs
3
22
ns
OF
Synchronous Inputs (1,9,10)
T
Input Setup
IS
T
T
T
T
D31:0
BOFF
BTERM/READY
HOLD
5
19
9
ns
ns
ns
ns
IS1
IS2
IS3
IS4
9
T
Input Hold
IH
T
T
T
T
D31:0
BOFF
BTERM/READY
HOLD
5
7
2
5
ns
ns
ns
ns
IH1
IH2
IH3
IH4
25
80960CA-33, -25, -16
Table 17. 80960CA AC Characteristics (25 MHz) (Continued)
(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test
Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Relative Output Timings (1,2,3,8)
T
A31:2 Valid to ADS Rising
T – 4
T + 4
ns
AVSH1
T
BE3:0, W/R, SUP, D/C,
AVSH2
DMA, DACK3:0 Valid to ADS Rising
T – 6
T – 4
T + 6
T + 4
ns
ns
T
A31:2 Valid to DEN Falling
AVEL1
T
BE3:0, W/R, SUP, INST,
AVEL2
DMA, DACK3:0 Valid to DEN Falling
T – 6
T + 6
ns
ns
ns
ns
T
T
T
T
T
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
± 4
NLQV
DVNH
NLNH
NHQX
EHTV
TVEL
N*T – 4
N*T + 4
(4)
N*T ± 4
(N+1)*T–8
(4)
(5)
(6)
(N+1)*T+6 ns
T/2 – 7
T/2 – 4
∞
ns
ns
DT/R Valid to DEN Falling
Relative Input Timings (1,2,3)
T
T
T
T
T
T
T
T
RESET Input Setup (2-x Clock Mode)
RESET Input Hold (2-x Clock Mode)
DREQ3:0 Input Setup
8
ns
ns
ns
ns
ns
ns
ns
ns
(13)
(13)
(7)
IS5
IH5
IS6
IH6
IS7
IH7
IS8
IH8
7
14
DREQ3:0 Input Hold
9
(7)
XINT7:0, NMI Input Setup
9
(15)
(15)
(14)
(14)
XINT7:0, NMI Input Hold
5
3
RESET Input Setup (1-x Clock Mode)
RESET Input Hold (1-x Clock Mode)
T/4 + 1
NOTES:
1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
2. See Figure 16 for capacitive derating information for output delays and hold times.
3. See Figure 17 for capacitive derating information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes
active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for
proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-
chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.
8. These specifications are guaranteed by the processor.
9. These specifications must be met by the system for proper operation of the processor.
10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for
PCLK2:1 loading.
11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in
reset, the input clock may stop even in 1-x mode.
12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-
cent cycles.
13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the
CLKIN. (See Figure 22.)
14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.
(See Figure 23.)
15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins
are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-
ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-
tive PCLK2:1 rising edges.
26
80960CA-33, -25, -16
Table 18. 80960CA AC Characteristics (16 MHz)
(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock (1,9)
T
T
CLKIN Frequency
CLKIN Period
0
32
MHz
F
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
62.5
31.25
125
∞
ns
ns
(11)
C
)
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
CLK1x
±0.1%
∆
(12)
(11)
CS
CH
In 1-x Mode (f
In 2-x Mode (f
)
)
10
10
62.5
∞
ns
ns
CLK1x
CLK2x
T
CLKIN Low Time
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
10
10
62.5
∞
ns
ns
(11)
CL
)
T
T
CLKIN Rise Time
CLKIN Fall Time
0
0
6
6
ns
ns
CR
CF
Output Clocks (1,8)
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (f
In 2-x Mode (f
)
CLK1x
CLK2x
– 2
2
2
25
ns
ns
(3,12)
(3)
CP
)
T
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
T
2T
ns
ns
(12)
(3)
CLK1x
C
C
)
CLK2x
T
T
T
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
PCLK2:1 Fall Time
(T/2) – 4
T/2
T/2
4
ns
ns
ns
ns
(12)
(12)
(3)
PH
PL
PR
PF
(T/2) – 4
1
1
4
(3)
Synchronous Outputs (8)
T
T
Output Valid Delay, Output Hold
, T
(6,10)
OH
OV
T
A31:2
BE3:0
ADS
3
3
6
3
4
5
3
4
18
20
22
22
20
20
20
20
20
22
20
T/2 + 18
18
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OH1 OV1
T
, T
OH2 OV2
, T
T
OH3 OV3
T
, T
, T
W/R
OH4 OV4
T
D/C, SUP, DMA
BLAST, WAIT
DEN
OH5 OV5
, T
T
OH6 OV6
T
, T
, T
OH7 OV7
T
HOLDA, BREQ
OH8 OV8
, T
T
T
LOCK
DACK3:0
D31:0
4
4
3
OH9 OV9
, T
, T
OH10 OV10
T
OH11 OV11
, T
T
DT/R
FAIL
EOP3:0/TC3:0
T/2 + 3
2
3
OH12 OV12
, T
T
OH13 OV13
T
, T
(6,10)
(6)
OH14 OV14
T
Output Float for all outputs
3
22
ns
OF
Synchronous Inputs (1,9,10)
T
Input Setup
IS
T
T
T
T
D31:0
BOFF
BTERM/READY
HOLD
5
21
9
ns
ns
ns
ns
IS1
IS2
IS3
IS4
9
T
Input Hold
IH
T
T
T
T
D31:0
BOFF
BTERM/READY
HOLD
5
7
2
5
ns
ns
ns
ns
IH1
IH2
IH3
IH4
27
80960CA-33, -25, -16
Table 18. 80960CA AC Characteristics (16 MHz) (Continued)
(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
Relative Output Timings (1,2,3,8)
T
A31:2 Valid to ADS Rising
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
T – 4
T + 4
ns
AVSH1
T
AVSH2
T – 6
T – 6
T + 6
T + 6
ns
ns
T
A31:2 Valid to DEN Falling
AVEL1
T
BE3:0, W/R, SUP, INST,
AVEL2
DMA, DACK3:0 Valid to DEN Falling
T – 6
T + 6
ns
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
± 4
NLQV
DVNH
NLNH
NHQX
EHTV
TVEL
N*T – 4
N*T + 4
(4)
N*T ± 4
(4)
(5)
(6)
(N+1)*T–8
(N+1)*T+6
T/2 – 7
T/2 – 4
∞
DT/R Valid to DEN Falling
Relative Input Timings (1,2,3)
T
T
T
T
T
T
T
T
RESET Input Setup (2-x Clock Mode)
RESET Input Hold (2-x Clock Mode)
DREQ3:0 Input Setup
10
ns
ns
ns
ns
ns
ns
ns
ns
(13)
(13)
(7)
IS5
IH5
IS6
IH6
IS7
IH7
IS8
IH8
9
16
DREQ3:0 Input Hold
11
(7)
XINT7:0, NMI Input Setup
9
(15)
(15)
(14)
(14)
XINT7:0, NMI Input Hold
5
3
RESET Input Setup (1-x Clock Mode)
RESET Input Hold (1-x Clock Mode)
T/4 + 1
NOTES:
1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
2. See Figure 16 for capacitive derating information for output delays and hold times.
3. See Figure 17 for capacitive derating information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes
active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for
proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-
chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.
8. These specifications are guaranteed by the processor.
9. These specifications must be met by the system for proper operation of the processor.
10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for
PCLK2:1 loading.
11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in
reset, the input clock may stop even in 1-x mode.
12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-
cent cycles.
13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN.
(See Figure 22.)
14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.
(See Figure 23.)
15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are
sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting
them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive
PCLK2:1 rising edges.
28
80960CA-33, -25, -16
4.5.1 AC Test Conditions
The AC Specifications in Section 4.5 are tested with
the 50 pF load shown in Figure 7. Figure 16 shows
how timings vary with load capacitance.
Output Pin
C
L
Specifications are measured at the 1.5V crossing
point, unless otherwise indicated. Input waveforms
are assumed to have a rise and fall time of ≤ 2 ns
from 0.8V to 2.0V. See Section 4.5.2, AC Timing
Waveforms for AC spec definitions, test points and
illustrations.
C
= 50 pF for all signals
L
F_CX008A
Figure 7. AC Test Load
4.5.2 AC Timing Waveforms
1.5V
CLKIN
T
CP
T
2.4V
1.5V
0.45V
1.5V
PCLK2:1
T
T
PL
PH
T
PF
T
PR
F_CX009A
Figure 8. Input and Output Clocks Waveform
T
T
CR
CF
2.0V
1.5V
0.8V
T
CH
T
CL
T
C
F_CX010A
Figure 9. CLKIN Waveform
29
80960CA-33, -25, -16
1.5V
Min
PCLK2:1
1.5V
T
OV
Max
T
OH
Outputs
Outputs
1.5V
1.5V
T
OF
Max
1.5V
Min
1.5V
F_CX011A
Figure 10. Output Delay and Float Waveform
PCLK2:1
1.5V
1.5V
1.5V
T
T
IH
IS
Min
Max
Inputs:
(READY, HOLD, BTERM,
BOFF, DREQ3:0,
Valid
D31:0 on reads)
F_CX012A
Figure 11. Input Setup and Hold Waveform
T
T
- OUTPUT DELAY - The maximum output delay is referred to
OV
OH
as the Output Valid Delay (T ). The minimum output delay is
OV
referred to as the Output Hold (T ).
OH
T
- OUTPUT FLOAT DELAY - The output float condition occurs
OF
when the maximum output current becomes less that I in magnitude.
LO
T
T
- INPUT SETUP AND HOLD - The input setup and hold requirements
specify the sampling window during which synchronous inputs must be
stable for correct processor operation.
IS
IH
30
80960CA-33, -25, -16
PCLK2:1
1.5V
1.5V
1.5V
T
IH
T
IS
Min
1.5V
Min
1.5V
NMI, XINT7:0
Valid
F_CX013A
Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform
1.5V
PCLK2:1
Outputs:
1.5V
OV
1.5V
OF
T
T
Max
Max
Min
Min
A31:2, D31:0, BE3:0,
ADS, BLAST, WAIT, W/R,
DT/R, DEN, LOCK,
1.5V Valid
Valid
D/C, SUP, DMA
T
T
T
IH
IS
Min
IS
T
IH
Min
Min
Min
1.5V
1.5V
1.5V
HOLD
T
T
OV
OV
Min Max
Min Max
HOLDA
1.5V
1.5V
1.5V
T
T
- OUTPUT DELAY - The maximum output delay is referred to
OV
OH
as the Output Valid Delay (T ). The minimum output delay is
OV
referred to as the Output Hold (T ).
OH
T
- OUTPUT FLOAT DELAY - The output float condition occurs
OF
when the maximum output current becomes less that I in magnitude.
LO
T
T
- INPUT SETUP AND HOLD - The input setup and hold requirements
specify the sampling window during which synchronous inputs must be
stable for correct processor operation.
IS
IH
F_CX014A
Figure 13. Hold Acknowledge Timings
31
80960CA-33, -25, -16
1.5V
PCLK2:1
1.5V
OV
1.5V
T
T
OF
Max
Min
Max
Min
Outputs:
A31:2, D31:0, BE3:0,
1.5V Valid
1.5V
Valid
ADS, BLAST, WAIT, W/R,
DT/R, DEN, LOCK,
D/C, SUP, DMA
1.5V
T
T
IS
IS
T
T
IH
IH
BOFF
1.5V
1.5V
1.5V
F_CX015A
Figure 14. Bus Backoff (BOFF) Timings
32
80960CA-33, -25, -16
1.5V
PCLK2:1
ADS
1.5V
1.5V
1.5V
1.5V
1.5V
T
AVSH
A31:2, BE3:0,
W/R, LOCK,
1.5V
SUP, D/C, DMA
1.5V
Out
1.5V
D31:0
T
NLQV
1.5V
T
T
NHQX
DVHN
1.5V
WAIT
DT/R
T
T
AVEL
NLNH
1.5V
T
T
VEL
EHTV
DEN
1.5V
1.5V
V
V
IH
IL
In
D31:0
F_CX016A
Figure 15. Relative Timings Waveforms
4.5.3 Derating Curves
nom + 10
All outputs except: LOCK,
DMA, SUP, BREQ, DACK3:0,
EOP3:0/TC3:0, FAIL
nom + 5
LOCK, DMA, SUP, BREQ,
DACK3:0, EOP3:0/TC3:0, FAIL
nom
50
100
150
C
(pF)
L
Note: PCLK Load = 50pF
F_CX017A
Figure 16. Output Delay or Hold vs. Load Capacitance
33
80960CA-33, -25, -16
0.8V to 2.0V
10
8
0.8V to 2.0V
10
8
6
6
4
2
4
2
50
100
C
150
50
100
C
150
(pF)
(pF)
L
L
a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ
DACK3:0, EOP3:0/TC3:0, FAIL
b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0,
EOP3:0/TC3:0, FAIL
F_CX019A
Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC
900
T
= 100° C
C
T
= 0° C
C
0
33
0
f
(MHz)
PCLK
I
- I
CC CC
under test conditions
Figure 18. ICC vs. Frequency and Temperature
F_CX020A
34
80960CA-33, -25, -16
Table 20 lists the condition of each processor output
pin while HOLDA is asserted (low).
5.0 RESET, BACKOFF AND HOLD
ACKNOWLEDGE
Table 20. Hold Acknowledge
and Backoff Conditions
Table 19 lists the condition of each processor output
pin while RESET is asserted (low).
Pins
State During HOLDA
Floating
Table 19. Reset Conditions
A31:2
D31:0
State During Reset
(HOLDA inactive)1
Floating
Pins
BE3:0
W/R
Floating
A31:2
D31:0
BE3:0
W/R
Floating
Floating
Floating
ADS
Floating
Driven high (Inactive)
Driven low (Read)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Active)
Driven low (Receive)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Inactive)
Floating
WAIT
Floating
BLAST
DT/R
Floating
ADS
Floating
WAIT
DEN
Floating
BLAST
DT/R
LOCK
BREQ
D/C
Floating
Driven (High or low)
Floating
DEN
LOCK
BREQ
D/C
DMA
Floating
SUP
Floating
FAIL
Driven high (Inactive)
Driven high (Inactive)
Driven (If output)
DMA
Floating
DACK3:0
EOP3:0/TC3:0
SUP
Floating
FAIL
Driven low (Active)
Driven high (Inactive)
Floating (Set to input mode)
DACK3:0
EOP3:0/TC3:0
NOTES:
1. With regard to bus output pin state only, the Hold
Acknowledge state takes precedence over the reset
state. Although asserting the RESET pin will internally
reset the processor, the processor’s bus output pins
will not enter the reset state if it has granted Hold
Acknowledge to a previous HOLD request (HOLDA is
active). Furthermore, the processor will grant new
HOLD requests and enter the Hold Acknowledge state
even while in reset.
For example, if HOLDA is inactive and the processor is
in the reset state, then HOLD is asserted, the proces-
sor’s bus pins enter the Hold Acknowledge state and
HOLDA is granted. The processor will not be able to
perform memory accesses until the HOLD request is
removed, even if the RESET pin is brought high. This
operation is provided to simplify boot-up synchroniza-
tion among multiple processors sharing the same bus.
35
80960CA-33, -25, -16
6.0 BUS WAVEFORMS
Figure 19. Cold Reset Waveform
36
80960CA-33, -25, -16
Figure 20. Warm Reset Waveform
37
80960CA-33, -25, -16
Figure 21. Entering the ONCE State
38
80960CA-33, -25, -16
1.5V
1.5V
1.5V
1.5V
CLKIN
T
T
IS
IH
RESET
1.5V
1.5V
PCLK2:1
(Case 1)
1.5V
1.5V
1.5V
Max
Min
Min
Max
Max
Min
T
CP
T
CP
T
CP
PCLK2:1
(Case 2)
1.5V
1.5V
1.5V
SYNC
Note: Case 1 and Case 2 show two possible polarities of PCLK2:1
F_CX024A
Figure 22. Clock Synchronization in the 2-x Clock Mode
2x CLK
CLKIN
1.5V
1.5V
T
T
IH
IS
RESET
1.5V
Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal
generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising
edge of CLKIN. The RESET pin is sampled when PCLK is high.
F_CX025A
Figure 23. Clock Synchronization in the 1-x Clock Mode
39
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Burst
0
Function
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
Bit
22
21
20-19
2
1
31-23
0
0..0
0
0
X
xx
0
X
x
X
xx
0
Disabled
0
X
xx
0
00
Disabled
0
OFF
0
Value
00000
00000
A
D
A
D
A
D
PCLK
ADS
A31:4, SUP,
DMA, D/C,
Valid
Valid
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
Valid
Valid
Valid
WAIT
D31:0
In
Out
In
F_CX026A
Figure 24. Non-Burst, Non-Pipelined Requests Without Wait States
40
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Burst
0
Function
Bit
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
X
xx
3
X
x
X
xx
X
xxxxx
Disabled
0
X
xx
1
01
Disabled
0
OFF
0
Value
00011
A
3
A
2
1
D
1
PCLK
ADS
A31:2, BE3:0
Valid
W/R
BLAST
DT/R
DEN
DMA, D/C,
SUP, LOCK
Valid
WAIT
D31:0
In
F_CX027A
Figure 25. Non-Burst, Non-Pipelined Read Request With Wait States
41
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Function
Bit
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
X
xx
X
X
x
X
xx
3
Disabled
0
X
xx
1
01
Disabled
0
OFF
0
Value
xxxxxx
00011
A
3
2
1
D
1
A
PCLK
ADS
A31:2,
BE3:0
Valid
W/R
BLAST
DT/R
DEN
SUP, DMA,
D/C, LOCK
Valid
WAIT
D31:0
Out
F_CX028A
Figure 26. Non-Burst, Non-Pipelined Write Request With Wait States
42
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Burst
0
Function
Bit
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
0
00
0
X
x
X
xx
X
xxxxx
Enabled
1
32-Bit
10
0
00
Disabled
0
OFF
0
Value
00000
A
D
D
D
D
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0
In1
In2
In3
In0
F_CX029A
Figure 27. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus
43
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Function
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
Bit
22
21
20-19
2
1
31-23
0
0..0
0
0
2
1
01
X
xx
X
xxxxx
Enabled
1
X
x
32-bit
10
1
01
Disabled
0
OFF
0
Value
00010
A
2
1
D
1
D
1
D
1
D
1
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
WAIT
00
01
10
11
In2
In3
In0
In1
D31:0
F_CX030A
Figure 28. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus
44
80960CA-33, -25, -16
External
Byte
Order
Pipe-
Lining
Bus
Width
Ready
Function
Bit
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
X
xxxxx
X
xx
0
00
0
Enabled
1
X
x
32-bit
10
0
00
Disabled
0
OFF
0
Value
00000
A
D
D
D
D
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0
Out0
Out1
Out2
Out3
F_CX031A
Figure 29. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus
45
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Function
Bit
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
X
xxxxx
X
xx
1
01
2
Enabled
1
X
x
32-bit
10
1
01
Disabled
0
OFF
0
Value
00010
A
2
1
D
1
D
1
D
1
D
1
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
WAIT
00
01
10
11
Out3
Out2
Out0
Out1
D31:0
F_CX032A
Figure 30. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus
46
80960CA-33, -25, -16
External
Pipe-
Lining
Byte
Order
Bus
Width
Ready
Burst
0
Function
Bit
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
1
01
2
X
xx
Enabled
1
X
x
X
xxxxx
16-bit
01
1
01
Disabled
0
OFF
0
Value
00010
A
2
1
D
1
D
1
D
1
D
1
A
PCLK
ADS
SUP, DMA,
D/C, LOCK,
A31:4, BE3/BHE,
BE0/BLE
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
WAIT
D31:0
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
F_CX033A
Figure 31. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus
47
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Function
Bit
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
1
01
2
X
x
X
xx
X
xxxxx
Enabled
1
8-bit
00
1
01
Disabled
0
OFF
0
Value
00010
A
2
1
D
1
D
1
D
1
D
1
A
PCLK
ADS
SUP, DMA,
D/C, LOCK,
A31:4
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00, 01, 10 or 11
BE1/A1,
BE0/A0
A1:0 = 00
A1:0 = 01
A1:0 = 10
A1:0 =11
WAIT
D31:0
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
D7:0
Byte 0
F_CX034A
Figure 32. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus
48
80960CA-33, -25, -16
External
Byte
Order
Pipe-
Lining
Bus
Width
Ready
Burst
0
Function
Bit
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0
0
X
xx
0
X
xx
Disabled
0
X
x
X
X
xx
X
xx
X
x
ON
1
Value
0..0
00000
xxxxx
A
A'
D
A''
D'
A'''
D''
A''''
D'''
D''''
PCLK
ADS
A31:4, SUP,
DMA, D/C,
LOCK
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
W/R
A3:2
BE3:0
Valid
Valid
Valid
Valid
Valid
Invalid
IN
IN
D
IN
D'
IN
D''
IN
D'''
D31:0
WAIT
D''''
BLAST
DT/R
DEN
Non-Pipelined Request Concludes
Pipelined Reads Begin.
Pipelined Reads Conclude,
Non-Pipelined Requests Begin.
F_CX035A
Figure 33. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
49
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Function
Bit
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
1
X
xx
X
xx
X
xxxxx
Disabled
1
X
x
X
xx
X
xx
X
x
ON
1
Value
00001
A
1
A'
D
1
D'
PCLK
ADS
A31:4, SUP,
DMA, D/C,
LOCK
Valid
Valid
Invalid
Invalid
Invalid
W/R
A3:2
BE3:0
Valid
Valid
IN
D
IN
D'
D31:0
WAIT
BLAST
DT/R
DEN
Non-Pipelined Request Concludes
Pipelined Reads Begin.
Pipelined Reads Conclude,
Non-Pipelined Requests Begin.
F_CX036A
Figure 34. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus
50
80960CA-33, -25, -16
External
Pipe-
Lining
Byte
Order
Bus
Width
Ready
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Function
Control
22
21
20-19
2
1
31-23
Bit
0
0..0
0
0
0
00
0
X
xx
Enabled
1
X
x
X
xxxxx
32-bit
10
X
xx
Disabled
0
ON
1
Value
00000
A
D
D
D
A'
D
D'
D'
PCLK
ADS
A31:4, SUP,
DMA, D/C,
In-
Valid
Valid
Valid
BE3:0, LOCK
In-
Valid
W/R
A3:2
In-
Valid
00
01
10
11
Valid Valid
IN
D
IN
D
IN
IN
IN
D
IN
D
D31:0
D
D
WAIT
BLAST
DT/R
DEN
Pipelined Reads
Conclude, Non-Pipelined
Requests Begin
Non-pipelined Request
Concludes, Pipelined
Reads Begin
F_CX037A
Figure 35. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
51
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Bus
Width
Function
Order
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
Bit
22
21
20-19
2
1
31-23
0
0..0
0
0
2
1
01
X
xx
X
xxxxx
Enabled
1
X
x
32-bit
10
X
xx
Disabled
0
ON
1
Value
00010
D'
A
2
1
D
1
D
1
D
1
A'
D
2
1
PCLK
ADS
A31:4, SUP,
In-
valid
DMA, D/C,
Valid
Valid
BE3:0, LOCK
In-
valid
W/R
A3:2
In-
valid
00
01
10
11
Valid
IN
D
IN
D
IN
D
IN
D'
IN
D
D31:0
WAIT
BLAST
DT/R
DEN
Pipelined reads conclude,
Non-pipelined requests begin.
Non-pipelined request concludes,
pipelined reads begin.
F_CX038A
Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus
52
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Order
Bus
Width
Function
Bit
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
22
21
20-19
2
1
31-23
0
0..0
0
0
1
01
2
X
xx
Enabled
1
X
x
X
xxxxx
16-bit
10
X
xx
Disabled
0
ON
1
Value
00010
D'
A
2
1
D
1
D
1
D
1
A'
D
2
1
PCLK
ADS
A31:4, SUP,
DMA, D/C,
In-
valid
Valid
Valid
BE0/BLE,
BE3/BHE,
LOCK
In-
valid
W/R
In-
valid
A3:2 = 00 or 10
A3:2 = 01 or 11
Valid
Valid
A3:2
In-
valid
BE1/A1
D15:0
A1=1
D15:0
A1=0
D15:0
A1=0
D15:0
D'
D15:0
A1=1
D31:0
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes,
pipelined reads begin.
Pipelined reads conclude,
Non-pipelined requests begin.
F_CX040A
Figure 37. Burst, Pipelined Read Request With Wait States, 16-Bit Bus
53
80960CA-33, -25, -16
External
Ready
Pipe-
Lining
Byte
Bus
Width
Function
Order
Burst
0
NWDD
18-17
NWAD
16-12
NXDA
11-10
NRDD
9-8
NRAD
7-3
Control
Bit
22
21
20-19
2
1
31-23
0
0..0
0
0
1
01
2
X
x
X
xx
X
xxxxx
Enabled
1
8-bit
10
X
xx
Disabled
0
ON
1
Value
00010
A
2
1
D
1
D
1
D
1
A'
D
2
1
D'
PCLK
ADS
A31:4, SUP,
In-
valid
Valid
Valid
DMA, D/C,
LOCK
In-
valid
W/R
A3:2
In-
valid
A3:2 = 00, 01, 10, or 11
Valid
BE1/A1,
BE0/A0
In-
valid
A1:0 = 00
A1:0 = 01
A1:0 = 10 A1:0 = 11
Valid
D7:0
D7:0
Byte 1
Byte 2
D7:0
D'
D7:0
Byte 0
D7:0
Byte 3
D31:0
WAIT
BLAST
DT/R
DEN
Pipelined reads conclude,
Non-pipelined requests begin.
Non-pipelined request concludes,
pipelined reads begin.
F_CX039A
Figure 38. Burst, Pipelined Read Request With Wait States, 8-Bit Bus
54
80960CA-33, -25, -16
Quad-Word Read Request
= 0, N = 0, N = 0
Quad-Word Write Request
N
N
= 1, N
= 0, N = 0
WAD
WDD
Ready Enabled
WDA
RAD
RDD
Ready Enabled
XDA
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0,
Valid
Valid
LOCK
W/R
BLAST
DT/R
DEN
READY
BTERM
A3:2
00
01 10
11
00
01
10
11
WAIT
D31:0
D0
D1 D2 D3
D0
D1
D2
D3
F_CX041A
Figure 39. Using External READY
55
80960CA-33, -25, -16
Quad-Word Write Request
= 0, N = 0, N = 0
N
WAD
WDD
Ready Enabled
WDA
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0,
LOCK
Valid
W/R
BLAST
DT/R
DEN
READY
BTERM
See Note
A3:2
00
01
10
11
WAIT
D31:0
D1
D2
D3
D0
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal will terminate a bus access if the signal is asserted during
the last (or only) data transfer of the bus access.
F_CX042A
Figure 40. Terminating a Burst with BTERM
56
80960CA-33, -25, -16
Regenerate ADS
ADS
BLAST
READY
BURST
BURST
NON-BURST
MAY CHANGE
RESUME REQUEST
BOFF
SUSPEND REQUEST
A31:2, SUP,
DMA, D/C,
BE3:0, WAIT,
DEN, DT/R
D31:0,
(WRITES)
Begin Request
End Request
BOFF May be asserted to suspend request
BOFF may not
be asserted
BOFF may not
be asserted
Note: READY/BTERM must be enabled; N
, N
RAD
, N = 0
, N
RDD WAD WDD
F_CX043A
Figure 41. BOFF Functional Timing
57
80960CA-33, -25, -16
Word Read
Request
Word Read Request
=1, N =1
N
=0,
=0
Hold State
Hold State
N
RAD
RAD
XDA
N
XDA
PCLK2:1
ADS
A31:2, SUP,
DMA, D/C,
Valid
Valid
BE3:0, WAIT,
DEN, DT/R
BLAST
HOLD
HOLDA
F_CX044A
Figure 42. HOLD Functional Timing
58
80960CA-33, -25, -16
System
Clock
PCLK2:1
ADS
Start DMA
Bus Request
End of DMA
Bus Request
! (BLAST
& READY
& !WAIT)
DMA
Acknowledge
(See Note)
DACKx
(All Modes)
High To Prevent
Next Bus Cycle
DREQx
(Case 1)
DMA
Request
t
t
High To Prevent
Next Bus Cycle
IS5
IH5
DREQx
(Case 2)
t
t
IS5
IH5
Note:
1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and
unpacking modes in which loads are followed by loads or stores are followed by stores.
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
Applications are non Fly-By transfers and adjacent load-stores or store-loads.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
accesses (defined by ADS and BLAST. Refer to i960 Cx Microprocessor User’s Manual for “access”,
“request” definitions.
F_CX018A
Figure 43. DREQ and DACK Functional Timing
PCLK2:1
EOP
2 CLKs Min
15 CLKs Max
Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
triggered. EOP must be
held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
F_CX045A
Figure 44. EOP Functional Timing
59
80960CA-33, -25, -16
PCLK2
DREQ
ADS
DACK
TC
Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the
last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active
®
for the entire bus request. Refer to the i960 Cx Microprocessor User’s Manual for
further information.
F_CX046A
Figure 45. Terminal Count Functional Timing
RESET
FAIL
(Bus Test)
Pass
(Internal Self-Test)
Pass
Fail
Fail
102 Cycles
~65,000 Cycles
5 Cycles
F_CX047A
Figure 46. FAIL Functional Timing
60
80960CA-33, -25, -16
0
0
4
1
8
2
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
Short Request (Aligned)
Byte, Byte Requests
Short-Word
Load/Store
Short Request (Aligned)
Byte, Byte Requests
Word Request (Aligned)
Byte, Short, Byte, Requests
Short, Short Requests
Word
Load/Store
Byte, Short, Byte Requests
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Requests
Short, Word, Short Requests
Double-Word
Load/Store
Byte, Word, Short, Byte Requests
Word, Word Requests
One Double-Word
Request (Aligned)
F_CX048A
Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
61
80960CA-33, -25, -16
0
4
1
8
2
12
3
16
4
20
5
24
6
Byte Offset
0
Word Offset
One Three-Word
Request (Aligned)
Byte, Short, Word,
Word, Byte Requests
Short, Word, Word,
Short Requests
Triple-Word
Load/Store
Byte, Word, Word,
Short, Byte Requests
Word, Word,
Word Requests
Word, Word,
Word Requests
Word,
Word,
Word
Requests
One Four-Word
Request (Aligned)
Byte, Short, Word, Word,
Word, Byte Requests
Short, Word, Word, Word,
Short Requests
Quad-Word
Load/Store
Byte, Word, Word, Word,
Short, Byte Requests
Word, Word, Word,
Word Requests
Double-
Word,
Double-
Word,
Requests
F_CX049A
Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
62
80960CA-33, -25, -16
Read Request
NWAD=2, NXDA = 0
Ready Disabled
Write Request
Idle Bus
(not in Hold Acknowledge state)
N
WAD=2, NXDA = 0
Ready Disabled
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0
Valid
Valid
Valid
Valid
LOCK
W/R
BLAST
DT/R
DEN
A3:2
Valid
Valid
WAIT
D31:0
Out
In
READY,
BTERM
F_CX050A
Figure 49. Idle Bus Operation
63
80960CA-33, -25, -16
7.0 REVISION HISTORY
This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a
result of design changes. The sections significantly changed since the previous revision are:
Last
Rev.
Section
Description
Table 11. 80960CA PGA Package Thermal
Characteristics
-005
Removed references and notes pertaining to
θJ-CAP and θJ-PIN.
Table 12. 80960CA PQFP package Thermal
Characteristics
-005
-005
Removed references and notes pertaining to θJL
and θJB.
3.3 80960CA Mechanical Data
Removed section containing information on
Package Dimensions. Moved section header to
encompass Pinout tables and diagrams.
3.7 Suggested Sources for 80960CA
Accessories
-005
-005
Removed entire section containing information
about 80960CA accessories.
Tables 16, 17 and18 80960CA AC Charac-
teristics (33-, 25- and 16MHz, respectively)
TTVEL maximum deleted.
TNHQX and TEHTV minimums changed:
WAS:
IS:
TNHQX
TEHTV
(N+1)*T-6
T/2 - 6
(N+1)*T-8
T/2 - 7
All
-005
All timing diagrams and waveforms have been
redrawn to conform to consistent format.
Data sheet formatting has been changed to
conform to corporate standards. Specific
formatting changes are not itemized in this revision
history.
64
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