80960CF-25 [INTEL]
SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR; 特殊环境80960CF - 30 ， -25 ， -16的32位高性能超标量处理器
| 型号： | 80960CF-25 |
| 厂家： | 
INTEL |
| 描述： | SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR |
| 文件： | 总62页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
PROCESSOR
Socket and Object Code Compatible with 80960CA
Two Instructions/Clock Sustained Execution
Four 59 Mbytes/s DMA Channels with Data Chaining
#
#
#
Demultiplexed 32-bit Burst Bus with Pipelining
#
32-bit Parallel Architecture
Ð Two Instructions/clock Execution
Ð Load/Store Architecture
Y
Y
High Bandwidth On-Chip Data RAM
Ð 1 Kbytes On-Chip RAM for Data
Ð Sustain 128 bits per clock access
Ð Sixteen 32-bit Global Registers
Ð Sixteen 32-bit Local Registers
Ð Manipulate 64-bit Bit Fields
Ð 11 Addressing Modes
Ð Full Parallel Fault Model
Ð Supervisor Protection Model
Y
Four On-Chip DMA Channels
Ð 59 Mbytes/s Fly-by Transfers
Ð 32 Mbytes/s Two-Cycle Transfers
Ð Data Chaining
Ð Data Packing/Unpacking
Ð Programmable Priority Method
Y
Y
Fast Procedure Call/Return Model
Ð Full Procedure Call in 4 clocks
Y
32-Bit Demultiplexed Burst Bus
Ð 128-bit Internal Data Paths to and
from Registers
On-Chip Register Cache
Ð Burst Bus for DRAM Interfacing
Ð Address Pipelining Option
Ð Fully Programmable Wait States
Ð Supports 8, 16 or 32-bit Bus Widths
Ð Supports Unaligned Accesses
Ð Supervisor Protection Pin
Ð Caches Registers on Call/Ret
Ð Minimum of 6 Frames provided
Ð Up to 15 Programmable Frames
Y
Y
Y
On-Chip Instruction Cache
Ð 4 Kbyte Two-Way Set Associative
Ð 128-bit Path to Instruction Sequencer
Ð Cache-Lock Modes
Y
Y
Selectable Big or Little Endian Byte
Ordering
Ð Cache-Off Mode
High-Speed Interrupt Controller
Ð Up to 248 External Interrupts
Ð 32 Fully Programmable Priorities
Ð Multi-mode 8-bit Interrupt Port
Ð Four Internal DMA Interrupts
Ð Separate, Non-maskable Interrupt Pin
Ð Context Switch in 750 ns Typical
On-Chip Data Cache
Ð 1 Kbyte Direct-Mapped,
Write Through
Ð 128 bits per Clock Access on
Cache Hit
Product Grades Available
b
a
Ð SE3: 40 C to 110 C
§
§
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
January 1995
Order Number: 271328-001
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–1
Figure 1. 80960CF Die Photo
2
Special Environment 80960CF-30, -25, -16
32-Bit High Performance Superscalar Processor
CONTENTS
PAGE
CONTENTS
PAGE
1.0 PURPOSE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
FIGURES
Figure 1
Figure 2
Figure 3
80960CF Die Photo ÀÀÀÀÀÀÀÀÀÀÀÀ 2
80960CF Block Diagram ÀÀÀÀÀÀÀ 5
2.0 i960 CF PROCESSOR
OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Example Pin Description
Entry ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.1 The C-Series Core ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.2 Pipelined, Burst Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.3 Flexible DMA Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
2.4 Priority Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀ 6
2.5 Instruction Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Figure 4a 80960CF PGA Pinout (View
from Top Side) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
Figure 4b 80960CF PGA Pinout (View
from Bottom Side) ÀÀÀÀÀÀÀÀÀÀÀÀ 17
Figure 5
Figure 6
Figure 7
168-Lead Ceramic PGA
Package Dimensions ÀÀÀÀÀÀÀÀÀ 18
3.0 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.1 Package Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.2 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
3.3 80960CF Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.4 Mechanical Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
3.5 Package Thermal Specifications ÀÀÀÀ 20
3.6 Stepping Register Information ÀÀÀÀÀÀ 21
80960CF PGA Package
Thermal Characteristics ÀÀÀÀÀÀÀ 20
Measuring 80960CF PGA
Case Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ 21
Figure 8
Figure 9
Register G0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
AC Test Load ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
Figure 10a Input and Output Clocks
Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
3.7 Suggested Sources for 80960CF
Accessories ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
Figure 10b CLKIN Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
4.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀ 22
4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 22
4.2 Operating Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
4.3 Recommended Connections ÀÀÀÀÀÀÀÀ 22
4.4 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
4.5 AC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
Figure 11 Output Delay and Float
Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
Figure 12a Input Setup and Hold
Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
Figure 12b NMI, XINT7:0 Input Setup
and Hold Waveform ÀÀÀÀÀÀÀÀÀÀ 31
Figure 13 Hold Acknowledge
Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
5.0 RESET, BACKOFF AND HOLD
ACKNOWLEDGE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
Figure 14 Bus Back-Off (BOFF)
Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
6.0 BUS WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
3
CONTENTS
Figure 15 Relative Timings
PAGE
CONTENTS
Figure 31 Burst, Non-Pipelined Read
Request with Wait States,
PAGE
Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
8-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
Figure 16 Output Delay or Hold vs Load
Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
Figure 32 Non-Burst, Pipelined Read
Request without Wait States,
Figure 17 Rise and Fall Time Derating at
Highest Operating
Temperature and Minimum
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49
Figure 33 Non-Burst, Pipelined Read
Request with Wait States,
V
CC
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50
Figure 18
I
vs Frequency and
CC
Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
Figure 34 Burst, Pipelined Read
Request without Wait States,
Figure 19 Cold Reset Waveform ÀÀÀÀÀÀÀÀÀ 36
Figure 20 Warm Reset Waveform ÀÀÀÀÀÀÀÀ 37
Figure 21 Entering the ONCE State ÀÀÀÀÀÀ 38
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
Figure 35 Burst, Pipelined Read
Requests with Wait States,
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52
Figure 22a Clock Synchronization in the
2x Clock Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
Figure 36 Burst, Pipelined Read
Requests with Wait States,
Figure 22b Clock Synchronization in the
1x Clock Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
16-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53
Figure 37 Burst, Pipelined Read
Requests with Wait States,
Figure 23 Non-Burst, Non-Pipelined
Requests without Wait
8-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54
States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
Figure 38 Using External READY ÀÀÀÀÀÀÀÀ 55
Figure 24 Non-Burst, Non-Pipelined
Read Request with Wait
Figure 39 Terminating a Burst with
BTERM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56
States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
Figure 25 Non-Burst, Non-Pipelined
Write Request with Wait
Figure 40 BOFF Functional Timing ÀÀÀÀÀÀ 57
Figure 41 HOLD Functional Timing ÀÀÀÀÀÀ 57
States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
Figure 42 DREQ and DACK Functional
Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58
Figure 26 Burst, Non-Pipelined Read
Request without Wait States,
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43
Figure 43 EOP Functional Timing ÀÀÀÀÀÀÀ 58
Figure 27 Burst, Non-Pipelined Read
Request with Wait States,
Figure 44 Terminal Count Functional
Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
Figure 45 FAIL Functional Timing ÀÀÀÀÀÀÀ 59
Figure 28 Burst, Non-Pipelined Write
Request without Wait States,
Figure 46 A Summary of Aligned and
Unaligned Transfers for Little
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
Endian Regions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60
Figure 29 Burst, Non-Pipelined Write
Request with Wait States,
Figure 47 A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46
Figure 30 Burst, Non-Pipelined Read
Request with Wait States,
(Continued) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61
Figure 48 Idle Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀ 62
16-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47
4
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
tions every clock, and peak at execution of three
instructions per clock.
1.0 PURPOSE
This document previews electrical characterizations
of Intel’s i960 CF embedded microprocessor (avail-
able in 33, 25 and 16 MHz). For a detailed descrip-
tion of any i960 CF processor functional topicÐoth-
er than parametric performanceÐrefer to the latest
i960 CA Microprocessor Reference Manual (Order
No. 270710) and the i960 CF Reference Manual Ad-
dendum (Order No. 272188).
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte/s bandwidth to a system’s high-
speed external memory sub-system. In addition, the
80960CF’s on-chip caching of instructions, proce-
dure context and critical program data substantially
decouples system performance from the wait states
associated with accesses to the system’s slower,
cost sensitive, main memory sub-system.
The 80960CF bus controller also integrates full wait
state and bus width control for highest system per-
formance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF.
2.0 i960 CF PROCESSOR OVERVIEW
Intel’s i960 CF microprocessor is the performance
follow-on product to the i960 CA processor. The
i960 CF product is socket- and object code-compati-
ble with the CA; this makes CA-to-CF design up-
grades straightforward. The i960 CF processor’s in-
struction cache is 4 Kbytes (CA device has 1 Kbyte);
CF data cache is 1 Kbyte (CA device has no data
cache). This extra cache on the CF product adds a
significant performance boost over the CA. The
80960CF is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals, and instruction set extensions to shift 64-
bit operands and configure on-chip hardware. Multi-
ple 128-bit internal busses, on-chip instruction cach-
ing and a sophisticated instruction scheduler allow
the processor to sustain execution of two instruc-
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. The DMA channels perform: sin-
gle-cycle or two-cycle transfers, data packing and
unpacking, and data chaining. Block transfers, in ad-
dition to source or destination synchronized trans-
fers, are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns.
271328–2
Figure 2. 80960CF Block Diagram
5
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
2.1. The C-Series Core
Ð Demultiplexed, Burst Bus to exploit most efficient
DRAM access modes.
The C-Series core is a very high performance micro-
architectural implementation of the 80960 Core Ar-
chitecture. The C-Series core can sustain execution
of two instructions per clock (66 MIPs at 33 MHz).
To achieve this level of performance, Intel has incor-
porated state-of-the-art silicon technology and inno-
vative microarchitectural constructs into the imple-
mentation of the C-Series core. Factors that contrib-
ute to the core’s performance include:
Ð Address Pipelining to reduce memory cost while
maintaining performance.
Ð 32-, 16- and 8-bit modes for I/O interfacing ease.
Ð Full internal wait state generation to reduce sys-
tem cost.
Ð Little and Big Endian support to ease application
development.
Ð Unaligned access support for code portability.
Ð Parallel instruction decoding allows issue of up
to three instructions per clock.
Ð Three-deep request queue to decouple the bus
from the core.
Ð Most instructions execute in a single clock.
Ð Parallel instruction decode allows sustained,
simultaneous execution of two single-clock in-
structions every clock cycle.
2.3. Flexible DMA Controller
A four channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disassem-
bly, and a high performance fly-by mode capable of
transfer speed of up to 59 Mbytes per second at
33 MHz. The DMA controller features a performance
and flexibility which is only possible by integrating
the DMA controller and the 80960CF core.
Ð Efficient instruction pipeline minimizes pipeline
break losses.
Ð Register and resource scoreboarding allow
simultaneous multi-clock instruction execution.
Ð Branch look-ahead and prediction allows many
branches to execute with no pipeline break.
Ð Local Register Cache integrated on-chip caches
Call/Return context.
Ð Two-way set associative, 4 Kbyte integrated in-
struction cache.
2.4. Priority Interrupt Controller
Ð Direct mapped,
through, write allocate.
1 Kbyte data cache, write
A programmable-priority interrupt controller man-
ages up to 248 external sources through the 8-bit
external interrupt port. The Interrupt Unit also han-
dles the four internal sources from the DMA control-
ler, and a single non-maskable interrupt input. The
8-bit interrupt port can also be configured to provide
individual interrupt sources that are level or edge
triggered.
Ð 1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle.
2.2. Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CF to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 132 Mbytes per second (at 33 MHz). Internal-
ly programmable wait states and 16 separately con-
figurable memory regions allow the processor to in-
terface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus Controller’s main features in-
clude:
Interrupts in the 80960CF are prioritized and sig-
naled within 270 ns of the request. If the interrupt is
of higher priority than the processor priority, the con-
text switch to the interrupt routine typically is com-
plete in another 480 ns. The interrupt unit provides
the mechanism for the low latency and high through-
put interrupt service which is essential for embedded
applications.
6
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
2.5. Instruction Set Summary
The following table summarizes the 80960CF instruction set by logical groupings. See the i960 CA Microproc-
essor Reference Manual for a complete description of the instruction set.
Data
Arithmetic
Logical
Bit, Bit Field
and Byte
Movement
Load
Store
Add
And
Set Bit
Clear Bit
Subtract
Multiply
Divide
Not And
And Not
Or
Move
Load Address
Not Bit
Alter Bit
Remainder
Modulo
Shift
Exclusive Or
Not Or
Or Not
Nor
Scan for Bit
Span over Bit
Extract
*Extended
Shift
Modify
Scan Byte for Equal
Exclusive Nor
Not
Nand
Extended
Multiply
Extended
Divide
Add with
Carry
Subtract with
Carry
Rotate
Comparison
Branch
Call and Return
Fault
Compare
Conditional
Compare
Unconditional
Branch
Call
Conditional
Fault
Call Extended
Call System
Return
Conditional
Branch
Synchronize
Faults
Compare and
Increment
Compare and
Branch
Branch and Link
Compare and
Decrement
Test Condition Code
Check Bit
Debug
Processor
Atomic
Management
Modify Trace
Controls
Mark
Modify
Atomic Add
Atomic Modify
Process
Controls
Force Mark
Modify
Arithmetic
Controls
*System Control
*DMA Control
Flush Local
Registers
NOTE:
Instructions marked by (*) are 80960CF extensions to the 80960 instruction set.
7
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 1. Pin Description Nomenclature
Symbol Description
3.0 PACKAGE INFORMATION
3.1. Package Introduction
I
O
Input only pin
Output only pin
This section describes the pins, pinouts and thermal
characteristics for the 80960CF in the 168-pin Ce-
ramic Pin Grid Array (PGA) package. For complete
package specifications and information, see the Intel
Packaging Outlines and Dimensions Guide (Order
No. 231369).
I/O
-
Pin can be either an input or output
Pins ‘‘must be’’ connected as
described
S( . . . ) Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
3.2. Pin Descriptions
S(E) Edge sensitive input
S(L) Level sensitive input
The 80960CF pins are described in this section. Ta-
ble 1 presents the legend for interpreting the pin de-
scriptions in the following tables.
A( . . . ) Asynchronous. Inputs may be
asynchronous to PCLK2:1.
A(E) Edge sensitive input
Pins associated with the 32-bit demultiplexed proc-
essor bus are described in Table 2. Pins associated
with basic processor configuration and control are
described in Table 3. Pins associated with the
80960CF DMA Controller and Interrupt Unit are de-
scribed in Table 4.
A(L) Level sensitive input
H( . . . ) While the processor’s bus is in the
Hold Acknowledge or Bus Backoff
state, the pin:
H(1) is driven to V
H(0) is driven to V
H(Z) floats
CC
SS
Figure 3 provides an example pin description table
entry. ‘‘I/O’’ signifies that data pins are input-output.
‘‘S’’ indicates pins are synchronous to PCLK2:1.
‘‘H(Z)’’ indicates that these pins float while the proc-
essor bus is in a Hold Acknowledge state. ‘‘R(Z)’’
indicates that the pins also float while RESET is low.
H(Q) continues to be a valid output
R( . . . ) While the processor’s RESET pin is
low, the pin
R(1) is driven to V
R(0) is driven to V
R(Z) floats
CC
All pins float while the processor is in the ONCE
mode.
SS
R(Q) continues to be a valid output
Name Type
Description
D31:0
I/O DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration.
The least significant bit of the data is carried on D0 and the most significant on D31. When
the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit bus
widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
S(L)
H(Z)
R(Z)
Figure 3. Example Pin Description Entry
8
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals
Name
A31:2
Type
Description
O
S
ADDRESS BUS carries the physical address upper 30 bits. A31 is the most
significant address bit and A2 is the least significant. During a bus access, A31:2
identify all external addresses to word (4-byte) boundaries. The byte enable
signals indicate the selected byte in each word. During burst accesses, A3 and A2
increment to indicate successive data cycles.
H(Z)
R(Z)
D31:0
I / O
S(L)
H(Z)
R(Z)
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
significant on D31. When the bus is configured for 8-bit data, the lower 8 data
lines, D7:0 are used. For 16-bit bus widths, D15:0 are used. For 32-bit bus widths
the full data bus is used.
BE3
BE2
BE1
BE0
O
S
BYTE ENABLES select which of the four bytes addressed by A31:2 are active
during an access to a memory region configured for a 32-bit data-bus width. BE3
applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8; and BE0 applies
to D7:0.
H(Z)
R(1)
32-bit bus:
BE3
BE2
BE1
BE0
–Byte Enable 3
–Byte Enable 2
–Byte Enable 1
–Byte Enable 0
–enable D31:24
–enable D23:16
–enable D15:8
–enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the
processor directly encodes BE3, BE1 and BE0 to provided BHE, A1 and BLE
respectively.
16-bit bus:
BE3
BE2
BE1
BE0
–Byte High Enable (BHE)
–enable D15:8
–Not used (is driven high or low)
–Address Bit 1 (A1)
–Byte Low Enable (BLE)
–enable D7:0
For accesses to a memory region configured for an 8-bit data bus width, the
processor directly encodes BE1 and BE0 to provide A1 and A0 respectively.
8-bit bus:
BE3
BE2
BE1
BE0
–Not used (is driven high or low)
–Not used (is driven high or low)
–Address Bit 1 (A1)
–Address Bit 0 (A0)
W/R
O
S
WRITE/READ is asserted for read requests and deasserted for write requests.
The W/R signal changes in the same clock cycle as ADS. It remains valid for the
entire access in non-pipelined regions. In pipelined regions, W/R is not
guaranteed valid in the last cycle of a read access.
H(Z)
R(0)
ADS
O
S
ADDRESS STROBE indicates valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
H(Z)
R(1)
READY
I
READY is an input which signals the termination of a data transfer. READY is
used to indicate that read data on the bus is valid, or that a write-data transfer has
completed. The READY signal works in conjunction with the internally
programmed wait-state generator. If READY is enabled in a region, the pin is
sampled after the programmed number of wait-states has expired. If the READY
pin is deasserted, wait states continue to be inserted until READY becomes
S(L)
H(Z)
R(Z)
asserted. This is true for the N
N
, N
, N
RAD RDD WAD
, and N
wait states. The
WDD
wait states cannot be extended.
XDA
9
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)
Name
Type
Description
BTERM
I
BURST TERMINATEÐThe burst terminate signal breaks up a burst access and
causes another address cycle to occur. The BTERM signal works in conjunction
with the internally programmed wait-state generator. If READY and BTERM are
enabled in a region, the BTERM pin is sampled after the programmed number of
wait states has expired. When BTERM is asserted, a new ADS signal is generated
and the access is completed. The READY input is ignored when BTERM is
asserted. BTERM must be externally synchronized to satisfy the BTERM setup
and hold times.
S(L)
H(Z)
R(Z)
WAIT
O
S
H(Z)
R(1)
WAIT indicates internal wait state generator status. WAIT is asserted when wait
states are being caused by the internal wait state generator and not by the
READY or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT
can also be thought of as a READY output that the processor provides when it is
inserting wait states.
BLAST
O
S
H(Z)
R(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the wait state counter
reaches zero. BLAST remains asserted until the clock following the last cycle of
the last data transfer of a bus access. If the READY or BTERM input is used to
extend wait states, the BLAST signal remains asserted until READY or BTERM
terminates the access.
DT/R
DEN
O
S
H(Z)
R(0)
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is
used in conjunction with DEN to provide control for data transceivers attached to
the external bus. When DT/R is asserted, the signal indicates that the processor
receives data. Conversely, when deasserted, the processor sends data. DT/R
changes only while DEN is high.
O
S
H(Z)
R(1)
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the
start of the bus request first data cycle and is deasserted at the end of the last
data cycle. DEN is used in conjunction with DT/R to provide control for data
transceivers attached to the external bus. DEN remains asserted for sequential
reads from pipelined memory regions. DEN is deasserted when DT/R changes.
LOCK
O
S
H(Z)
R(1)
BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK may be used to prevent external agents from accessing memory which is
currently involved in an atomic operation. LOCK is asserted in the first clock of an
atomic operation, and deasserted in the clock cycle following the last bus access
for the atomic operation. To allow the most flexibility for a memory system
enforcement of locked accesses, the processor acknowledges a bus hold request
when LOCK is asserted. The processor performs DMA transfers while LOCK is
active.
HOLD
BOFF
I
HOLD REQUEST signals that an external agent requests access to the external
bus. The processor asserts HOLDA after completing the current bus request.
HOLD, HOLDA and BREQ are used together to arbitrate access to the
processor’s external bus by external bus agents.
S(L)
H(Z)
R(Z)
I
BUS BACKOFF ÐThe backoff pin, when asserted, suspends the current access
and causes the bus pins to float. When deasserted, the ADS signal is asserted on
the next clock cycle and the access is resumed.
S(L)
H(Z)
R(Z)
10
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)
Name
Type
Description
HOLDA
O
S
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus. When HOLDA is asserted, the external
address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA
and BREQ are used together to arbitrate access to the processor’s external bus
by external bus agents. Since the processor grants HOLD requests and enters the
Hold Acknowledge state even while RESET is asserted, HOLDA pin state is
independent of the RESET pin.
H(1)
R(Q)
BREQ
D/C
O
S
BUS REQUEST is asserted when the bus controller has a request pending. BREQ
can be used by external bus arbitration logic in conjunction with HOLD and
HOLDA to determine when to return mastership of the external bus to the
processor.
H(Q)
R(0)
O
S
DATA OR CODE is asserted for a data request and deasserted for instruction
requests. D/C has the same timing as W/R.
H(Z)
R(Z)
DMA
SUP
O
S
DMA ACCESS indicates whether the bus request was initiated by the DMA
controller. DMA is asserted for any DMA request. DMA is deasserted for all other
requests.
H(Z)
R(Z)
O
S
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode. SUP is asserted when the request has supervisor privileges, and
is deasserted otherwise. SUP can be used to isolate supervisor code and data
structures from non-supervisor requests.
H(Z)
R(Z)
Table 3. 80960CF Pin DescriptionÐProcessor Control Signals
Description
Name
Type
RESET
I
RESET causes the chip to reset. When RESET is asserted, all external signals return
to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock
mode is selected, RESET must remain asserted for 16 PCLK2:1 cycles before being
deasserted in order to guarantee correct processor initialization. When the 1-x clock
mode is selected, RESET must remain asserted for 10,000 PCLK2:1 cycles before
being deasserted in order to guarantee correct initialization. The CLKMODE pin
selects 1-x or 2-x input clock division of the CLKIN pin.
A(L)
H(Z)
R(Z)
N(Z)
The processor’s Hold Acknowledge bus state functions while the chip is reset. If the
processor’s bus is in the Hold Acknowledge state when RESET is asserted, the
processor will internally reset, but maintains the Hold Acknowledge state on external
pins until the Hold request is removed. If a hold request is made while the processor is
in the reset state, the processor bus grants HOLDA and enters the Hold Acknowledge
state.
FAIL
O
S
FAIL indicates failure of the processor’s self-test performed at initialization. When
RESET is deasserted and the processor begins initialization, the FAIL pin is asserted.
An internal self-test is performed as part of the initialization process. If this self-test
passes, the FAIL pin is deasserted otherwise it remains asserted. The FAIL pin is
reasserted while the processor performs an external bus self-confidence test. If this
self-test passes, the processor deasserts the FAIL pin and branches to the user’s
initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the
use of the FAIL pin can be disabled with the STEST pin.
H(Q)
R(0)
11
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 3. 80960CF Pin DescriptionÐProcessor Control Signals (Continued)
Name
STEST
Type
Description
I
SELF TEST causes the processor’s internal self-test feature to be enabled or
disabled at initialization. STEST is read on the rising edge of RESET. When asserted,
the processor’s internal self-test and external bus confidence tests are performed
during processor initialization. When deasserted, only the external bus confidence
tests are performed during initialization.
S(L)
H(Z)
R(Z)
ONCE
I
ON CIRCUIT EMULATION causes all outputs to be floated when asserted. ONCE is
continuously sampled while RESET is low, and is latched on the rising edge of
RESET. To place the processor in the ONCE state:
A(L)
H(Z)
R(Z)
(1) assert RESET and ONCE (order does not matter)
(2) wait for at least 16 CLKIN periods in 2-x mode, or 10,000 CLKIN periods in 1-x
mode, after V and CLKIN are within operating specifications
CC
(3) deassert RESET
(4) wait at least 32 CLKIN periods
(The processor is now latched in the ONCE state as long as RESET is high.)
To exit the ONCE state, bring V and CLKIN to operating conditions, then assert
CC
RESET and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions of the processor until
step 4 above is completed. The CLKIN may then be changed to DC to achieve the
lowest possible ONCE mode leakage current.
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board.
CLKIN
I
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
A(E)
H(Z)
R(Z)
CLKMODE
I
CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
a system, as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
A(L)
H(Z)
R(Z)
PCLK2
PCLK1
O
S
PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and
outputs of the processor. All inputs and output timings are specified in relation to
PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are
provided to allow flexibility in the system’s allocation of capacitive loading on the
clock. PCLK2:1 may also be connected at the processor to form a single clock signal.
H(Q)
R(Q)
V
V
V
Ð
Ð
Ð
GROUND connections consist of 24 pins which must be connected externally to a
board plane.
SS
V
SS
POWER connections consist of 24 pins which must be connected externally to a V
board plane.
CC
CC
V
CCPLL
Connecting a simple low pass filter to V
is a separate V supply pin for the phase lock loop used in 1x clock mode.
CC
CCPLL
may help reduce clock jitter (T ) in
CP
CCPLL
should be connected to V
noisy environments. Otherwise, V
.
CC
CCPLL
N/C
Ð
NO CONNECT pins must not be connected in a system.
12
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 4. 80960CF Pin DescriptionÐDMA and Interrupt Unit Control Signals
Name
Type
Description
DREQ3
DREQ2
DREQ1
DREQ0
I
DMA REQUEST causes a DMA transfer to be requested. Each of the four signals
request a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests
channel 1, etc. When two or more channels are requested simultaneously, the
channel with the highest priority is serviced first. Channel priority mode is
programmable.
A(L)
H(Z)
R(Z)
DACK3
DACK2
DACK1
DACK0
O
S
DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the
four signals acknowledge a transfer for a single channel. DACK0 acknowledges
channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the
requesting device of a DMA is accessed.
H(1)
R(1)
EOP3/TC3
EOP2/TC2
I / O
END OF PROCESS/TERMINAL COUNT can be programmed as either an input
(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually
programmable. When programmed as an input, EOPx causes the termination of a
current DMA transfer for the channel corresponding to the EOPx pin. EOP0
corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is
configured for sourceand destination chaining, the EOP pin for that channel causes
termination of only the current buffer transferred and causes the next buffer to be
transferred. EOP3:0 are asynchronous inputs.
A(L)
EOP1/TC1 H(Z/Q)
EOP0/TC0
R(Z)
When programmed as an output, the channel’s TCx pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx is driven with the same
timing as DACKx during the last DMA transfer for a buffer. If the last bus request is
executed as multiple bus accesses, TCx remains asserted for the entire bus request.
XINT7
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
I
EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be
configured in three modes.
A(E/L)
H(Z)
R(Z)
In Dedicated Mode, each pin is a dedicated external interrupt source. Dedicated
inputs can be individually programmed to be level (low) or edge (falling) activated.
In Expanded Mode, the 8 pins act together as an 8-bit vectored interrupt source. The
interrupt pins in this mode are level activated. Since the interrupt pins are active low,
the vector number requested is the one’s complement of the positive logic value
place on the port. This eliminates glue logic to interface to combinational priority
encoders which output negative logic.
In Mixed Mode, XINT7:5 are dedicated sources and XINT4:0 act as the 5 most
significant bits of an expanded mode vector. The least significant bits are set to 010
internally.
NMI
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated
source.
A(E)
H(Z)
R(Z)
13
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
80960CF pinout as viewed from the top side of the
component (i.e., pins facing down). Figure 4b shows
the complete 80960CF pinout as viewed from the
pin-side of the package (i.e., pins facing up). See
Section 4.0, Electrical Specifications for specifica-
tions and recommended connections.
3.3. 80960CF Pinout
3.3.1 80960CF PGA PINOUT
Tables 5 and 6 list the 80960CF pin names with
package location. Figure 4-a depicts the complete
Table 5. PGA Pin Name with Package Location (Signal Order)
Address Bus
Data Bus
Bus Control
Processor Control
Name ÀÀÀÀLocation
RESET ÀÀÀÀÀÀÀA16
I/O
Name ÀÀLocation
A31 ÀÀÀÀÀÀÀÀS15
A30 ÀÀÀÀÀÀÀÀQ13
A29 ÀÀÀÀÀÀÀÀR14
A28 ÀÀÀÀÀÀÀÀQ14
A27 ÀÀÀÀÀÀÀÀS16
A26 ÀÀÀÀÀÀÀÀR15
A25 ÀÀÀÀÀÀÀÀS17
A24 ÀÀÀÀÀÀÀÀQ15
A23 ÀÀÀÀÀÀÀÀR16
A22 ÀÀÀÀÀÀÀÀR17
A21 ÀÀÀÀÀÀÀÀQ16
A20 ÀÀÀÀÀÀÀÀP15
A19 ÀÀÀÀÀÀÀÀP16
A18 ÀÀÀÀÀÀÀÀQ17
A17 ÀÀÀÀÀÀÀÀP17
A16 ÀÀÀÀÀÀÀÀN16
A15 ÀÀÀÀÀÀÀÀN17
A14ÀÀÀÀÀÀÀÀM17
A13 ÀÀÀÀÀÀÀÀL16
A12 ÀÀÀÀÀÀÀÀL17
A11 ÀÀÀÀÀÀÀÀK17
A10 ÀÀÀÀÀÀÀÀJ17
A9 ÀÀÀÀÀÀÀÀÀH17
A8 ÀÀÀÀÀÀÀÀÀG17
A7 ÀÀÀÀÀÀÀÀÀG16
A6 ÀÀÀÀÀÀÀÀÀF17
A5 ÀÀÀÀÀÀÀÀÀE17
A4 ÀÀÀÀÀÀÀÀÀE16
Name ÀÀLocation
D31 ÀÀÀÀÀÀÀÀR03
D30ÀÀÀÀÀÀÀÀQ05
D29 ÀÀÀÀÀÀÀÀS02
D28ÀÀÀÀÀÀÀÀQ04
D27 ÀÀÀÀÀÀÀÀR02
D26ÀÀÀÀÀÀÀÀQ03
D25 ÀÀÀÀÀÀÀÀS01
D24 ÀÀÀÀÀÀÀÀR01
D23ÀÀÀÀÀÀÀÀQ02
D22 ÀÀÀÀÀÀÀÀP03
D21ÀÀÀÀÀÀÀÀQ01
D20 ÀÀÀÀÀÀÀÀP02
D19 ÀÀÀÀÀÀÀÀP01
D18 ÀÀÀÀÀÀÀÀN02
D17 ÀÀÀÀÀÀÀÀN01
D16ÀÀÀÀÀÀÀÀM01
D15 ÀÀÀÀÀÀÀÀL01
D14 ÀÀÀÀÀÀÀÀL02
D13 ÀÀÀÀÀÀÀÀK01
D12 ÀÀÀÀÀÀÀÀJ01
D11 ÀÀÀÀÀÀÀÀH01
D10 ÀÀÀÀÀÀÀÀH02
D9 ÀÀÀÀÀÀÀÀÀG01
D8 ÀÀÀÀÀÀÀÀÀF01
D7 ÀÀÀÀÀÀÀÀÀE01
D6 ÀÀÀÀÀÀÀÀÀF02
D5 ÀÀÀÀÀÀÀÀÀD01
D4 ÀÀÀÀÀÀÀÀÀE02
Name ÀÀLocation
BE3 ÀÀÀÀÀÀÀÀS05
BE2 ÀÀÀÀÀÀÀÀS06
BE1 ÀÀÀÀÀÀÀÀS07
BE0ÀÀÀÀÀÀÀÀR09
Name ÀÀLocation
DREQ3 ÀÀÀÀÀA07
DREQ2 ÀÀÀÀÀB06
DREQ1 ÀÀÀÀÀA06
DREQ0 ÀÀÀÀÀB05
FAILÀÀÀÀÀÀÀÀÀÀA02
STESTÀÀÀÀÀÀÀÀB02
ONCE ÀÀÀÀÀÀÀÀC03
W/R ÀÀÀÀÀÀÀS10
ADS ÀÀÀÀÀÀÀR06
DACK3 ÀÀÀÀÀA10
DACK2 ÀÀÀÀÀA09
DACK1 ÀÀÀÀÀA08
DACK0 ÀÀÀÀÀB08
CKLIN ÀÀÀÀÀÀÀÀC13
CLKMODE ÀÀÀÀC14
PCLK1ÀÀÀÀÀÀÀÀB14
PCLK2ÀÀÀÀÀÀÀÀB13
READY ÀÀÀÀÀS03
BTERMÀÀÀÀÀR04
EOP/TC0 ÀÀÀA11
EOP/TC1 ÀÀÀA12
EOP/TC2 ÀÀÀA13
EOP/TC3 ÀÀÀA14
WAITÀÀÀÀÀÀÀS12
BLAST ÀÀÀÀÀS08
V
SS
Location
DT/RÀÀÀÀÀÀÀS11
DEN ÀÀÀÀÀÀÀS09
C07, C08, C09,
C10, C11, C12,
F15, G03, G15,
H03, H15, J03,
J15, K03, K15,
L03, L15, M03,
M15, Q07, Q08,
Q09, Q10, Q11
XINT7 ÀÀÀÀÀÀC17
XINT6 ÀÀÀÀÀÀC16
XINT5 ÀÀÀÀÀÀB17
XINT4 ÀÀÀÀÀÀC15
XINT3 ÀÀÀÀÀÀB16
XINT2 ÀÀÀÀÀÀA17
XINT1 ÀÀÀÀÀÀA15
XINT0 ÀÀÀÀÀÀB15
LOCK ÀÀÀÀÀÀS14
HOLD ÀÀÀÀÀÀR05
HOLDA ÀÀÀÀÀS04
BREQ ÀÀÀÀÀÀR13
V
CC
Location
B07, B09,
B11, B12, C06,
E15, F03, F16,
G02, H16, J02,
J16, K02, K16, M02,
M16, N03, N15,
Q06, R07, R08,
R10, R11
D/C ÀÀÀÀÀÀÀÀS13
DMA ÀÀÀÀÀÀÀR12
SUP ÀÀÀÀÀÀÀQ12
NMI ÀÀÀÀÀÀÀÀD15
V
ÀÀÀÀÀÀÀB10
CCPLL
A3 ÀÀÀÀÀÀÀÀÀD17
A2 ÀÀÀÀÀÀÀÀÀD16
D3 ÀÀÀÀÀÀÀÀÀC01
D2 ÀÀÀÀÀÀÀÀÀD02
D1 ÀÀÀÀÀÀÀÀÀC02
BOFF ÀÀÀÀÀÀB01
No Connect
Location
A01, A03, A04, A05,
B03, B04, C04, C05,
D03
D0 ÀÀÀÀÀÀÀÀÀE03
14
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 6. PGA Pin Name with Package Location (Pin Order)
Address Bus
Data Bus
Bus Control
Location ÀÀName
G01 ÀÀÀÀÀÀÀÀÀD9
Processor Control
Location ÀÀÀÀName
M01 ÀÀÀÀÀÀÀÀÀD16
I/O
Location ÀÀName
A01ÀÀÀÀÀÀÀÀÀNC
A02 ÀÀÀÀÀÀÀFAIL
A03ÀÀÀÀÀÀÀÀÀNC
A04ÀÀÀÀÀÀÀÀÀNC
A05ÀÀÀÀÀÀÀÀÀNC
A06 ÀÀÀÀÀDREQ1
A07 ÀÀÀÀÀDREQ3
A08 ÀÀÀÀÀDACK1
A09 ÀÀÀÀÀDACK2
A10 ÀÀÀÀÀDACK3
A11 ÀÀÀEOP/TC0
A12 ÀÀÀEOP/TC1
A13 ÀÀÀEOP/TC2
A14 ÀÀÀEOP/TC3
A15 ÀÀÀÀÀÀXINT1
A16 ÀÀÀÀÀRESET
A17 ÀÀÀÀÀÀXINT2
Location ÀÀName
C01 ÀÀÀÀÀÀÀÀÀD3
C02 ÀÀÀÀÀÀÀÀÀD1
C03 ÀÀÀÀÀÀONCE
C04ÀÀÀÀÀÀÀÀÀNC
C05ÀÀÀÀÀÀÀÀÀNC
Location ÀÀName
R01 ÀÀÀÀÀÀÀÀD24
R02 ÀÀÀÀÀÀÀÀD27
R03 ÀÀÀÀÀÀÀÀD31
R04ÀÀÀÀÀBTERM
R05 ÀÀÀÀÀÀHOLD
R06 ÀÀÀÀÀÀÀADS
G02ÀÀÀÀÀÀÀÀV
M02 ÀÀÀÀÀÀÀÀÀV
CC
CC
G03 ÀÀÀÀÀÀÀÀV
G15 ÀÀÀÀÀÀÀÀV
M03ÀÀÀÀÀÀÀÀÀÀV
M15ÀÀÀÀÀÀÀÀÀÀV
SS
SS
SS
CC
SS
G16 ÀÀÀÀÀÀÀÀÀA7
G17 ÀÀÀÀÀÀÀÀÀA8
M16 ÀÀÀÀÀÀÀÀÀV
C06 ÀÀÀÀÀÀÀÀV
M17ÀÀÀÀÀÀÀÀÀÀA14
CC
C07 ÀÀÀÀÀÀÀÀV
C08 ÀÀÀÀÀÀÀÀV
C09 ÀÀÀÀÀÀÀÀV
C10 ÀÀÀÀÀÀÀÀV
C11 ÀÀÀÀÀÀÀÀV
C12 ÀÀÀÀÀÀÀÀV
R07 ÀÀÀÀÀÀÀÀV
R08 ÀÀÀÀÀÀÀÀV
SS
SS
SS
SS
SS
SS
CC
CC
H01 ÀÀÀÀÀÀÀÀD11
H02 ÀÀÀÀÀÀÀÀD10
N01ÀÀÀÀÀÀÀÀÀÀD17
N02ÀÀÀÀÀÀÀÀÀÀD18
R09ÀÀÀÀÀÀÀÀBE0
H03 ÀÀÀÀÀÀÀÀV
H15 ÀÀÀÀÀÀÀÀV
N03ÀÀÀÀÀÀÀÀÀÀV
N15ÀÀÀÀÀÀÀÀÀÀV
R10 ÀÀÀÀÀÀÀÀV
R11 ÀÀÀÀÀÀÀÀV
SS
SS
CC
CC
CC
CC
CC
H16 ÀÀÀÀÀÀÀÀV
N16ÀÀÀÀÀÀÀÀÀÀA16
N17ÀÀÀÀÀÀÀÀÀÀA15
R12 ÀÀÀÀÀÀÀDMA
R13 ÀÀÀÀÀÀBREQ
R14 ÀÀÀÀÀÀÀÀA29
R15 ÀÀÀÀÀÀÀÀA26
R16 ÀÀÀÀÀÀÀÀA23
R17 ÀÀÀÀÀÀÀÀA22
C13ÀÀÀÀÀÀCLKIN
C14 ÀÀCLKMODE
C15 ÀÀÀÀÀÀXINT4
C16 ÀÀÀÀÀÀXINT6
C17 ÀÀÀÀÀÀXINT7
H17 ÀÀÀÀÀÀÀÀÀA9
J01 ÀÀÀÀÀÀÀÀD12
P01 ÀÀÀÀÀÀÀÀÀÀD19
P02 ÀÀÀÀÀÀÀÀÀÀD20
P03 ÀÀÀÀÀÀÀÀÀÀD22
P15 ÀÀÀÀÀÀÀÀÀÀA20
P16 ÀÀÀÀÀÀÀÀÀÀA19
P17 ÀÀÀÀÀÀÀÀÀÀA17
J02 ÀÀÀÀÀÀÀÀV
CC
J03 ÀÀÀÀÀÀÀÀV
SS
SS
CC
J15 ÀÀÀÀÀÀÀÀV
B01 ÀÀÀÀÀÀBOFF
B02 ÀÀÀÀÀSTEST
B03ÀÀÀÀÀÀÀÀÀNC
B04ÀÀÀÀÀÀÀÀÀNC
B05 ÀÀÀÀÀDREQ0
B06 ÀÀÀÀÀDREQ2
D01 ÀÀÀÀÀÀÀÀÀD5
D02 ÀÀÀÀÀÀÀÀÀD2
D03ÀÀÀÀÀÀÀÀÀNC
D15 ÀÀÀÀÀÀÀÀNMI
D16 ÀÀÀÀÀÀÀÀÀA2
D17 ÀÀÀÀÀÀÀÀÀA3
J16 ÀÀÀÀÀÀÀÀV
S01 ÀÀÀÀÀÀÀÀD25
S02 ÀÀÀÀÀÀÀÀD29
S03 ÀÀÀÀÀREADY
S04 ÀÀÀÀÀHOLDA
S05 ÀÀÀÀÀÀÀÀBE3
S06 ÀÀÀÀÀÀÀÀBE2
S07 ÀÀÀÀÀÀÀÀBE1
S08 ÀÀÀÀÀBLAST
S09 ÀÀÀÀÀÀÀDEN
S10 ÀÀÀÀÀÀÀW/R
S11ÀÀÀÀÀÀÀDT/R
S12ÀÀÀÀÀÀÀWAIT
S13 ÀÀÀÀÀÀÀÀD/C
S14 ÀÀÀÀÀÀLOCK
S15 ÀÀÀÀÀÀÀÀA31
S16 ÀÀÀÀÀÀÀÀA27
S17 ÀÀÀÀÀÀÀÀA25
J17 ÀÀÀÀÀÀÀÀA10
K01 ÀÀÀÀÀÀÀÀD13
Q01ÀÀÀÀÀÀÀÀÀÀD21
Q02ÀÀÀÀÀÀÀÀÀÀD23
Q03ÀÀÀÀÀÀÀÀÀÀD26
Q04ÀÀÀÀÀÀÀÀÀÀD28
Q05ÀÀÀÀÀÀÀÀÀÀD30
K02 ÀÀÀÀÀÀÀÀV
CC
K03 ÀÀÀÀÀÀÀÀV
SS
SS
CC
B07 ÀÀÀÀÀÀÀÀV
K15 ÀÀÀÀÀÀÀÀV
CC
B08 ÀÀÀÀÀDACK0
E01 ÀÀÀÀÀÀÀÀÀD7
E02 ÀÀÀÀÀÀÀÀÀD4
E03 ÀÀÀÀÀÀÀÀÀD0
K16 ÀÀÀÀÀÀÀÀV
B09 ÀÀÀÀÀÀÀÀV
K17 ÀÀÀÀÀÀÀÀA11
Q06ÀÀÀÀÀÀÀÀÀÀV
CC
CC
B10 ÀÀÀÀÀV
Q07ÀÀÀÀÀÀÀÀÀÀV
Q08ÀÀÀÀÀÀÀÀÀÀV
Q09ÀÀÀÀÀÀÀÀÀÀV
Q10ÀÀÀÀÀÀÀÀÀÀV
Q11ÀÀÀÀÀÀÀÀÀÀV
CCPLL
SS
SS
SS
SS
SS
B11 ÀÀÀÀÀÀÀÀV
E15 ÀÀÀÀÀÀÀÀV
L01 ÀÀÀÀÀÀÀÀD15
L02 ÀÀÀÀÀÀÀÀD14
CC
CC
CC
B12 ÀÀÀÀÀÀÀÀV
E16 ÀÀÀÀÀÀÀÀÀA4
E17 ÀÀÀÀÀÀÀÀÀA5
B13 ÀÀÀÀÀPCLK2
B14 ÀÀÀÀÀPCLK1
B15 ÀÀÀÀÀÀXINT0
B16 ÀÀÀÀÀÀXINT3
B17 ÀÀÀÀÀÀXINT5
L03 ÀÀÀÀÀÀÀÀV
L15 ÀÀÀÀÀÀÀÀV
SS
SS
F01 ÀÀÀÀÀÀÀÀÀD8
F02 ÀÀÀÀÀÀÀÀÀD6
L16 ÀÀÀÀÀÀÀÀA13
L17 ÀÀÀÀÀÀÀÀA12
Q12 ÀÀÀÀÀÀÀÀÀSUP
Q13ÀÀÀÀÀÀÀÀÀÀA30
Q14ÀÀÀÀÀÀÀÀÀÀA28
Q15ÀÀÀÀÀÀÀÀÀÀA24
Q16ÀÀÀÀÀÀÀÀÀÀA21
Q17ÀÀÀÀÀÀÀÀÀÀA18
F03 ÀÀÀÀÀÀÀÀV
CC
F15 ÀÀÀÀÀÀÀÀV
SS
F16 ÀÀÀÀÀÀÀÀV
CC
F17 ÀÀÀÀÀÀÀÀÀA6
15
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–3
Figure 4a. 80960CF PGA Pinout (View from Top Side)
16
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–4
Figure 4b. 80960CF PGA Pinout (View from Bottom Side)
17
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.4. Mechanical Data
3.4.1 CERAMIC PGA PACKAGE
271328–5
Family: Ceramic Pin Grid Array Package
Millimeters
Max
Inches
Max
Symbol
Min
3.56
0.64
23
Notes
Min
Notes
A
4.57
0.140
0.025
0.110
0.045
0.017
1.735
1.595
0.090
0.100
0.180
0.045
0.140
0.055
0.020
1.765
1.605
0.110
0.130
A
A
A
1.14
0.30
SOLID LID
SOLID LID
SOLID LID
SOLID LID
1
2
3
1.14
0.43
44.07
40.51
2.29
2.54
1.40
B
0.51
D
44.83
40.77
2.79
D
1
e
1
L
3.30
N
168
168
S
1
1.52
2.54
0.060
0.100
ISSUE
IWS REV X 7/15/88
Figure 5. 168-Lead Ceramic PGA Package Dimensions
18
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 7. Ceramic PGA Package Dimension Symbols
Letter or
Symbol
Description of Dimensions
A
Distance from seating plane to highest point of body
Distance between seating plane and base plane (lid)
Distance from base plane to highest point of body
Distance from seating plane to bottom of body
Diameter of terminal lead pin
A
A
A
1
2
3
B
D
Largest overall package dimension of length
D
A body length dimension, outer lead center to outer lead center
Linear spacing between true lead position centerlines
Distance from seating plane to end of lead
1
1
e
L
S
1
Other body dimension, outer lead center to edge of body
NOTES:
1. Controlling dimension: millimeter.
2. Dimension ‘‘e ’’ (‘‘e’’) is non-cumulative.
1
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.
4. Dimensions ‘‘B’’, ‘‘B ’’ and ‘‘C’’ are nominal.
1
5. Details of Pin 1 identifier are optional.
19
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.5. Package Thermal Specifications
Table 8 shows the maximum T allowable (without
A
exceeding T ) at various airflows and operating fre-
C
quencies (f
).
PCLK
The 80960CF is specified for operation when T
C
(the case temperature) is within the range of
b
a
Note that T is greatly improved by attaching fins or
A
a heat sink to the package. P (the maximum power
40 C– 110 C. T may be measured in any envi-
C
§
§
ronment to determine whether the 80960CF is within
specified operating range. The case temperature is
measured at the center of the top surface, opposite
the pins. Refer to Figure 7.
consumption) is calculated by using the typical I
as tabulated in Section 4.4, DC Specifications, and
CC
V
of 5V.
CC
T
A
(the ambient temperature) can be calculated
from i (thermal resistance from case to ambient)
CA
with the following equation:
e
b
P*i
T
A
T
C
CA
Table 8. Maximum T at Various Airflows In C (PGA Package Only)
A
§
Airflow-ft/min (m/sec)
f
PCLK
(MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
T
with
Heat Sink*
33
25
16
38
50
63
57
65
74
74
79
84
76
81
86
81
85
89
84
87
90
A
T
without
Heat Sink
33
25
16
18
34
51
33
46
60
47
57
68
57
65
74
66
72
80
67
74
81
A
*0.285 high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
×
PGA Thermal ResistanceÐ C/Watt
§
AirflowÐft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0) (1.01) (2.03) (3.07) (4.06) (5.07)
i Junction-to-Case
(Case Measured
as shown in Figure 7)
1.5
17
13
1.5
14
9
1.5
11
1.5
9
1.5
7.1
3.9
1.5
6.6
3.4
i Case-to-Ambient
(No Heatsink)
271328–6
i Case-to-Ambient
(with Unidirectional)
Heatsink)*
5.5
5.0
NOTES:
1. This table applies to 80960CF PGA plugged into socket or soldered directly
into board.
e
a
§
2. i
3. i
i
i
e
e
e
i
4 C/W (approx.)
.
JA
JC
CA
J-CAP
J-PIN
J-PIN
4 C/W (inner pins) (approx.)
8 C/W (outer pins) (approx.)
§
§
i
* 0.285 high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil
×
center-to-center fin spacing).
Figure 6. 80960CF PGA Package Thermal Characteristics
20
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.7 Suggested Sources for 80960CF
Accessories
The following are some suggested sources of ac-
cessories for the 80960CF. They are neither an
endorsement of any kind, nor a warranty of the
performance of any of the listed products and/or
companies.
Sockets
1. 3M Textool Test and Interconnection Products
Department
P.O. Box 2963
Austin, TX 78769-2963
2. Augat, Inc.
Interconnection Products Group
33 Perry Avenue
P.O. Box 779
271328–7
Attleboro, MA 02703
(508) 222-2202
Figure 7. Measuring 80960CF PGA Case
Temperature
3. Concept Manufacturing Inc.
(Decoupling Sockets)
43024 Christy Street
Fremont, CA 94538
(415) 651-3804
3.6 Stepping Register Information
Upon Reset, Register G0 contains die stepping in-
formation. The following figure shows how G0 is
configured. The most significant byte contains an
ASCII 0. The upper middle byte contains an ASCII C.
The lower middle byte contains an ASCII F. The
least significant byte contains the stepping number
in ASCII. G0 retains this information until it is written
over by the user program.
Heat Sinks/Fins
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75381-0839
(214) 243-4321
Table 9 contains a cross reference of the number in
the least significant byte of register G0 to the die
stepping number.
2. E G & G Division
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
ASCII
00
0
43
C
46
F
Stepping Number
Stepping Number
LSB
DECIMAL
MSB
Figure 8. Register G0
Table 9. Die Stepping Cross Reference
G0 Least
Die Stepping
Significant Byte
01
02
03
04
05
A
B
C
D
E
21
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
Parameter
Maximum Rating
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
b
b
a
65 C to 150 C
Storage Temperature
§
§
(2)
a
40 C to 125 C
Case Temperature Under Bias
§
§
a
0.5V to 6.5V
Supply Voltage wrt. V
SS
b
a
0.5V
Voltage on Other pins wrt V
SS
0.5V to V
CC
4.2. Operating Conditions
Operating Conditions (80960CF-33, -25, -16)
Symbol
Parameter
Min
Max
Units
Notes
V
Supply Voltage
80960CF-30
80960CF-25
80960CF-16
4.75
4.50
4.50
5.25
5.50
5.50
CC
V
f
f
Input Clock Frequency (2-x Mode)
Input Clock Frequency (1-x Mode)
80960CF-30
80960CF-25
80960CF-16
0
0
0
60.6
50
MHz
MHz
MHz
CLK2x
CLK1x
32
80960CF-30
80960CF-25
80960CF-16
8
8
8
30.3
25
MHz
MHz
MHz
(1)
16
b
a
110
T
C
Case Temperature Under Bias
80960CF-30, -25, -16
PGA Package
40
C
§
NOTES:
(1) When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum
frequency of 8 MHz for proper processor operation. However, in the 1-x Mode, CLKIN may still be stopped when the
processor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once
CLKIN restarts and has stabilized.
(2) Case temperatures are ‘‘Instant On’’.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical per-
4.3 Recommended Connections
formance. Inductance can be reduced by shortening
board traces between the processor and decoupling
capacitors as much as possible. Capacitors specifi-
cally designed for PGA packages will offer the low-
est possible inductance.
Power and ground connections must be made to
multiple V and V (GND) pins. Every 80960CF-
based circuit board should include power (V ) and
CC
SS
CC
ground (V ) planes for power distribution. Every
SS
pin must be connected to the power plane, and
V
CC
every V
pin must be connected to the ground
SS
For reliable operation, always connect unused in-
puts to an appropriate signal level. In particular, any
unused interrupt (XINT, NMI) or DMA (DREQ) input
plane. Pins identified as ‘‘N.C.’’ must not be con-
nected in the system.
should be connected to V through a pull-up resis-
CC
Liberal decoupling capacitance should be placed
near the 80960CF. The processor can cause tran-
sient power surges when its numerous output buff-
ers transition, particularly when connected to large
capacitive loads.
tor, as should BTERM if not used. Pull-up resistors
should be in the range of 20 KX for each pin tied
high. If READY or HOLD are not used, the unused
input should be connected to ground. N.C. pins
must always remain unconnected. Refer to the
i960 CA Microprocessor Reference Manual for more
information.
22
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
4.4. DC Specifications
DC Characteristics
(80960CF-30, -25, -16 under the conditions described in Section 4.2, Operating Conditions.)
Symbol
Parameter
Min
Max
0.8
a
Units
Notes
b
V
IL
Input Low Voltage for all pins except RESET
Input High Voltage for all pins except RESET
Output Low Voltage
0.3
V
V
V
V
IH
2.0
V
V
0.3
0.3
CC
e
V
0.45
I
5 mA
OL
OH
OL
e b
e b
V
Output High Voltage
I
I
1mA
200mA
2.4
b
V
V
OH
OH
V
0.5
CC
b
0.3
3.5
V
Input Low Voltage for RESET
Input High Voltage for RESET
1.5
V
V
ILR
IHR
LI1
a
V
CC
I
Input Leakage Current for each pinexcept:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0,
s
s
V
CC
g
READY, HOLD, BOFF, CLKMODE
15
mA
0V
V
IN
(1)
I
I
Input Leakage Current for:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF
LI2
LI3
b
e
0.45V (2)
0
0
325
mA
mA
V
IN
Input Leakage Current for:
READY, HOLD, CLKMODE
e
500
V
2.4V (3)
IN
s
s
g
I
Output Leakage Current
15
mA 0.45V
V
V
CC
LO
OUT
I
I
I
Supply Current (80960CF-30)
CC
I
I
Max
Typ
1150
960
mA
(4)
(5)
CC
CC
Supply Current (80960CF-25)
CC
CC
I
I
Max
Typ
950
775
mA
(4)
(5)
CC
CC
Supply Current (80960CF-16)
I
I
Max
Typ
750
575
mA
mA
(4)
(5)
CC
CC
I
ONCE-mode Supply Current
150
ONCE
C
Input Capacitance for:
CLKIN, RESET, ONCE,
IN
READY, HOLD, DREQ3:0, BOFF
XINT7:0, NMI, BTERM, CLKMODE
e
0
12
12
12
pF
pF
pF
F
1 MHz
C
e
C
Output Capacitance of each output pin
I/O Pin Capacitance
F
C
1 MHz, (6)
OUT
e
1 MHz
C
F
I/O
NOTES:
(1) No Pull-up or pull-down.
C
(2) These pins have internal pullup resistors.
(3) These pins have internal pulldown resistors.
(4) Measured at worst case frequency, V and temperature, with device operating and outputs loaded to the test conditions
CC
described in Section 4.5.1, AC Test Conditions.
(5) I Typical is not tested.
(6) Output Capacitance is the capacitive load of a floating output.
CC
(7) CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.
23
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
4.5 AC Specifications
AC Characteristics Ð 80960CF-30
(80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.) See notes which follow this table.
Symbol
Parameter
Min
Max
Units
Notes
(10)
INPUT CLOCK
T
CLKIN Frequency
CLKIN Period
0
60.6
MHz
(1)
F
T
In 1-x Mode (f
In 2-x Mode (f
)
)
33
16.5
125
%
ns
ns
(1,12)
(1)
C
CLK1x
CLK2x
g
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
0.1%
D
(1,13)
CS
CLK1x
In 1-x Mode (f
In 2-x Mode (f
)
)
6
6
62.5
%
ns
ns
(1,12)
(1)
CH
CLK1x
CLK2x
T
CLKIN Low Time
CLKIN Rise Time
In 1-x Mode (f
In 2-x Mode (f
)
)
6
6
62.5
%
ns
ns
(1,12)
(1)
CL
CLK1x
CLK2x
T
0
0
6
6
ns
ns
(1)
(1)
CR
T
CLKIN Fall Time
CF
(9)
OUTPUT CLOCKS
b
2
T
CLKIN to PCLK2:1 Delay In 1-x Mode (f
In 2-x Mode (f
)
)
2
2
25
ns
ns
(1,3,13,14)
(1,3)
CP
CLK1x
CLK2x
T
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
)
T
2T
ns
ns
(1,13)
(1,3)
CLK1x
CLK2x
C
C
b
b
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
(T/2)
(T/2)
2
2
T/2
T/2
4
ns
ns
ns
ns
(1,13)
(1,13)
(1,3)
PH
T
PL
T
1
PR
T
PCLK2:1 Fall Time
1
4
(1,3)
PF
(10)
SYNCHRONOUS OUTPUTS
T
T
Output Valid Delay, Output Hold
(6, 11)
OV
OH
T
T
T
T
T
T
T
T
T
T
T
T
T
T
, T
A31:2
BE3:0
ADS
3
3
6
3
4
5
3
4
4
4
3
14
16
18
18
16
16
16
16
16
18
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OV1 OH1
, T
OV2 OH2
, T
OV3 OH3
, T
W/R
OV4 OH4
, T
D/C, SUP, DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
OV5 OH5
, T
OV6 OH6
, T
OV7 OH7
, T
OV8 OH8
, T
OV9 OH9
, T
DACK3:0
D31:0
DT/R
FAIL
EOP/TC3:0
OV10 OH10
, T
OV11 OH11
, T
a
a
14
18
T/2
3
T/2
14
OV12 OH12
, T
2
3
(6, 11)
(6)
OV13 OH13
, T
OV14 OH14
T
Output Float for all outputs
3
22
ns
OF
(10)
SYNCHRONOUS INPUTS
T
Input Setup
IS
T
IS1
T
IS2
T
IS3
T
IS4
D31:0
BOFF
BTERM/READY
HOLD
3
17
7
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
7
T
Input Hold
IH
T
IH1
T
IH2
T
IH3
T
IH4
D31:0
BOFF
BTERM/READY
HOLD
5
5
2
3
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
24
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
AC Characteristics Ð 80960CF-30
(80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.) See notes which follow this table. (Continued)
Symbol
Parameter
(9,7)
Min
Max
Units
Notes
RELATIVE OUTPUT TIMINGS
b
a
T
T
A31:2 Valid to ADS Rising
T
4
T
4
ns
AVSH1
AVSH2
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
b
b
a
a
T
T
6
4
T
T
6
4
ns
ns
T
T
A31:2 Valid to DEN Falling
AVEL1
BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling
AVEL2
b
a
T
6
T
6
ns
ns
ns
ns
ns
ns
ns
g
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
6
NLQV
DVNH
NLNH
b
a
6
T
T
T
N*T
6
N*T
(4)
(4)
(5)
(6)
(7)
g
N*T
4
a
b
a
a
1) * T 6
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
(N
1) * T
6
(N
NHQX
b
%
T
T/2
6
EHTV
b
a
4
T
DT/R Valid to DEN Falling
T/2
4
T/2
TVEL
(7)
RELATIVE INPUT TIMINGS
T
IS5
T
IH5
T
IS6
T
IH6
T
IS7
T
IH7
T
IS8
T
IH8
RESET Input Setup (2x Clock Mode)
RESET Input Hold (2x Clock Mode)
DREQ3:0 Input Setup
6
ns
ns
ns
ns
ns
ns
ns
ns
(14)
(14)
(8)
5
12
7
DREQ3:0 Input Hold
(8)
XINT7:0, NMI Input Setup
7
(8)
XINT7:0, NMI Input Hold
3
(8)
RESET Input Setup (1x Clock Mode)
RESET Input Hold (1x Clock Mode)
3
(15)
(15)
a
T/4
1
NOTES:
1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
2. See Figure 22 for capacitive derating information for output delays and hold times.
3. See Figure 23 for capacitive derating information for rise and fall times.
4. Where N is the number of N
, N
RAD
, N
RDD
, or N
WAD
wait states that are programmed in the Bus Controller Region
WDD
Table. When there are no wait states in an access, WAIT never goes active.
e
5. N
Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. See Notes 1, 2 and 3.
8. Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order
to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1
the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising
edges to be seen by the processor.
9. These specifications are guaranteed by the processor.
10. These specifications must be met by the system for proper operation of the processor.
11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for
PCLK2:1 loading.
12. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
13. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than
g
0.1% between adjacent cycles.
14. In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup
and hold times to the falling edge of the CLKIN. (See Figure 28a.)
15. In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted
while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)
25
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
AC Characteristics Ð 80960CF-25
(80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.)
Symbol
Parameter
Min
Max
Units
Notes
(10)
INPUT CLOCK
T
T
CLKIN Frequency
CLKIN Period
0
50
MHz
(1)
F
In 1-x Mode (f
In 2-x Mode (f
)
)
40
20
125
%
ns
ns
(1,12)
(1)
C
CLK1x
CLK2x
g
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
0.1%
D
(1,13)
CS
CH
CLK1x
In 1-x Mode (f
In 2-x Mode (f
)
)
8
8
62.5
%
ns
ns
(1,12)
(1)
CLK1x
CLK2x
T
CLKIN Low Time
In 1-x Mode (f
In 2-x Mode (f
)
)
8
8
62.5
%
ns
ns
(1,12)
(1)
CL
CLK1x
CLK2x
T
T
CLKIN Rise Time
CLKIN Fall Time
0
0
6
6
ns
ns
(1)
(1)
CR
CF
(9)
OUTPUT CLOCKS
b
2
T
T
CLKIN to PCLK2:1 Delay In 1-x Mode (f
In 2-x Mode (f
)
)
2
2
25
ns
ns
(1,3,13,14)
(1,3)
CP
CLK1x
CLK2x
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
)
T
2T
ns
ns
(1,13)
(1,3)
CLK1x
CLK2x
C
C
b
b
T
T
T
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
PCLK2:1 Fall Time
(T/2)
(T/2)
3
3
T/2
T/2
4
ns
ns
ns
ns
(1,13)
(1,13)
(1,3)
PH
PL
PR
PF
1
1
4
(1,3)
(10)
SYNCHRONOUS OUTPUTS
T
T
Output Valid Delay, Output Hold
(6, 11)
OV
OH
T
T
T
T
T
T
T
T
T
T
T
T
T
T
, T
A31:2
BE3:0
ADS
3
16
18
20
20
18
18
18
18
18
20
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OV1 OH1
, T
3
6
3
4
5
3
4
4
4
3
OV2 OH2
, T
OV3 OH3
, T
W/R
OV4 OH4
, T
D/C,SUP,DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
OV5 OH5
, T
OV6 OH6
, T
OV7 OH7
, T
OV8 OH8
, T
OV9 OH9
, T
DACK3:0
D31:0
DT/R
OV10 OH10
, T
OV11 OH11
, T
a
a
16
20
T/2
3
T/2
16
OV12 OH12
, T
FAIL
EOP3:0/TC3:0
2
3
OV13 OH13
, T
(6, 11)
(6)
OV14 OH14
T
T
Output Float for all outputs
3
22
ns
OF
IS
(10)
SYNCHRONOUS INPUTS
Input Setup
T
IS1
T
IS2
T
IS3
T
IS4
D31:0
BOFF
BTERM/READY
HOLD
5
19
9
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
9
T
Input Hold
IH
T
IH1
T
IH2
T
IH3
T
IH4
D31:0
BOFF
BTERM/READY
HOLD
5
7
2
5
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
26
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
AC Characteristics Ð 80960CF-25
(80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.) (Continued)
Symbol
Parameter
Min
Max
Units
Notes
(9,7)
RELATIVE OUTPUT TIMINGS
b
a
T
T
A31:2 Valid to ADS Rising
T
4
T
4
ns
AVSH1
AVSH2
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
b
b
a
a
T
T
6
4
T
T
6
4
ns
ns
T
T
A31:2 Valid to DEN Falling
AVEL1
BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling
AVEL2
b
a
T
6
T
6
ns
ns
ns
ns
ns
ns
ns
g
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
6
NLQV
DVNH
NLNH
b
a
6
T
T
T
N*T
6
N*T
(4)
(4)
(5)
(6)
(7)
g
N*T
4
a
b
a
a
1) * T 6
(N
1) * T
6
(N
NHQX
b
%
T
T/2
6
EHTV
b
a
4
T
DT/R Valid to DEN Falling
T/2
4
T/2
TVEL
(7)
RELATIVE INPUT TIMINGS
T
RESET Input Setup (2x Clock Mode
8
7
ns
ns
ns
ns
ns
ns
ns
ns
(14)
(14)
(8)
IS5
IH5
IS6
IH6
IS7
IH7
IS8
IH8
T
T
T
T
T
T
T
RESET Input Hold (2x Clock Mode)
DREQ3:0 Input Setup
14
9
DREQ3:0 Input Hold
(8)
XINT7:0, NMI Input Setup
9
(8)
XINT7:0, NMI Input Hold
5
(8)
RESET Input Setup (1x Clock Mode)
RESET Input Hold (1x Clock Mode)
3
(15)
(15)
a
T/4
1
NOTES:
(1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
(2) See Figure 22 for capacitive derating information for output delays and hold times.
(3) See Figure 23 for capacitive derating information for rise and fall times.
(4) Where N is the number of N
, N
RAD
, N
RDD
, or N
WAD
wait states that are programmed in the Bus Controller Region
WDD
Table. When there are no wait states in an access, WAIT never goes active.
e
(5) N
Number of wait states inserted with READY.
(6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
(7) See Notes 1, 2 and 3.
(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in
order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of
PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1
rising edges to be seen by the processor.
(9) These specifications are guaranteed by the processor.
(10) These specifications must be met by the system for proper operation of the processor.
(11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for
PCLK2:1 loading.
(12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
(13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than
g
0.1% between adjacent cycles.
(14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and
hold times to the falling edge of the CLKIN. (See Figure 28a.)
(15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted
while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)
27
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
AC Characteristics Ð 80960CF-16
(80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.) (Continued)
Symbol
Parameter
Min
Max
Units
Notes
(10)
INPUT CLOCK
T
CLKIN Frequency
CLKIN Period
0
32
MHz
(1)
F
T
C
In 1-x Mode (f
In 2-x Mode (f
)
)
62.5
31.25
125
%
ns
ns
(1,12)
(1)
CLK1x
CLK2x
g
T
T
CLKIN Period Stability
CLKIN High Time
In 1-x Mode (f
)
0.1%
D
(1,13)
CS
CLK1x
In 1-x Mode (f
In 2-x Mode (f
)
)
10
10
62.5
%
ns
ns
(1,12)
(1)
CH
CLK1x
CLK2x
T
CLKIN Low Time
In 1-x Mode (f
In 2-x Mode (f
)
)
10
10
62.5
%
ns
ns
(1,12)
(1)
CL
CLK1x
CLK2x
T
CLKIN Rise Time
CLKIN Fall Time
0
0
6
6
ns
ns
(1)
(1)
CR
T
CF
(9)
OUTPUT CLOCKS
b
2
T
CLKIN to PCLK2:1 Delay In 1-x Mode (f
In 2-x Mode (f
)
)
2
2
25
ns
ns
(1,3,13,14)
(1,3)
CP
CLK1x
CLK2x
T
PCLK2:1 Period
In 1-x Mode (f
In 2-x Mode (f
)
)
T
2T
ns
ns
(1,13)
(1,3)
CLK1x
CLK2x
C
C
b
b
T
PCLK2:1 High Time
PCLK2:1 Low Time
PCLK2:1 Rise Time
PCLK2:1 Fall Time
(T/2)
(T/2)
4
4
T/2
T/2
4
ns
ns
ns
ns
(1,13)
(1,13)
(1,3)
PH
T
PL
T
1
PR
T
1
4
(1,3)
PF
(10)
SYNCHRONOUS OUTPUTS
T
T
Output Valid Delay, Output Hold
(6, 11)
OV
OH
T
T
T
T
T
T
T
T
T
T
T
T
T
T
, T
OV1 OH1
, T
A31:2
BE3:0
ADS
3
18
20
22
22
20
20
20
20
20
22
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
6
3
4
5
3
4
4
4
3
OV2 OH2
, T
OV3 OH3
, T
W/R
OV4 OH4
, T
D/C, SUP, DMA
BLAST, WAIT
DEN
OV5 OH5
, T
OV6 OH6
, T
OV7 OH7
, T
HOLDA, BREQ
LOCK
OV8 OH8
, T
OV9 OH9
, T
DACK3:0
D31:0
DT/R
OV10 OH10
, T
OV11 OH11
, T
a
a
18
22
T/2
3
T/2
18
OV12 OH12
, T
FAIL
EOP3:0/TC3:0
2
3
OV13 OH13
, T
(6, 11)
(6)
OV14 OH14
T
Output Float for all outputs
3
22
ns
OF
(10)
SYNCHRONOUS INPUTS
T
Input Setup
IS
T
T
T
T
D31:0
5
21
9
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
IS1
IS2
IS3
IS4
BOFF
BTERM/READY
HOLD
9
T
Input Hold
IH
T
T
T
T
D31:0
BOFF
BTERM/READY
HOLD
5
7
2
5
ns
ns
ns
ns
(1,11)
(1,11)
(1,11)
(1,11)
IH1
IH2
IH3
IH4
28
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
AC Characteristics Ð 80960CF-16
(80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,
AC Test Conditions.) (Continued)
Symbol
Parameter
Min
Max
Units
Notes
(9,7)
RELATIVE OUTPUT TIMINGS
b
a
T
T
A31:2 Valid to ADS Rising
T
4
T
4
ns
AVSH1
AVSH2
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
b
b
a
a
T
T
6
6
T
T
6
6
ns
ns
T
T
A31:2 Valid to DEN Falling
AVEL1
AVEL2
BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling
b
a
T
6
T
6
ns
ns
ns
ns
ns
ns
ns
g
T
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
Output Data Hold after WAIT Rising
DT/R Hold after DEN High
6
NLQV
DVNH
NLNH
b
a
6
T
T
T
N*T
6
N*T
(4)
(4)
(5)
(6)
(7)
g
N*T
4
a
b
a
a
1) * T 6
(N
1) * T
6
(N
NHQX
b
%
T
T/2
6
EHTV
b
a
4
T
DT/R Valid to DEN Falling
T/2
4
T/2
TVEL
(7)
RELATIVE INPUT TIMINGS
T
RESET Input Setup (2x Clock Mode)
10
9
ns
ns
ns
ns
ns
ns
ns
ns
(14)
(14)
(8)
IS5
IH5
IS6
IH6
IS7
IH7
IS8
IH8
T
T
T
T
T
T
T
RESET Input Hold (2x Clock Mode)
DREQ3:0 Input Setup
16
11
9
DREQ3:0 Input Hold
(8)
XINT7:0, NMI Input Setup
(8)
XINT7:0, NMI Input Hold
5
(8)
RESET Input Setup (1x Clock Mode)
RESET Input Hold (1x Clock Mode)
3
(15)
(15)
a
T/4
1
NOTES:
(1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
(2) See Figure 22 for capacitive derating information for output delays and hold times.
(3) See Figure 23 for capacitive derating information for rise and fall times.
(4) Where N is the number of N
, N
RAD
, N
RDD
, or N
WAD
wait states that are programmed in the Bus Controller Region
WDD
Table. When there are no wait states in an access, WAIT never goes active.
e
(5) N
Number of wait state inserted with READY.
(6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
(7) See Notes 1, 2 and 3.
(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in
order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of
PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1
rising edges to be seen by the processor.
(9) These specifications are guaranteed by the processor.
(10) These specifications must be met by the system for proper operation of the processor.
(11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Figure 22 to adjust the timing for
PCLK2:1 loading.
(12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
(13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than
g
0.1% between adjacent cycles.
(14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and
hold times to the falling edge of the CLKIN. (See Figure 28a.)
(15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted
while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)
29
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
4.5.1. AC TEST CONDITIONS
The AC Specifications in Section 4.5 are tested with
the 50 pf load shown in Figure 9. See Figure 16 to
see how timings vary with load capacitance.
Specifications are measured at the 1.5V crossing
point, unless otherwise indicated. Input waveforms
s
are assumed to have a rise-and-fall time of
2 ns
from 0.8V to 2.0V. See Section 4.5.2, AC Timing
Waveforms for AC spec definitions, test points and
illustrations.
e
CL 50 pf for all signals
271328–8
Figure 9. AC Test Load
4.5.2. AC TIMING WAVEFORMS
271328–9
Figure 10a. Input and Output Clocks Waveform
271328–10
Figure 10b. CLKIN Waveform
30
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–11
Figure 11. Output Delay and Float Waveform
271328–12
Figure 12a. Input Setup and Hold Waveform
271328–13
271328–14
Figure 12b. NMI, XINT7:0 Input Setup and Hold Waveform
31
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–15
Figure 13. Hold Acknowledge Timings
271328–16
Figure 14. Bus Back-Off (BOFF) Timings
32
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–17
Figure 15. Relative Timings Waveforms
4.5.3 DERATING CURVES
271328–18
NOTE:
PCLK Load
e
50 pF
Figure 16. Output Delay or Hold vs Load Capacitance
33
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
(a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ,
DACK3:0, EOP3:0/TC3:0, FAIL
(b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0,
EOP3:0/TC3:0, FAIL
271328–19
Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
271328–20
I
ÐI under test conditions
CC CC
Figure 18. I vs Frequency and Temperature
CC
34
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
The following table lists the condition of each proc-
essor output pin while HOLDA is asserted (low).
5.0 RESET, BACKOFF AND HOLD
ACKNOWLEDGE
Table 11. Hold Acknowledge
and Backoff Conditions
The following table lists the condition of each proc-
essor output pin while RESET is asserted (low).
Pins
A31:A2
D31:D0
BE3:0
State During HOLDA
Floating
Table 10. Reset Conditions
Pins
State During Reset
1
(HOLDA inactive)
Floating
A31:A2
D31:D0
BE3:0
Floating
Floating
Floating
W/R
Floating
Driven high (Inactive)
Driven low (Read)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Active)
Driven low (Receive)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Inactive)
Floating
ADS
Floating
W/R
WAIT
Floating
ADS
BLAST
DT/R
Floating
WAIT
Floating
BLAST
DT/R
DEN
Floating
LOCK
Floating
DEN
BREQ
D/C
Driven (high or low)
Floating
LOCK
BREQ
D/C
DMA
Floating
SUP
Floating
DMA
Floating
FAIL
Driven high (Inactive)
Driven high (Inactive)
Driven high (Inactive)
Driven high (Inactive)
Driven high (Inactive)
Driven if output
Driven if output
Driven if output
Driven if output
SUP
Floating
DACK3
DACK2
DACK1
DACK0
EOP/TC3
EOP/TC2
EOP/TC1
EOP/TC0
FAIL
Driven low (Active)
Driven high (Inactive)
Driven high (Inactive)
Driven high (Inactive)
Driven high (Inactive)
Floating (set to input mode)
Floating (set to input mode)
Floating (set to input mode)
Floating (set to input mode)
DACK3
DACK2
DACK1
DACK0
EOP/TC3
EOP/TC2
EOP/TC1
EOP/TC0
NOTE:
(1) With regard to bus output pin state only, the Hold Ac-
knowledge state takes precedence over the reset state. Al-
though asserting the RESET pin will internally reset the
processor, the processor’s bus output pins will not enter
the reset state if it has granted Hold Acknowledge to a pre-
vious HOLD request (HOLDA is active). Furthermore, the
processor will grant new HOLD requests and enter the
Hold Acknowledge state even while in reset.
For example, if HOLDA is not active and the processor is
in the reset state, then HOLD is asserted, the processor’s
bus pins will enter the Hold Acknowledge state and
HOLDA will be granted. The processor will not be able to
perform memory accesses until the HOLD request is re-
moved, even if the RESET pin is brought high. This opera-
tion is provided to simplify boot-up synchronization among
multiple processors sharing the same bus.
35
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
6.0 BUS WAVEFORMS
Figure 19. Cold Reset Waveform
36
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Figure 20. Warm Reset Waveform
37
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Figure 21. Entering the ONCE State
38
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–24
NOTE:
Case 1 and Case 2 show two possible polarities of PCLK2:1.
Figure 22a. Clock Synchronization in the 2x Clock Mode
271328–25
NOTE:
In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2XCLK. 2XCLK is an internal signal generat-
ed by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN.
The RESET pin is sampled when PCLK is high.
Figure 22b. Clock Synchronization in the 1x Clock Mode
39
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–26
Figure 23. Non-Burst, Non-Pipelined Requests without Wait States
40
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–27
Figure 24. Non-Burst, Non-Pipelined Read Request with Wait States
41
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–28
Figure 25. Non-Burst, Non-Pipelined Write Request with Wait States
42
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–29
Figure 26. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus
43
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–30
Figure 27. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus
44
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–31
Figure 28. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus
45
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–32
Figure 29. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus
46
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–33
Figure 30. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus
47
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–34
Figure 31. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus
48
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–35
Figure 32. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
49
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–36
Figure 33. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
50
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–37
Figure 34. Burst, Pipelined Read Request without Wait States, 32-Bit Bus
51
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–38
Figure 35. Burst, Pipelined Read Requests with Wait States, 32-Bit Bus
52
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–39
Figure 36. Burst, Pipelined Read Requests with Wait States, 16-Bit Bus
53
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Region Table Entry
271328–40
Figure 37. Burst, Pipelined Read Requests with Wait States, 8-Bit Bus
54
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–41
Figure 38. Using External READY
55
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–42
NOTE:
READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts
a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM
signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access.
Figure 39. Terminating a Burst with BTERM
56
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–43
Figure 40. BOFF Functional Timing
271328–44
Figure 41. HOLD Functional Timing
57
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–45
NOTES:
1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-by and some packing and unpacking
modes, in which loads are followed by loads, or stores are followed by stores.
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. Applications are non
fly-by transfers and adjacent load-stores or store-loads.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined
by ADS and BLAST. Refer to User’s Manual for ‘‘access’’, ‘‘request’’ definition.
Figure 42. DREQ and DACK Functional Timing
271328–46
NOTE:
EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests.
EOP is NOT edge triggered. EOP must be held for a minimum of 2 clock cycles then EOP must be deasserted
within 15 clock cycles.
Figure 43. EOP Functional Timing
58
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–47
NOTE:
Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is
executed as multiple bus accesses, the TC will be active for the entire bus request. Refer to the User’s Manual for
further information.
Figure 44. Terminal Count Functional Timing
271328–48
Figure 45. FAIL Functional Timing
59
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–49
Figure 46. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
60
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328–50
Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
61
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Figure 48. Idle Bus Operation
62
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